JPH07123128B2 - Field-effect semiconductor device and method of manufacturing the same - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a field effect semiconductor device using a semi-insulating compound semiconductor substrate and a method for manufacturing the same.

[Technical background of the invention and its problems]

A Schottky gate type field effect transistor (MESFET) using a semi-insulating GaAs substrate is known as shown in FIG. In the figure, 31 is a semi-insulating GaAs substrate, an n-type operating layer 32 is formed on the surface thereof, and a gate electrode 33 forming a Schottky barrier is formed with this operating layer 32. The n ⁺ type source region 34 and the drain region 35 are formed in self-alignment with the gate electrode 33 by ion implantation, and the source electrode 36 and the drain electrode are formed on the respective surfaces.
37 are formed. When such a GaAs-MESFET is miniaturized, the distance between the source electrode 36 and the drain electrode 37 becomes narrower, and the effect of applying a high electric field between them and the effect that the source region 34 and the drain region 35 are extremely close to each other are combined, In addition to the current flowing through the operating layer 32 that is a channel, the current flowing through the substrate 31 increases. As a result, there are problems that the threshold voltage of the MESFET is lowered, the drain conductance is increased, and the mutual conductance is lowered. In particular, MESFET using a semi-insulating substrate is a Si-MO using a conductive substrate.
Unlike SFET and the like, the potential barrier between the source / drain region and the substrate is low, so the above problems associated with shortening the channel become prominent.

Therefore, a structure has been proposed in which a p-layer serving as a potential barrier is formed around the source / drain regions as shown in FIGS. However, in the structure as shown in FIG. 5, the junction area between the source / drain regions 14 and 15 and the p-type layers 16 and 17 is large.
Further, in the structure shown in FIG. 6 proposed by the proponents (Japanese Patent Application No. 59-231711), there is a problem that the effect as a barrier is insufficient because the p-type regions 6 and 17 are extremely small. It was

[Object of the Invention]

In view of the above points, an object of the present invention is to provide a field effect semiconductor device using a semi-insulating compound semiconductor substrate and a method for manufacturing the same, which solves the problem of characteristic deterioration due to miniaturization.

[Outline of Invention]

In the field effect semiconductor device according to the present invention, a first conductivity type operation layer is formed on a surface portion of a semi-insulating compound semiconductor substrate,
In the structure in which the source / drain regions having the same conductivity type as the operating layer and deep and high concentration are formed in a self-aligning manner with the gate electrode formed on the surface thereof, the first electrode below the side portion of the gate electrode is formed.
It is characterized in that a barrier layer of the second conductivity type is formed deeper than the source / drain regions at the junction between the conductivity type layer and the substrate.

In addition, according to the method of the present invention for manufacturing such a field effect semiconductor device, after the source / drain regions of the first conductivity type are formed by ion implantation of impurities using the gate electrode as a mask, the sidewalls of the gate electrode are selectively etched. After forming an insulating film on the first insulating film, another insulating film is formed, and only the side wall portion is removed to form a second film at the joint between the first conductivity type layer and the substrate through the opening.
It is characterized in that the barrier layer of conductivity type is formed deeper than the source / drain regions.

The step of forming the side wall may be performed before forming the source / drain regions.

〔The invention's effect〕

The field-effect semiconductor device according to the present invention can control the current flowing through the semi-insulating substrate below the operation layer that is the channel region even when miniaturized. As a result,
A high-performance field-effect semiconductor device can be obtained by preventing a decrease in threshold voltage, an increase in drain conductance, and a decrease in mutual conductance due to a shortened channel. In the present invention, the barrier layer that suppresses the substrate current is
The area in contact with the N ⁺ layer is small, and moreover, the area necessary for sufficiently exerting the effect as a barrier can be secured. Therefore, the device and method of the present invention can realize a high-performance device, and when applied to an integrated circuit, high speed operation,
High integration is possible.

Example of Invention

 Examples of the present invention will be described below.

FIG. 1 shows a GaAs-MESFET of one embodiment. 11 is resistivity 10
It is a semi-insulating GaAs substrate of about ⁷ to 10 ⁸ Ω · cm, the n-type operating layer 12 to be the channel region is formed on the surface, and the surface is a Schottky gate made of 4000 Å tungsten nitride (WNx). The electrode 13 is formed. Gate electrode
The operating layer 12 is formed by ion implantation on both sides of the substrate with 13 in between.
Higher concentration and deep n ⁺ type source region 14 and drain region 15
Are formed. These source / drain regions 14, 15
In the boundary portion with the substrate 11 in the portion close to the gate electrode of
P-type barrier layers 16 and 17 that form a high barrier against carrier injection (electron injection in this embodiment) from the source / drain regions 14 and 15 into the substrate 11 are formed. Reference numerals 18 and 19 denote source / drain electrodes, respectively.

An example of manufacturing such a MESFET is shown in FIG.
Next, description will be made with reference to (e). First, the n-type operating layer 12 is formed by implanting Si ions into the semi-insulating GaAs substrate 11 under the conditions of 50 KeV and 2.0 × 10 ¹² / cm ² . Then on this board
A WNx film having a thickness of 4000 liters is formed, and a gate electrode 13 having a width of 1.0 μm is formed by using a known photolithography technique and dry etching technique. Using this gate electrode as a mask, Si ions are further ion-implanted under the conditions of 180 KeV and 3 × 10 ¹³ / cm ² to form source / drain regions 14 and 15 (FIG. 2 (a)). After that, the entire surface of the substrate is plasma-enhanced by SiO ₂ to form SiO _2.
A film of 4000 Å is deposited and this SiO ₂ film is etched by an amount corresponding to the film thickness by anisotropic dry etching such as RIE. The SiO ₂ film formed by plasma CVD isotropically deposited to form the gate electrode 13
Since the same thickness is formed on the side walls of the SiO ₂ film, the entire surface of the SiO ₂ film is anisotropically etched to selectively leave the SiO ₂ film 20 only on the side walls of the gate electrode 13 (see FIG. b)).

Then, a 4000N SiN film is deposited on the entire surface of the substrate by plasma CVD, and the gate electrode and the SiO ₂ side wall surface are exposed by the planarization method and etching back method using a known resist (FIG. 2 (c)). Here, 21 is the remaining SiN film.

The SiO ₂ side wall 20 is removed by selective wet etching using ammonium fluoride in water, and Zn ions, for example, as p-type impurities are ion-implanted at 500 KeV 5 × 10 ¹² / cm ² from this opening (FIG. 2 (d)). ). Source / drain regions 14,15
Zn ions are also implanted in a part of the region, but because the amount of implantation is smaller than that of Si, and because of the high-energy implantation, the surface side becomes particularly low concentration, the race / drain regions 14, 15 There is almost no increase in parasitic resistance due to the decrease in concentration. Also, a p-layer is formed at a part of the junction between the operating layer and the substrate due to the lateral scattering of the ion implantation, but there is no problem for the same reason.

After that, the SiN film 21 is peeled off, and the activation of the implanted impurities is annealed at 800 to 850 ° C. by a capless method in an As atmosphere to form the source / drain electrodes 18 and 19 of AuGe alloy, and the self-aligned type is formed. The GaAs-MESFET is completed (Fig. 2 (e)).

A MESFET according to this example and a conventional MESFET not having a p-type barrier layer formed under the same conditions were compared and the performances were compared. As a result, the threshold voltage shift amount when the gate length was reduced from 4 μm to 1 μm was Whereas the mold is 400 mV,
In this example, it was improved to 100 mV. This value is slightly inferior in performance in this respect as compared with the value of 60 mV obtained in the embodiment shown in FIG. 5 in which most of the n ⁺ periphery is surrounded by the p-type layer. However, the delay time per gate stage of the circuit composed of MESFETs according to this embodiment is 35 ps, and as shown in FIG.
It is about 20% faster than the structure that encloses most of n ⁺ . This is because the capacitance to the substrate has decreased.
Further, the improvement of the delay time is 40% as compared with the conventional structure without the p-type barrier layer. Also, in the structure (FIG. 6) in which p is formed shallowly on the contact surface with a part of the substrate like n ⁺ surroundings, the threshold voltage shift amount is 200 mV and the delay time is 40 ps. High performance was obtained.

The present invention can reverse the ion implantation step of forming the source / drain regions 14 and 15 described with reference to FIGS. 2A and 2B and the step of forming the gate electrode sidewall. In that case, the p-type region expands as shown in FIG. 3, and the potency as a potential barrier is strengthened. According to this method, the acceleration voltage for ion implantation, the dose amount, and the ion species for forming the p-type layer are set so that the p-type layer 16 is formed at the boundary between the n-type layer 12 and the substrate 11 in the channel region. By carrying it, it becomes possible to realize a high-performance FET.

[Brief description of drawings]

FIG. 1 is a diagram showing a GaAs-MESFET of one embodiment of the present invention, FIGS. 2 (a) to 2 (e) are diagrams for explaining the manufacturing process thereof, and FIG. 3 is a GaAs-MESFET of another embodiment. Figure showing MESFET, No. 4
FIG. 5, FIG. 5 and FIG. 6 are views showing a conventional GaAs-MESFET. 11 ... Semi-insulating GaAs substrate, 12 ... N-type operating layer, 13 ... Schottky gate electrode, 14 ... N ⁺ type source region, 15 ...
… N ⁺ type drain region, 16, 17 …… p type barrier layer, 18 ……
Source electrode, 19 ... Drain electrode, 20 ... SiO ₂ film, 21 ...
… SiN film, 22 …… N-type layer.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Masao Mochizuki 1 Komukai Toshiba-cho, Sachi-ku, Kawasaki-shi, Kanagawa Stock Research Institute, Toshiba Research Institute (72) Inventor Tomori Inoue Komukai-shi, Kawasaki-shi, Kanagawa 1 Toshiba Corp. Research Institute (56) References JP-A-53-76676 (JP, A) JP-A-47-23179 (JP, A) JP-A-61-101080 (JP, A) JP-A-61 -222177 (JP, A)

Claims (4)

[Claims] 1. A semi-insulating compound semiconductor substrate, a first conductivity type operation layer formed on the surface of the substrate, a gate electrode formed on the operation layer, and the substrate sandwiching the gate electrode. A source / drain region having a first conductivity type and a high impurity concentration formed deeper than the operation layer on a surface portion, and the source / drain region only under the both ends of the gate electrode in a boundary portion between the source / drain region and the substrate. A field-effect semiconductor device comprising a pair of second conductivity type barrier layers formed deeper than a drain region. 2. The semi-insulating compound semiconductor substrate is semi-insulating
2. The field effect semiconductor device according to claim 1, wherein the field effect semiconductor device is a GaAs substrate, and the gate electrode forms a Schottky barrier with the operating layer. 3. A semi-insulating compound semiconductor substrate is provided with a first surface portion.
Forming a conductive type operating layer; forming a gate electrode on the operating layer; forming a first conductive type source and drain region of high impurity concentration using the gate electrode as a mask; Forming a side wall film on the electrode, forming a film different from the side wall film, further exposing the gate electrode and the upper portion of the side wall film, and then removing the side wall film to form this portion as an opening; Another impurity is ion-implanted into the junction between the first conductivity type below the side of the gate electrode and the substrate to deeper than the source and drain regions.
A method of manufacturing a field effect semiconductor device, comprising the step of forming a conductive barrier layer. 4. The field effect semiconductor device according to claim 3, wherein the step of forming the side wall film is performed before forming the source / drain regions, and the source / drain regions are formed using the side wall film as a mask. Production method.