JPH0714036B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device including a programmable read-only memory element.

[Conventional technology]

Programmable read-only memory elements (hereinafter referred to as PROMs) are required to have a particularly high memory capacity and reliable programming in view of their applications.

FIG. 3 is a sectional view of an example of a conventional junction breakdown type PROM cell.

An N type buried layer 2 is formed on a P type silicon substrate 1, an N type epitaxial layer 3 is deposited, and a P type base region 4 and an N type emitter region 5 are sequentially provided on the epitaxial layer 3. During this time, two PN junctions 8 and 9 are formed. When writing, the PN junction 9 biased in the reverse direction is destroyed by applying an overcurrent to the PN junctions 8 and 9 connected back to back,
Information is written by leaving only the PN junction 8 in the forward direction.

[Problems to be solved by the invention]

However, in the conventional structure, since the emitter region 5 has to be formed inside the base region 4, the occupied area per unit memory element becomes large, and it is difficult to increase the storage capacity. .

In addition, the distance (base width) between the two PN junctions 8 and 9 is relatively narrow, which results in a relatively large current amplification factor (h _FE ) and the parasitic thyristor effect (parasitic PNPN effect) between the memory elements.
Occurs, and a write current leaks, which causes a problem that the write yield and reliability are reduced.

FIG. 4 is an equivalent circuit diagram of a conventional junction breakdown type PROM.

As shown in FIG. 4, when the effect of the parasitic thyristor 50 occurs, the write current is generated in the current path 51 shown by the dotted line, that is, the path interposing the storage element Q ₀₀ , the parasitic thyristor 50, and the storage elements Q ₀₁ and Q _11. Leaks out, and the current path 52 originally shown by the solid line
The write current leaks to the memory element Q ₁₀ which should not be written, or a defect due to insufficient writing occurs,
It causes a problem that the writing step and the reliability are deteriorated.

[Means for solving problems]

A feature of the present invention is that a semiconductor substrate of one conductivity type, a buried layer of a reverse conductivity type selectively provided on the semiconductor substrate, a semiconductor layer of a reverse conductivity type provided on the buried layer, An insulating separation film that insulates and separates the opposite conductivity type semiconductor layer, a one conductivity type semiconductor layer provided on at least one of the opposite conductivity type semiconductor layers that are separated by insulation, and a surface of the one conductivity type semiconductor layer. A depression formed on the surface of the one conductivity type semiconductor layer, an insulating film provided in the depression on the surface of the one-conductivity-type semiconductor layer, and a metal electrode provided on the insulating film. A semiconductor memory device having a memory element that stores information by destroying or non-destructing an insulating film.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of an embodiment of the present invention.

The N ⁺ type buried layer 2 is provided on the P type silicon substrate 1, and the N ⁻ type epitaxial layer 3 is deposited on the surface of the silicon substrate. This epitaxial layer 3 is isolated by a silicon dioxide layer 6 into a plurality of island regions. One island region includes one buried layer 2. The silicon dioxide layer 6 is also provided in one island region to separate the epitaxial layer 3. A P-type base region 4 is provided in an island region of the separated epitaxial layer 3 which forms a memory element. Recesses are provided in these base regions 4, and a thin insulating film 11 is provided so as to cover the recesses. The metal electrode 7 is formed thereon. At the same time, providing a metal electrode 7 ₃ also on the island of epitaxial layer was not provided the base region 4 and the insulating film 11.

Information is stored by short-circuiting the electrode 7 and the base region 4 by applying a write voltage to the thin insulating film 11 to cause dielectric breakdown.

2A to 2E are cross-sectional views of the semiconductor chip in the order of steps for explaining the method for manufacturing the semiconductor memory device of the present invention.

First, as shown in FIG. 2A, a P-type silicon substrate 1
Then, the N-type buried layer 2 is selectively formed, and then the N-type epitaxial layer 3 is formed on the surface of the silicon substrate 1, and the surface is oxidized to form the silicon dioxide layer 6.

Next, as shown in FIG. 2B, P type impurities are selectively ion-implanted through the silicon dioxide layer 6 and then annealed to form a P type base region 4.

Next, as shown in FIG. 2C, the silicon dioxide layer 6
Then, the silicon layer on the main surface of the base region 4 is selectively etched to form the opening 12.

Next, as shown in FIG. 2D, a thinly controlled insulating film 11 is formed on the surface thereof. The insulating film 11 oxidizes the opening 12 into silicon dioxide, further deposits polycrystalline silicon on the opening 12, or another insulating film (such as a silicon nitride film or a polycrystalline film) on the opening 12. It can also be realized by depositing a silicon layer or the like).

Next, as shown in FIG. 2E, a metal is deposited on the surface and the metal is selectively removed to form the metal electrode 7.

In this embodiment, a write voltage is applied to the thinly controlled insulating film 11 having a recess in the base region 4 to form a corner portion 13 of the recess.
By performing dielectric breakdown, the metal of the metal electrode 7 is short-circuited with the base region 4 to store information. For example, when the insulating film 11 is silicon dioxide formed by thermal oxidation, the breakdown voltage is about 7V when the film thickness is 300Å.

The semiconductor memory device of the present invention has a simple structure, and the occupied area per unit memory device is the opening 12 of the silicon dioxide layer 6.
Area (Fig. 2 (c)), and according to the recent microfabrication technology, the area of this opening 12 is 1.5 × 1.5 μm ² , and the size of the base region 4 is about 6 × 6 μm ^2. Become.
On the other hand, in the conventional memory element, as shown in FIG. 3, the emitter must be formed inside the base region 4, and the aperture 12 of the emitter must be formed inside the base region 4. The size of 4 is about 10 × 10 μm ² . Therefore, according to the present invention, the occupied area per unit storage element can be significantly reduced as compared with the conventional one, and the storage capacity can be increased.

Further, since the storage element of the conventional junction breakdown type PROM has a bipolar transistor structure with an open base, interference between storage elements, that is, a parasitic thyristor effect occurs,
This is a cause of lowering the writing yield and reliability.

However, according to the present invention, since the emitter region does not exist in the memory element and the insulating film 11 exists on the P-type base region 4 instead, interference does not occur between the memory elements and the write yield is improved. A storage element with good reliability can be obtained.

〔The invention's effect〕

As described above, the present invention has a simple structure in which the thinly controlled insulating film is sandwiched between the base region and the electrode, and therefore, the occupied area per unit memory element can be reduced. There is an effect that the storage capacity can be increased, and by eliminating the parasitic thyristor effect that acts between the memory elements, a reliable program can be performed and a semiconductor memory device with improved write yield and reliability can be obtained. Further, since the depression is formed on the surface of the base region and the insulating film is provided there, a predetermined dielectric breakdown of the insulating film can be easily performed by the electric field concentration at the corner portion of the depression.

[Brief description of drawings]

FIG. 1 is a sectional view of an embodiment of the present invention, and FIG.
(E) is a sectional view of a semiconductor chip shown in the order of steps for explaining the manufacturing method of the embodiment shown in FIG. 1, and FIG. 3 is a sectional view showing an example of a memory element of a conventional junction breakdown type PROM, Four
The figure is an equivalent circuit diagram of a conventional junction breakdown type PROM. 1 ... P-type silicon substrate, 2 ... N-type buried layer, 3 ... N-type epitaxial layer, 4 ... P-type base region, 5 ... N-type emitter region, 6 ... Silicon dioxide layer, 7, 7 ₃ ... Metal electrode, 8,9 ... P
N junction, 10 ... N type collector region, 11 ... Insulating film, 12 ... Opening portion, 13 ... Corner portion of recess, 50 ... Parasitic thyristor, 51, 5
2 ... Current path, Q ₀₀ , Q ₀₁ , Q ₁₀ , Q ₁₁ ... Unit memory element,
X ₀ , X ₁ ... Word line, Y ₀ , Y ₁ ... Digit line.

Claims (2)

[Claims] 1. A semiconductor substrate of one conductivity type, a buried layer of a reverse conductivity type selectively provided on the semiconductor substrate, a semiconductor layer of a reverse conductivity type provided on the buried layer, and the reverse layer. An insulating separation film for insulating and separating the conductive type semiconductor layer, a one conductive type semiconductor layer provided on at least one of the reverse conductive type semiconductor layers which are insulatingly separated, and a surface of the one conductive type semiconductor layer. The formed insulation, the insulating film provided in the depression on the surface of the one-conductivity-type semiconductor layer, and the metal electrode provided on the insulation film, and the insulation at the corner of the depression. A semiconductor memory device having a memory element for storing information by breaking or non-breaking a film. 2. The semiconductor memory device according to claim 1, wherein said insulating film is at least one selected from the group consisting of silicon oxide, silicon nitride and polycrystalline silicon.