JPH0718759B2 - Gate coupled input type signal input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A gate-coupled input signal input of an infrared detection element in which a photovoltaic infrared detection element and a signal processing circuit are AC-coupled to perform signal multiplexing inside the element. Regarding the circuit, a photovoltaic type infrared detection element biased via a load is connected to the gate of the field-effect transistor with an alternating current in order to improve the S / N ratio (signal to noise ratio) with a simple circuit configuration. In the signal input circuit of the gate input coupling system, which is connected to the
The output voltage of the photovoltaic infrared detection element is configured to be positively fed back to the substrate potential of the photovoltaic infrared detection element via an impedance conversion circuit having a gain of 1 or less.

[Industrial application field]

The present invention relates to a gate-coupled input type signal input circuit, and in particular, an infrared detecting element for AC multiplexing a photovoltaic type infrared detecting element (PV element) and a signal processing circuit to multiplex signals inside the element. The present invention relates to a gate coupled input type signal input circuit.

PV device and Charge Coupled Device (CCD)
Infrared detectors that combine signal processing circuits such as the above to perform signal multiplexing inside the device have been attracting attention as next-generation infrared sensors and are being researched and developed.

In this infrared detection element, the output voltage obtained by photoelectric conversion by the PV element is input to the signal processing circuit,
Its S / N ratio is important.

[Conventional technology]

4 (A) and 4 (B) are a circuit diagram of an example of a conventional gate-coupled input type signal input circuit and an equivalent circuit diagram of its main part. In the figure (A), 1 is a PV element, 2 is a MOS type field effect transistor (FET), _RL is a load resistance, C is a connection point between the cathode of the PV element 1 and the load resistance _RL to the gate of FET2. It is a capacitor that is AC-coupled. This conventional circuit inputs the AC component of the output voltage of the PV element 1 to the gate of the FET 2, and is therefore called a "gate coupled input method". FE
The source of T2 is grounded, and the drain is connected to a MOS type signal processing circuit such as CCD to which electric charges should be input.

FIG. 4 (B) is the PV element 1 and load resistance R _{L of} FIG. 4 (A).
The equivalent circuit of the circuit part which consists of is shown. 4 in the same figure (B)
Is a current source of the photocurrent I _P extracted from the PV element 1 according to the incident light amount of infrared light, R ₀ is an internal resistance (reverse resistance) of the PV element 1, and these are connected in parallel with each other, and It is connected in series with the load resistance R _L. Vdd is the power supply voltage, V
_OUT indicates the output voltage to the gate of the MOS type FET2.

In FIG. 4 (B), no current flows from the connection point of the load resistance R _L to the current source 4 and the internal resistance R ₀ to the gate of the FET 2. Therefore, if the current flowing through the internal resistance R ₀ is I _1. The formula is obtained.

Vdd = R _L · (I ₁ + I _P ) + R ₀ · I ₁ (1) When rearranging equation (1) for I ₁ , _Therefore , the output voltage V _OUT is Becomes

In this conventional circuit, a photocurrent is generated in the PV element 1 by the infrared light incident on the PV element 1, and the voltage determined by the equation (3) is determined by the internal resistance R ₀ of the PV element 1 and the photocurrent I _P. V _OUT is PV
Although taken out from the cathode of the device 1, only the AC component is applied to the gate of the FET 2 by the capacitor C. As a result, the drain current flowing through the FET2 is injected into the MOS type signal processing circuit.

In this gate-coupled input type signal input circuit, the current (or charge) injected into the MOS type signal processing circuit corresponds to the AC component of the output voltage V _OUT of the PV element 1, that is, the variation of the target sample temperature to be detected. Signal, and is not affected by the DC component corresponding to the temperature level of the target sample or the ambient temperature, which is the background light. Therefore, it is applied to an infrared detector for long-wavelength infrared light that detects a temperature change of only a few degrees at normal temperature of the sample to be detected, and the sample temperature is changed to a large level DC component corresponding to background light. Even if a weak AC signal component corresponding to a change is taken out in a superposed manner, the problem that the detection sensitivity is lowered does not occur in the gate coupling input method.

[Problems to be solved by the invention]

In the above-mentioned conventional circuit, the load resistance R _L must be set to a large resistance value in order to increase the voltage change range of the output voltage V _OUT of the PV element 1.

However, in such a case, the internal resistance R ₀ of the PV element operating especially for long wavelengths or at high temperature is extremely small, so that R _L / R ₀ > 1 and the output is as shown in equation (3). Voltage
There is a problem that a sufficient value of voltage cannot be obtained as V _{OUT, and} as a result, the S / N ratio of the output signal of FET2 becomes poor.

The present invention was created in view of the above points, and an object of the present invention is to provide a gate-coupled input type signal input circuit capable of improving the S / N ratio with a simple circuit configuration.

[Means for solving problems]

FIG. 1 shows a principle configuration diagram of the present invention and an equivalent circuit diagram of essential parts. The same components as those in FIGS. 4A and 4B are designated by the same reference numerals, and the description thereof will be omitted.

As shown in FIG. 1 (A), according to the present invention, the output voltage V _OUT of the PV element 1 biased via the load resistance R _L is transferred to the PV element 1 via the impedance conversion circuit 3 having a gain of 1 or less. It is configured so as to perform positive feedback to the substrate potential.

[Action]

The FET 2a of the gate coupled input type signal input circuit according to the present invention
The equivalent circuit of the circuit section on the input side is as shown in FIG. 1 (B). In FIG. 1 (B), 5 is obtained by inputting the output voltage V _OUT of the PV element 1 to the substrate potential of the PV element 1 by positive feedback via the impedance conversion circuit 3 having a gain A (where A ≦ 1). The voltage source of the voltage A · V _OUT is shown.

The voltage source 5 is connected to the input terminal of the power supply voltage Vdd via the internal resistance R ₀ and the load resistance R _L of the PV element 1 in series. A series circuit of the voltage source 5 and the internal resistance R ₀ is connected in parallel with the current source 4.

In the equivalent circuit shown in FIG. 1 (B), the following equation is obtained when the current flowing through the internal resistance R ₀ is I ₁ .

Vdd = _RL (I _I + I _P ) + I ₁ · R ₀ + A · V _OUT (4) V _OUT = I ₁ · R ₀ + A · V _OUT (5) From formula (4) and formula (5), select I ₁ Eliminating and rearranging about V _OUT gives:

Comparing equation (6) with equation (3), the internal resistance R ₀ is effectively 1 / (1-A) times in the present invention.

Since the gain A of the impedance conversion circuit 3 is 1 or less, the value of the internal resistance R ₀ is effectively increased to 1 / (1-A) times, and even if the value of the load resistance R _L is large, the FET 2a The voltage to the gate can be increased.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 1A are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 2, 6 is a MOS type FET, the gate of which is connected to the connection point of the PV element 1 load resistor R _L and the capacitor C, and the source of which is the anode (substrate) of the PV element 1.
, And the drains of the MOS type FET 7 respectively, and constitute a source follower corresponding to the impedance conversion circuit 3.

Reference numeral 7 is a load MOS type FET whose gate and source are connected. Vdd and Vss are the drain of FET6 and FET, respectively.
Supply voltage to 7 sources.

A structural sectional view of the embodiment circuit shown in FIG. 2 is shown in FIG.
In the figure, a p-type substrate 10 made of InSb (indium antimony), HgCdTe (mercury cadmium telluride), an n ⁺ diffusion layer 11 and a silicon oxide film (Si
The thin film 12 made of O ₂ ), zinc sulfide (ZnS), etc. constitutes the PV element 1.

On the other hand, two P wells 14 and 15 are formed on the n-type silicon (Si) substrate 13, and n ⁺ diffusion layers 16, 17 and 18 are further formed in the P well 14. Also another P
An n ⁺ diffusion layer 19 is formed in the well 15, and this n ⁺ diffusion layer 19 constitutes the source region of the MOS type FET 2 and P
The well 15 also constitutes an input diode.

On the n-type Si substrate 13 in which the above respective regions are formed, an oxide film 20 made of SiO ₂ is formed by a known means, and gate electrodes 21 and 22 made of polycrystalline silicon and an input gate are further formed thereon. An electrode 23, a storage gate 24, an electrode 25 forming a part of the CCD, and the like are formed.

The drain of the MOS type FET 2 described above corresponds to the region of the P well 15 directly below the accumulation gate 24, and the gate is the input gate electrode 23.
Equivalent to. The n ⁺ diffusion layer 16 corresponds to the drain of the MOS type FET 6, and the source and the MOS type of the MOS type FET 6
Since the drains of the FETs 7 are always at the same potential, they are both shared by the n ⁺ diffusion layers 17. Furthermore, MOS type FET
The n ⁺ diffusion layer 18 corresponds to the source of 7.

Further, the non-doped polycrystalline silicon film 26 is formed on the oxide film 20, and the polycrystalline silicon film 27 and the SiO ₂ film are formed at different positions.
A capacitor C in which an oxide film 28 and the like and a polycrystalline silicon film 29 are sequentially laminated is formed. The above-mentioned non-doped polycrystalline silicon film 26 constitutes the load resistance R _L.

In such a configuration, the photocurrent generated by the infrared light received by the PV element 1 and the output voltage determined by the internal resistance of the PV element 1 are applied from the n ⁺ diffusion layer 11 to the gate electrode 21 corresponding to the gate of the FET 6. The gate electrode 21, the oxide film 20,
Impedance conversion is performed by the FET 6 composed of the n ⁺ diffusion layers 16 and 17, the P well 14 and the silicon substrate 13, and the positive feedback input is made from the n ⁺ diffusion layer 17 to the substrate 10.

PV element 1 represented by formula (6) amplified in this way
Of the output voltage of the n ⁺ diffusion layer 11 and thereafter, only the AC component is taken out by the capacitor C and applied to the gate electrode 23, and passes through the region of the P well 15 immediately below the input gate electrode 23, and the P well 15 immediately below the accumulation gate 24. The signal charge is accumulated in the potential well of the region.

According to this embodiment, the gain A of the source follower by FET6 is
Since 0.9 can be easily realized, the output voltage V _OUT can be improved by about 10 times, as can be seen from the equation (6). Therefore, the drain current of the FET 2 becomes large and the signal amount becomes large, while the noise is substantially constant, so that the S / N ratio can be improved.

When the gain A is set to 1, the output voltage V _OUT becomes Vdd−R _L · I _{P as} can be seen from the equation (6), so the load resistance R _L
By increasing the value of, the output voltage in a large change range can be obtained.

The present invention is not limited to the above embodiment, and as the impedance change circuit 3, an emitter follower having a higher current drive capability than a source follower and an operational amplifier capable of obtaining a gain close to 1 may be used. . Further, it goes without saying that the load resistance R _L can be replaced with the polycrystalline silicon film 26 by using other means such as changing the shape ratio of the MOS type FET.

Further, the FET 2a may be a junction type FET.

〔The invention's effect〕

As described above, according to the present invention, the internal resistance of the PV element can be effectively improved by a factor of 1 / (1-A). It has the features that the voltage can be increased and thus the S / N ratio of the signal injected into the signal processing circuit can be improved, and that it can be configured with a simple circuit.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram and an equivalent circuit diagram of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a structural sectional view of an embodiment of the present invention, and FIG. An example circuit diagram and an equivalent circuit diagram are shown. In the figure, 1 is a photovoltaic detection element (PV element), 2 is a MOS field effect transistor (FET), 2a is a field effect transistor (FET), 3 is an impedance conversion circuit, 4 is a current source, and 5 is a voltage. Source, R ₀ is the internal resistance of the PV element, _RL is the load resistance, and C is the capacitor.

Claims (1)

[Claims] 1. A photovoltaic sensing element (1) biased through a load ( _RL ) is AC-connected to the gate of a field effect transistor (2a), the drain of the field effect transistor (2a). In a signal input circuit of a gate input coupling system for inputting a signal to a signal processing circuit, the output voltage of the photovoltaic detection element (1) is transferred to the photovoltaic power source via an impedance conversion circuit (3) having a gain of 1 or less. A gate-coupled input type signal input circuit which is positively fed back to the substrate potential of the mold detection element (1).