JPH0718760B2 - Gate input type signal input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A gate input type signal input circuit of an infrared detection element for coupling a photovoltaic detection element and a signal processing circuit to perform signal multiplexing inside the element, and a simple circuit configuration. The purpose is to improve the S / N ratio (signal-to-noise ratio) by connecting the photovoltaic detector element and the gate of the field effect transistor, and input the signal to the signal processing circuit from the drain of the field effect transistor. In the signal input circuit, the potential at the connection point between the photovoltaic sensing element and the gate of the field effect transistor is positively fed back to the substrate potential of the photovoltaic sensing element via an impedance conversion circuit having a gain of 1 or less. To configure.

[Industrial applications]

The present invention relates to a gate input system signal input circuit, and more particularly to an infrared detection device gate input system in which a photovoltaic type infrared detection element (PV element) and a signal processing circuit are combined to perform signal multiplexing inside the element. The present invention relates to a signal input circuit.

PV device and Charge Coupled Device (CCD)
Infrared detectors that combine signal processing circuits such as the above to perform signal multiplexing inside the device have been attracting attention as next-generation infrared sensors and are being researched and developed.

In this infrared detection element, the electric charge (photocurrent) obtained by photoelectric conversion by the PV element is input to the signal processing circuit, so its S / N ratio is important.

[Conventional technology]

FIG. 4 shows a circuit diagram of an example of a conventional gate input type signal input circuit. In the figure, 1 is a PV element, 2 is a MOS type field effect transistor (FET), and since the cathode of the PV element 1 is directly connected to the gate of the FET 2, it is called a "gate input method". FET2 source is grounded and drain is CC
It is connected to a signal processing circuit to which electric charges such as D should be input.

In this conventional circuit, a photocurrent is generated in the PV element 1 by the infrared light incident on the PV element 1, and a voltage determined by the product of the internal resistance of the PV element 1 and the photocurrent is applied to the gate of the FET 2. It As a result, the drain current flowing through the FET2 is injected into the signal processing circuit.

In this gate input type signal input circuit, the current (or charge) injected into the signal processing circuit is not directly related to the incident infrared light amount of the PV element 1 but has an exponential relationship, so that the PV element 1 is long. It is for detecting infrared light of wavelength, and has the feature that electric charge does not overflow even if its internal resistance is extremely small.

[Problems to be solved by the invention]

However, although the above-mentioned conventional circuit uses the photovoltaic power (open voltage) of the PV element 1, since the open voltage is extremely small on the order of mV, signal conversion is extremely weak,
There was a problem that the S / N ratio was bad.

Further, in order to amplify the open voltage, it is possible to install an amplifier between the cathode of the PV element 1 and the gate of the FET2, but in this case, the power consumption becomes large and it is necessary to match the operating points. There was a problem.

The present invention was created in view of the above points, and an object thereof is to provide a gate input type signal input circuit capable of improving the S / N ratio with a simple circuit configuration.

[Means for solving problems]

FIG. 1 shows a principle configuration diagram and an equivalent circuit diagram of the present invention. In the figure (A), the same components as those in FIG.
The description is omitted. In the circuit of the present invention shown in FIG. 1 (A), the potential at the connection point between the PV element 1 and the gate of the FET 2a is passed through the impedance conversion circuit 3 having a gain of 1 or less to the PV element 1
It is configured to positively feed back to the substrate potential of.

[Action]

FET 2a of the signal input circuit according to the present invention shown in FIG.
The AC equivalent circuit of the other circuit parts is as shown in FIG. In FIG. 2B, 4 is a current source of the photocurrent I _P taken out from the PV element 1 according to the incident light amount of infrared light, and 5 is
Gain A for the potential V _G at the connection point between the PV element 1 and the gate of FET2a
(However, A ≦ 1) is a voltage source of a voltage A · V _G obtained by the positive feedback input to the substrate potential of the PV device 1 via the impedance conversion circuit 3.

R _O is the internal resistance of the PV element 1 and is connected in series with the voltage source 5. The connection point between the resistor R _O and the current source 4 is connected to the gate of the FET 2a.

In FIG. 1B, since no current flows through the gate of the FET 2a, the photocurrent I _P flows through the series circuit of the resistor R _O and the voltage source 5 without being shunted. Therefore, the gate voltage (open voltage) V _S is expressed by the following equation.

This open voltage V _S is 1 / (1-A) times the open voltage I _P · R _O of the conventional signal input circuit shown in FIG. 4, and the gain A is 1 or less. Voltage V _S is 1 /
It will be amplified by (1-A) times.

〔Example〕

FIG. 2 shows a circuit diagram of an embodiment of the present invention. In the figure, the same components as those in FIG. 1A are designated by the same reference numerals, and the description thereof will be omitted. In FIG. 2, 6 is a MOS type FET, the gate of which is connected to the gate connection point of the PV element 1 and the MOS type FET 2, and the source of which is the anode (substrate) of the PV element 1 and the MO.
The source followers are connected to the drains of the S-type FETs 7 and correspond to the impedance conversion circuit 3.

Reference numeral 7 is a load MOS type FET whose gate and source are connected. Vdd and Vss are the drain of FET6 and FET, respectively.
Supply voltage to 7 sources.

A structural sectional view of the embodiment circuit shown in FIG. 2 is shown in FIG.
In the figure, 1 is a PV element, which is an n ⁺ diffusion layer 11 formed on a P-type substrate 10 such as InSb (indium antimony), PbSnTe (lead tin telluride), HgCdTe (mercury cadmium telluride), and the like. It is composed of an insulating thin film 12 such as SiO ₂ (silicon oxide film) or ZnS (zinc sulfide film) formed on.

On the other hand, two P wells 14 and 15 are formed on the n-type silicon (Si) substrate 13, and an n ⁺ diffusion layer is formed in the P well 14.
16, 17 and 18 are formed. Further, an n ⁺ diffusion layer 19 is formed in the other P well 15, and this n ⁺ diffusion layer 19 constitutes the source region of the MOS type FET 2 and also constitutes an input diode together with the P well 15. ing.

An oxide film 20 made of SiO ₂ is formed on the n-type Si substrate 13 in which the above regions are formed by a known method, and gate electrodes 21 and 22 made of polycrystalline silicon and an input gate are further formed thereon. Electrode 23, storage gate 24, electrode 2 forming a part of CCD
Five and so on are formed.

The drain of the MOS type FET 2 described above corresponds to the region of the P well 15 directly below the accumulation gate 24, and the gate is the input gate electrode 23.
Equivalent to. The n ⁺ diffusion layer 16 corresponds to the drain of the MOS type FET 6, and the source and the MOS type of the MOS type FET 6
Since the drains of the FETs 7 are always at the same potential, they are both shared by the n ⁺ diffusion layers 17. Further, the n ⁺ diffusion layer 18 corresponds to the source of the MOS type FET 7.

In such a configuration, the open voltage determined by the product of the photocurrent generated by the infrared light received by the PV element 1 and the internal resistance of the PV element 1 is from the n ⁺ diffusion layer 11 to the gate electrode 21 corresponding to the gate of the FET 6. Applied to the gate electrode 21, the oxide film 20, the n ⁺ diffusion layers 16 and 17, the P well 14, and the silicon substrate 13.
Impedance conversion is performed by FET6 consisting of n ⁺ diffusion layer
Positive feedback is input to the substrate 10 from 17.

The open voltage thus amplified is applied to the gate electrode 23 from the n ⁺ diffusion layer 11 and passes through the region of the P well 15 directly below the input gate electrode 23, so that the potential of the region of the P well 15 immediately below the storage gate 24 is increased. The signal charge is accumulated in the well.

According to this embodiment, the gain A of the source follower by FET6 is
Since about 0.9 can be easily realized, the open voltage V _S can be improved by about 10 times from the above formula. Therefore, the drain current of the FET 2 becomes large and the signal amount becomes large, while the noise is substantially constant, so that the S / N ratio can be improved.

Also, by making the current flowing through the load FET 7 one digit larger than the photocurrent I _P , the operating point is the same as that of the conventional circuit without the FET 6, so that it is possible to use an amplifier on the gate side of the FET 2. There is no problem of power consumption, and since the power consumption by the FETs 6 and 7 is small, there is no problem of power consumption.

The present invention is not limited to the above-described embodiment, and as the impedance conversion circuit 3, an emitter follower having a higher current drive capability than a source follower and an operational amplifier capable of obtaining a gain close to 1 may be used. .

Further, the MOS type FET 2, the impedance conversion circuit 3, and the signal processing circuit can be formed on the same substrate.

Further, although the MOS type FET 2 is used as the FET 2a in the present embodiment, the same effect can be obtained with a junction type FET or the like.

〔The invention's effect〕

As described above, according to the present invention, the open voltage is 1 / (1-
A) because it can be improved, the S / N ratio of the signal injected into the signal processing circuit can be improved, and a simple circuit can be constructed without problems of power consumption and operating point. It has features.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram and an equivalent circuit diagram of the present invention, FIG. 2 is a circuit diagram of an embodiment of the present invention, FIG. 3 is a structural sectional view of an embodiment of the present invention, and FIG. It is an example circuit diagram. In the figure, 1 is a photovoltaic infrared detection element (PV element), 2 is a MOS field effect transistor (FET), 2a is a field effect transistor (FET), 3 is an impedance conversion circuit, 4 is a current source, 5 Is the voltage source and R _O is the internal resistance of the PV element.

Claims (1)

[Claims] 1. A gate input type signal input in which a photovoltaic detection element (1) is connected to a gate of a field effect transistor (2a) and a signal is input from a drain of the field effect transistor (2a) to a signal processing circuit. In the circuit, the potential at the connection point between the photovoltaic sensing element (1) and the gate of the field effect transistor (2a) is detected by the photovoltaic sensing through an impedance conversion circuit (3) having a gain of 1 or less. A gate input type signal input circuit which is positively fed back to the substrate potential of the element (1).