JPH0718894B2 - Data comparison device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention compares data to be measured with preset upper and lower limit values and, for example, data for providing a trigger signal to a storage means of a memory recorder or the like. The present invention relates to a comparison device.

[Conventional technology]

When comparing the measured data with the reference value, one comparator may be used as long as the reference value is one, but when comparing two reference values, for example, the upper limit value and the lower limit value, the second value is conventionally used.
As shown in the figure, two comparators 1 and 2 are used. That is, the upper limit value setter 3 sets the upper limit value (MAX) in one comparator 1, and the lower limit value setter 4 sets the lower limit value (MIN) in the other comparator 2. The signal under measurement is converted into digital data by the A / D converter 5, and the data D is input to both the comparators 1 and 2. When D> MAX in the comparator 1 and D> MIN in the comparator 2, on the other hand, a trigger signal is output, and the trigger signal is given to a memory recorder (not shown) via the OR circuit 6.

[Problems to be Solved by the Invention]

According to the above-mentioned conventional example, it is convenient in that the upper limit value and the lower limit value can be freely set separately, but there is a cost difficulty in using two comparators.

Therefore, an object of the present invention is to provide a data comparison device capable of determining whether the measured data is inside or outside two reference values with one comparator.

[Means for Solving the Problems]

In order to achieve the above-mentioned object, in the present invention, as shown in FIG. 1, an n-bit digital comparator is provided.
10, a data input A / D converter 11 connected to one input terminal A1 to An side of the comparator 10, and a comparison reference connected to the other input terminal B1 to Bn side of the comparator 10. Including the value setter 12, one of the input terminals A1 to An of the comparator 10 and the A / D
AND circuit C1 to each output terminal of converter 11
Cn is connected, and AND circuits D1 to Dn are connected between the other input terminals B1 to Bn of the comparator 10 and the output terminals of the comparison reference value setting device 12, respectively, and the same. The comparison range setting device 13 for applying the same control logic signal is provided to both the AND circuits on the A / D converter 11 side and the comparison reference value setting device 12 side in the bit order.

[Action]

According to the above configuration, the comparison reference value setting unit 12 sets the lower limit value of the comparison range, and the comparison range setting unit 13 sets the width of the comparison range. For example, assuming that the comparator 10 to be used has 8 bits, the upper 2 bits from the comparison reference setting unit 12 are 1,
0, lower bits 0 or 1 (10 ×××
XX) is given to the AND circuits D8 to D1 on the comparison reference value setting unit 12 side, and the control logic signal “2” is given to the AND circuits C8, C7, D8 and D7 of the upper 2 bits from the comparison range setting unit 13. 1 "is an AND circuit C6 to C1 and D6 to D1 which is the lower level.
When a bit signal of (11000000) is given to the control logic signal “0”, the other input terminals B8 to B1 of the comparator 10 are output.
The side is fixed at (10000000).

On the other hand, the measurement data is supplied from the A / D converter 11,
Since the control logic signal “0” is applied to one of the AND circuits C6 to C1 of the lower 6 bits by the comparison range setting unit 13, the lower 6 bits of one of the input terminals A8 to A1 of the comparator 10 are Always "0" and the upper 2 bits are (00), (01),
Can be (10) and (11).

Therefore, the comparator 10 receives both input signals (1000
0000), a coincidence signal is output, and otherwise it is disagreement. By the way, in this case, since the lower 6 bits of the measurement data are forcibly set to "0", the coincident measurement data is in the range of (10000000) to (10111111). Where 8-bit full scale is 256
Therefore, the above range is 50% to 75% of full scale.

By the way, if only the upper 2 bits are designated as (11) by the comparison range setting unit 13 and the upper 2 bits are set as (00) by the comparison reference setting unit 12, it is 0%.
~ 25%, (01) 25% ~ 50%, (11) 75% ~
It will be 100% (both to full scale). As another example, to set the comparison range to 50% to 62.5%, the control logic signal of the comparison range setter 13 (111000
00) and set the output of the comparison reference value setter 12 to (100 ××××
X).

〔Example〕

Further, an embodiment of the present invention will be described in detail with reference to FIG.

In this embodiment, an 8-bit digital comparator 10 is provided, for example. A data input A / D converter 11 is connected to one of the input terminals A1 to A8 of the comparator 10.
The comparison reference value setting device 12 is connected to the other input terminals B1 to B8 side of the above, and in this case, AND circuits C1 to C8 and D1 to D8 are interposed between them. In addition, each input terminal A, B
In, the subscript 1 is the LSB and 8 is the MSB.

The AND circuit 2 is a 2-input type, each first input terminal a of the AND circuits C1 to C8 is connected to each output terminal of the A / D converter 11, and each output terminal thereof is one input terminal A1 described above. ~ Connected to A8. Similarly, the first input terminals a of the AND circuits D1 to D8
Are connected to the respective output terminals of the comparison reference value setting device 12, and their respective output terminals are connected to the other input terminals B1 to B8. A comparison range setter 13 is connected to the second input terminals b of the AND circuits C1 to C8 and D1 to D8. The comparison range setting unit 13 outputs the same control logic signal "0" or "1" to both AND circuits having the same bit order, for example, C8, D8; C7, D7.

Here, the comparison reference value setting circuit 12 to the AND circuit D8
A bit signal of (10 ××××××) is given to each first input terminal a of D1 and the comparison range setter 13 outputs an AND circuit C8
When the control logic signal of (11000000) is applied to each second input terminal b of C1; % ~ 7
It is determined whether or not it is within the range of 5%. If it is within the range, the output 10a of the comparator 10 is set to "L", and if it is out of the range, the output 10a is set to "H", and this signal is triggered. It is added as a signal to a memory recorder or the like (not shown).

In this embodiment, each input terminal A8 to A1; B8 of the comparator 10 is
An AND circuit is provided in each of B1 to B1. However, if the comparison range is set to a constant width of 1/4 of full scale, the comparator can be a 2-bit comparator, and the circuit configuration becomes simpler. . Further, unlike the embodiment, a logic input may be used, in which case it becomes a trigger circuit by pattern setting.

〔The invention's effect〕

As described above, according to the present invention, it is possible to compare the measurement data with two reference values with one comparator.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an embodiment according to the present invention, and FIG. 2 is a block diagram of a conventional example. In the figure, 10 is a comparator, 11 is an A / D converter, 12 is a comparison reference value setting circuit, and 13 is a comparison range setting circuit.

Claims (1)

[Claims] 1. An n-bit digital comparator 10 and the comparator.
For data input connected to one of the 10 input terminals A1 to An
The A / D converter 11 and the comparison reference value setter 12 connected to the other input terminal B1 to Bn side of the comparator 10, the comparator,
AND circuits C1 to Cn are respectively connected between the input terminals A1 to An of one of the 10 and the output terminals of the A / D converter 11, and the other input terminals B1 to of the comparator 10 are connected to each other. AND circuits D1 to Dn are respectively connected between Bn and the respective output terminals of the comparison reference value setting device 12, and the A / D converter 11 side and the comparison reference value setting in the same bit order are set. Bowl 1
A data comparison device characterized in that a comparison range setting device (13) for giving the same control logic signal is provided to both AND circuits on the second side.