JPH0732342B2 - Analog delay circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an analog delay circuit that can delay an analog signal with high resolution and that can easily change the delay time.

[Prior Art] Various delay circuits for electric circuits have been considered in the past. For example, a physical delay line, a distributed constant circuit, a BBD (charge transfer device), a CCD (charge coupled device), and a digital system are used for shifting. It is widely spread to program control using registers or RAM.

By the way, in the delay circuit, there are various technical fields in which it is desired to change the delay time arbitrarily, but it is difficult for the delay line and the distributed constant circuit to use the BBD, CCD, or Generally, a shift register or the like is used to control the frequency of the clock. However, since the signal that is delayed by using BBD, CCD, shift register, etc. uses the clock pulse to transfer the signal, the signal is sampled by the clock, so the resolution on the time axis is defined by the clock cycle. However, there is a drawback that the distortion rate becomes high. To solve this, theoretically, the clock should be made extremely fast to improve the resolution, but then, in order to obtain the target delay time, the number of stages of elements such as BBD, CCD, shift register is increased. It had to be made, and there was a drawback that it became technically difficult.

Further, these devices can change the delay time depending on the clock cycle, but have a drawback that the resolution also changes accordingly.

[Problems to be Solved by the Invention]

The present invention solves the above-mentioned drawbacks of the prior art,
It is an object of the present invention to provide an analog delay circuit capable of delaying an analog signal with a high resolution and thus a low distortion, and continuously varying a delay time without changing the resolution.

[Means for solving problems]

This invention has an oscillating circuit configured by cascade-connecting CMOS gates and feeding back the output to the input side. By controlling the voltage applied to the CMOS gates according to the input analog signal, the input analog signal It has a FM modulation circuit for pulse FM modulation and a circuit in which CMOS gate circuits are connected in series.The pulse FM modulation signal output from the FM modulation circuit is input, and the CMOS is controlled by a delay time control signal input from the outside. A variable delay circuit that variably delays the pulse FM modulation signal by controlling the voltage applied to the gate, and a cascade connection circuit of CMOS gates to which the pulse FM modulation signal output from this variable delay circuit is input. Of the delay circuit, an exclusive OR circuit that receives the output signal of this delay circuit and the input signal of this delay circuit, and outputs an exclusive OR of these, and this exclusive OR circuit. A FM demodulation circuit having a low-pass filter for smoothing the output signal of the circuit, and the CMOS gates connected in series on the same substrate as the CMOS gates of the FM modulation circuit, the variable delay circuit, and the FM demodulation circuit, and the output is input. Delay time stability that controls the power supply voltage of each CMOS gate of the FM modulation circuit, the variable delay circuit, and the FM demodulation circuit according to the result of comparing the oscillation frequency of the oscillation circuit configured by feedback to the reference frequency. It is characterized by having a conversion circuit.

[Work]

According to the solving means of the present invention, since the delay by the CMOS gate does not use a clock, high resolution can be obtained, and
The delay time can be controlled continuously by the power supply voltage of the CMOS gate.

Moreover, each CM of FM modulation circuit, variable delay circuit, FM demodulation circuit
Since temperature detection is performed using the CMOS gate on the same substrate as the OS gate and the power supply voltage of the CMOS gate of each of these circuits is controlled, temperature compensation can be performed with high accuracy.

〔Example〕

First, a delay circuit using a CMOS gate will be described.

An example of the CMOS gate circuit is shown in FIG. This is because the p-channel MOS-FET 12 and the n-channel MOS-FES 14 are connected to each other with their gates and drains connected to each other, the power supply voltages V _DD and V _SS are applied to their sources, and signals are input to their gates via the input terminal 13. Then, an inverted signal of the input signal is output from the drain to the output terminal 15.

In this CMOS inverter 10, a delay time occurs between the input and the output. This delay time is, as shown in FIG.
Depending on the supply voltage V _DD -V _SS, large power supply voltage V _DD -V as _SS small delay time, greater rate of change. this is,
This is because the conductance of the element changes depending on the power supply voltage V _DD −V _SS . Therefore, by utilizing this property, the delay time can be set to an arbitrary delay time by controlling the delay time according to the magnitude of the power supply voltage V _DD −V _SS .

Further, by connecting the CMOS inverters 10 in multiple stages as shown in FIG. 4, a longer delay time can be set. For example, when the power supply voltage V _DD −V _SS is 5V,
If a delay of 3.5 ns is obtained, a delay time of 8000 × 3.5 ns 28 μs can be obtained by connecting 8000 stages in series. Further, FIG. 5 shows the power supply voltage V _DD -V _SS vs. delay time characteristic when 80 stages are connected in series.

The delay time of the CMOS inverter circuit 10 also depends on the temperature as shown in FIGS. 3 and 5, and the higher the temperature, the longer the delay time.

Sixth Example of Delay Circuit Using CMOS Inverter Circuit 10
Shown in the figure. This is a device in which a CMOS gate and an element for controlling the delay time between its power supplies are inserted.

In FIG. 6, p-channel MOS-FET 12 and n-channel MO are shown.
With S-FET14, the gates are connected to each other,
The delayed signal is input from the gate and the signal is output from the drain. Source of p-channel MOS-FET12 and power supply V _DD
Between the source of the n-channel MOS-FET 14 and the power supply V _SS as a delay time control element.
ET16 and n-channel MOS-FET 18 are respectively inserted. Control voltages Vc ₁ and Vc ₂ are input from the terminals c1 and c2 to the gates of the p-channel MOS-FFT 16 and the n-channel MOS-EFT 18, respectively. These control voltages Vc ₁ and Vc ₂ are symmetrical voltages with respect to the reference potential V _DD −V _SS (in other words, V _DD −Vc ₁ = Vc ₂ −
V _SS ). Then, by controlling the values of the control voltages Vc ₁ and Vc ₂ , the voltage applied to the p-channel MOS-FET 12 and the n-channel MOS-FET 14 forming the CMOS inverter changes, and the delay time changes accordingly.

An example of the IC pattern of the circuit is shown in FIG. 6 and shown in FIG. this
The IC pattern also facilitates multi-stage connection.

The delay circuit of FIG. 8 comprises a plurality of CMOS inverters 10 connected in cascade. Each CMOS inverter 10-1 to 10-n
In each, the drain output of the previous stage is input to the gate of the next stage. Power supply voltages V _DD and V _SS are p-channel MOS-
CMOS inverter 1 via FET16, n-channel MOS-FET18
P-channel MOS-FETs 12 which form 0-1 to 10-n,
It is supplied to the n-channel MOS-FET 14, respectively. The control MOS-FETs 16 and 18 are controlled by the control voltages Vc ₁ and Vc ₂ to commonly control the applied voltage to the CMOS inverters 10-1 to 10-n. With such a configuration, it is possible to control the delay time in a wide range by using the common delay time control MOS-FETs 16 and 18.

The delay circuit shown in FIG. 9 is provided with two delay time control elements. That is, p in the circuit of FIG.
The p-channel MOS-FET 24 and the n-channel MOS-FET 26 are connected in parallel to the channel MOS-FET 16 and the n-channel MOS-FET 18, respectively. The control voltage V is applied to the gates of the p-channel MOS-FET 24 and the n-channel MOS-FET 26 from the terminals c3 and c4.
c ₃ and Vc ₄ are input respectively. By the voltages Vc ₁ and Vc ₂ input to the terminals c1 and c2 and the voltages Vc ₃ and Vc ₄ input to the terminals c3 and c4,
The delay time can be controlled by two systems. For example, as in an embodiment (FIG. 1) of the present invention described later, one system performs control for stabilizing the delay time with respect to fluctuations in power supply voltages V _DD and V _SS and temperature changes, and the other. This system can be used to perform variable control of delay time.

The delay circuit shown in FIG. 10 has a plurality of CMOS inverters 10 connected in cascade and two control systems. That is, each CMOS inverter is composed of a p-channel MOS-FET 12 and an n-channel MOS-FET 14, and a p-channel for control is provided inside it.
The channel MOS-FET 16 and the control n-channel MOS-FET 18 are connected. Also, a p-channel MOS-F for control is provided on the outside of it.
The ET24 and n-channel MOS-FET26 are connected commonly to all stages. In this circuit, the delay time is controlled by the two systems of the voltages Vc ₁ and Vc ₂ input to the gates of the MOS-FETs 16 and 18 and the voltages Vc ₃ and Vc ₄ input to the gates of the MOS-FETs 24 and 26. .

The delay circuit using the CMOS inverter has been described above. Next, an embodiment of the present invention using this delay circuit is shown in FIG. In Figure 1, all inverters
It is composed of a CMOS inverter (hereinafter simply referred to as an inverter) and is installed under the same temperature and power supply (V _DD and V _SS conditions (on the same substrate). In addition, in FIG.
The power supplies V _DD and V _SS are not shown.

The delay time constant voltage generation circuit 30 generates control voltages Vc ₁ and Vc ₂ for each inverter in FIG. 1 to obtain a constant delay time regardless of fluctuations in power supply voltages V _DD and V _SS and temperature. Circuit. In the constant delay time voltage generation circuit 30, the ring oscillator 32 uses the delay characteristics of the inverter, and an odd number of inverters 34, 36, 38 are cascaded, and the output of the final stage inverter 38 is the first stage inverter. Returned to 34 and configured. Each of the inverters 34, 36, 38 is constructed, for example, as shown in FIG. When "1" or "0" is input to the first-stage inverter 34, it is delayed by each inverter 34, 36, 38, and after the elapse of a predetermined time, the last-stage inverter 38 outputs a signal of the opposite level to the first-stage input. , This is fed back to the first stage input. Therefore, the first-stage input is inverted and the same operation is repeated, which causes oscillation. Ring oscillator 32
The oscillation frequency of is determined by the delay time of the open loop.
Since the delay time of the inverter is controlled by the power supply voltage as described above, the oscillation frequency of the ring oscillator 32 is
It is controlled by 34, 36, 38.

The oscillation output of the ring oscillator 32 is waveform-shaped by the inverter 40 and then input to the comparator 42. Comparator 42
Compares the output signal of the inverter 40 with the reference frequency signal obtained by dividing the oscillation signal of the crystal oscillator 44 by the frequency divider 46, and outputs a pulse signal having a width corresponding to the difference. .

The control voltage generation circuit 48 smoothes the output pulse of the comparator 42 to generate the DC voltages Vc ₁ and Vc ₂ . This DC voltage Vc ₁ , Vc ₂ is input as a control voltage to the control inputs c1 and c2 of the inverters 34, 36 and 38 constituting the ring oscillator 32,
The applied voltage is controlled. Since the delay characteristics of the inverters 34, 36, 38 depend on the applied voltage as described above, if configured so as to provide negative feedback with the above loop, a so-called PLL (phase locked loop) will be created. From 32, extremely stable oscillator frequency (reference frequency accuracy) can be obtained. That is, each of the inverters 34, 36, 38 is controlled to have a constant delay time regardless of fluctuations in the power supply voltage and temperature.

By using the control voltages Vc ₁ and Vc ₂ obtained by the control voltage generation circuit 48 as another inverter control voltage placed under the same temperature and power supply voltage V _DD −V _SS conditions, the power supply voltage V _DD Therefore, a delay that is not affected by changes in V _SS and temperature can be obtained.

The analog signal that is the delayed signal is input to the FM modulation circuit 50 from the input terminal 49. The FM modulation circuit 50 is the inverter 5
A ring oscillator 52 is configured by connecting 4,56,58 in cascade, and feeding back the output of the final stage inverter 58 to the input of the first stage inverter 54. The inverters 54, 56, 58 are constructed, for example, as shown in FIG. To the control terminals c1 and c2 (see FIG. 6) of the inverters 54, 56 and 58, the control voltages Vc ₁ and Vc ₂ for stabilizing the delay time are input via the resistors 60 and 62. The analog signal input from the input terminal 49 is
Control voltage Vc ₁ , V via amplifier 61 and capacitors 64, 66
It is superimposed on c ₂ . Therefore, the voltage applied to the inverters 54, 56, 58 is modulated by the input analog signal, and the ring oscillator 52 outputs a pulse signal having a frequency corresponding to the level of the input analog signal. That is, the ring oscillator 52 outputs a signal obtained by pulse-FM modulating the input analog signal.

The output signal of the ring oscillator 52 is output from the FM modulation circuit 50 and input to the delay circuit 68. The delay circuit 68 is of a two-system control type in which a plurality of inverters 70, 72, ..., 80 are connected in cascade, and the one shown in FIG. 10 is used, for example. One of the two control systems is used for control by the control voltages Vc ₁ and Vc ₂ and performs stabilization control of delay time. The other one system is used to control the delay time by the delay time control voltage Vc ₃ . The delay time control voltage Vc ₃ is directly input to the control terminal c 3 (see FIG. 10). In addition, this voltage Vc ₃ is applied to the intermediate voltage between the power supply voltages V _DD and V _SS by the inverting amplifier 82. Inverts the reference voltage Vc ₄ = Create a _{(Vc 4 = V DD + V} SS -Vc 3), and inputs the voltage Vc ₄ to the control terminal c4 (see FIG. 10).

In this way, the delay time is continuously controlled by the control voltage Vc ₃ .

The output signal of the delay circuit 68 is input to the FM demodulation circuit (pulse count detection circuit) 84. The FM demodulation circuit 84 is a delay circuit
The demodulated signal input from 68 is input to a circuit in which an even number (here, 4) of inverters 86, 88, 90, 92 are cascaded,
The output signal of the final stage 92 is input to the exclusive OR circuit 94, the output of the exclusive OR circuit 94 is smoothed by the low-pass filter 96, and the extracted signal is guided to the output terminal 98 as a demodulation signal. By controlling the voltage applied to the inverters 86 to 92 with the control voltages Vc ₁ and Vc ₂ , accurate pulse FM with less distortion can be obtained.
Demodulation can be performed.

The operation of the circuit of FIG. 1 is shown in FIG. An analog signal as shown in FIG. 11A is input from the input terminal 49. This signal is pulse FM modulated by the FM modulation circuit 50,
It is modulated into a signal having a frequency according to the voltage level as shown in FIG. 11 (b). The output signal of the FM modulation circuit 50 is delayed by the delay circuit 68 as shown in FIG. 11 (c). This delayed signal is pulse FM demodulated by the FM demodulation circuit 84 and output terminal 98
Outputs a delayed analog signal as shown in FIG. 11 (d). The delay time T is variable by the control voltage Vc ₃ . Further, each inverter is controlled by the control voltages Vc ₁ and Vc _{2 so} that the delay time T is not affected by the fluctuation of the temperature and the power supply voltage, so that the delay is stably and accurately performed.

〔The invention's effect〕

As described above, according to the present invention, an analog signal can be delayed by passing pulse FM modulation → delay by CMOS gate → pulse FM demodulation. According to this, unlike the BBD and CCD, sampling by a clock is not performed, so that delay can be performed with high resolution and thus with low distortion. Also, the delay time can be continuously changed by the voltage applied to the CMOS gate.

Moreover, each CM of FM modulation circuit, variable delay circuit, FM demodulation circuit
Since temperature detection is performed using the CMOS gate on the same substrate as the OS gate and the power supply voltage of the CMOS gate of each of these circuits is controlled, temperature compensation can be performed with high accuracy.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention. FIG. 2 is a circuit diagram showing a CMOS gate circuit. FIG. 3 shows the power supply voltage in the CMOS gate circuit of FIG.
It is a characteristic view showing a delay time characteristic. FIG. 4 is a circuit diagram showing a state in which the CMOS inverters 10 of FIG. 2 are connected in cascade in plural stages to obtain a long delay time. FIG. 5 is a characteristic diagram showing power supply voltage-delay time characteristics when the CMOS inverters 10 of FIG. 2 are connected in cascade in 80 stages. FIG. 6 is a circuit diagram showing an example of a delay circuit using a CMOS inverter. FIG. 7 is an example of an IC pattern of the CMOS inverter of FIG. 8 to 10 are circuit diagrams respectively showing other examples of the delay circuit using the CMOS inverter. FIG. 11 is an operation waveform diagram of the circuit of FIG. 10,34,36,38,40,54,56,58,70,72, ..., 80,86,88,90,92…
… CMOS Inverter, 12 …… CMOS Inverter p
Channel MOS-FET, 14 ... n constituting a CMOS inverter
Channel MOS-FET, 16, 18, 24, 26 ... Control MOS-FET, 3
0 …… Delay time constant voltage generation circuit (delay time stabilization circuit), 49 …… Analog input terminal, 50 …… FM modulation circuit, 68
...... Delay circuit (variable delay circuit), 84 …… FM demodulation circuit, 98
...... Analog output terminal.

Claims (1)

[Claims] 1. An input analog circuit having an oscillation circuit configured by cascade-connecting CMOS gates and feeding back the output to the input side, and controlling the voltage applied to the CMOS gates according to an input analog signal. It has an FM modulation circuit that pulse-FM modulates a signal and a circuit in which CMOS gate circuits are connected in series.The pulse FM modulation signal output from the FM modulation circuit is input, and the delay time control signal is input from the outside. A variable delay circuit that delays the pulse FM modulation signal with a variable delay time by controlling the voltage applied to the CMOS gate, and a cascade connection of CMOS gates to which the pulse FM modulation signal output from this variable delay circuit is input. A delay circuit consisting of a circuit, an exclusive OR circuit which receives the output signal of this delay circuit and the input signal of this delay circuit as an input, and outputs an exclusive OR of these, and this exclusive OR circuit. A FM demodulation circuit having a low-pass filter that smoothes the output signal of the circuit, the FM modulation circuit, the variable delay circuit, and the CMOS gates of the FM demodulation circuit are connected in cascade on the same substrate as the CMOS gates and the output thereof is provided. Delay time to control the power supply voltage of each CMOS gate of the FM modulation circuit, the variable delay circuit, and the FM demodulation circuit according to the result of comparing the oscillation frequency of the oscillation circuit configured by feeding back to the input side with the reference frequency. An analog delay circuit characterized by having a stabilizing circuit.