JPH0734317B2 - Read-only memory address control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial field of application] The present invention relates to a read only memory (hereinafter referred to as a ROM).
Abbreviated as "), and particularly to a ROM address control circuit for reducing the area occupied by a read-only memory array incorporated in a semiconductor device.

[Conventional technology]

In a semiconductor device having a ROM, the built-in ROM usually has an address control circuit that fully decodes an address signal to select a ROM cell. If some of the built-in ROMs have the same ROM output data over different addresses, this type of ROM has been used in the past.
Used a method of reducing the memory size by compressing the address by the address control circuit.

FIG. 2 is a block diagram showing an example of a conventional ROM address control circuit. FIG. 3 is an example of an address control circuit having a predecoder circuit. A microprogram ROM is a typical ROM having the same ROM output data for a plurality of addresses described above. Therefore, the address control circuit of the microprogram ROM will be described below. FIG. 4 is a microprogram ROM cell selection signal / output value list showing an example of cell selection signals and output values corresponding to the address input of the microprogram ROM.

In FIG. 2, an address control circuit composed of a predecoder circuit 6, an address register 5, an X decoder circuit 4 as a row selection decoder circuit, and a Y decoder circuit 3 as a column selection decoder circuit is operated by the address signals A0 to A4. The ROM output is obtained by activating the X decoder output Xn and Y decoder output Yn that select the cells of the microprogram ROM array 1. 3 (a), 3 (b) and 3 (c) are detailed circuit diagrams of the X decoder circuit 4, the Y decoder circuit 3 and the predecoder circuit 6, respectively.

The X decoder circuit shown in FIG.
The output of the lower 3 bits of is decoded to generate eight kinds of outputs from X0 to X7, and is used as a signal for selecting the row of the microprogram ROM array 1.

The Y decoder circuit shown in FIG. 3 (b) decodes the output of the upper 2 bits of the address register 5 and outputs the 3 bits Y0 to Y2.
Produce the following decoded output and select the array 1 row of the microprogram ROM. The predecoder circuit 6 of FIG. 3 (c) receives the address signals A0 to A3 and outputs PD0 to PD3. FIG. 5 is a truth table showing the operation of the predecoder circuit shown in FIG. 3 (c).

[Problems to be solved by the invention]

The above-mentioned conventional micro program ROM address control circuit has a pre-decoder circuit as a means for compressing a memory address when a plurality of addresses have the same ROM output data. However, there is a drawback in that the delay time of the predecoder circuit is added. The object of the present invention has been made in view of the above-mentioned drawbacks, and the delay time caused by the predecoding circuit by configuring the X decoder circuit and the Y decoder circuit without using the previously required predecoding circuit. In addition to reducing the number of pixels, the X decoder circuit can be designed to enable geometrically regular mask design according to the pitch of the ROM array to contribute to the reduction of the occupied area on the semiconductor device. is there.

[Means for solving problems]

In the address control circuit of the ROM according to the present invention, the same output data exists at a plurality of addresses designated by the first specific address space designated by a plurality of bits other than the most significant bit of the predetermined address signal and designated by this address space. A micro comprising a redundant data storage area and a non-redundant data storage area in which different output data exist at a plurality of addresses designated by the second specific address space other than the first specific address space and designated by this address space. A program read-only memory, an address register for temporarily storing the predetermined address signal, an X decoder for decoding the address register output and outputting a row selection signal and a column selection signal of the microprogram read-only memory, respectively. Read-only memo with Y decoder The X decoder includes a first row selection decoder circuit for outputting a row selection signal for designating a first specific address space by using a plurality of consecutive lower bits of the predetermined address signal, and the lower row. A second row selection decoder circuit for outputting a row selection signal for designating a second specific address space other than the first specific address space by using a plurality of bits obtained by combining a continuous plurality of bits with the next higher bit The Y decoder outputs a column selection signal corresponding to the first row selection decoder circuit using the most significant bit of the plurality of lower consecutive bits and the most significant bit of the predetermined address signal. A column selection signal corresponding to the second row selection decoder circuit is generated by using one column selection decoder circuit and the most significant bit of the predetermined address signal. Consists of a selection decoder circuit, while the row selection to enable at least one of the first and the second row selection decoder circuit by using the most significant bit of the predetermined address signal,
Corresponding to this row selection, at least one of the first and second column selection decoder circuits is enabled to perform column selection.

〔Example〕

 Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. The address signals A0 to A4 of the microprogram ROM array 1 are stored in the address register 5 '. Of the address signals A0 to A3 excluding the highest address signals A4 and A4, A0 to A2 are X decoder circuits 3'. It is supplied to and is fully decoded and specifies addresses 0 to 15. Further, A0 to A3 are supplied to the X decoder circuit 4'and specify an address space other than the address space specified by A0 to A2, that is, addresses 16 to 31. The address A3 is also supplied to the AND circuits 101 and 102. The address register 5 serves as a means for selecting one of the outputs of the X decoder circuits 3'and 4'by the highest address signal and selecting one of the outputs Y0 and Y1 of the corresponding Y decoder circuits as well as Y2. The in-phase signal of the highest-order address signal A4 of ° C 'is X-decoder circuit 4'.
Supply to. This decoder circuit 4'has vertical transistors forming an AND logic, and transistors QXn (n = 0 to 0) having a logical product relationship with these transistors.
6) That is, the vertical product transistor is input to the gate electrode of a transistor Q _X n configured by adding another vertical product on the ground potential side, and the Y select transistor Q _A
Input to the gate electrode of. The highest address signal A ₄
Reverse phase signal is inputted to the first X-decoder circuit 3 'gate electrode of the transistor Q to vertical stack transistors constituting an AND logic in the relation of logical _Z n (n = _0~7) of. Further, by taking the logical sum of the output of the X decoder circuit 3'and the output of the second X decoder circuit 4 ', that is, by short-circuiting the outputs, the control signal X ₀ to selects the row of the microprogram ROM array 1. Got X ₇ .

Next, in the address control circuit of FIG. 1, the address signal A ₀
To A ₄ to describe the operation when the input from the address 0 to address 31.

From address 0 to 15 address is the address signal A ₄ is "0" ▲ ▼ the signal line is first X-decoder circuit 3 'is selected. This X decoder circuit 3'has an input address signal
FIG. 4 shows a full decoder circuit that fully decodes A0 to A2, and row selection signals Xn and column selection signals Yn to the microprogram ROM 1 when the address signals A0 to A4 are changed from 0 to 15 addresses. The same operation as that by the conventional address control circuit is performed, and as a result, the same memory output can be obtained.

Next, when the address signals A0 to A4 are changed from the 16th address to the 31st address, the address signal A4 becomes "1", so that a column selection signal different from the outputs of the X decoder circuit 4'and the Y decoder circuits 101 and 102 is activated. Next Y select transistor
Q _A is selected. FIG. 6 is a table showing the operation of the X decoder path 4'for the address signals A0 to A3 in the embodiment of FIG.

As described above, the address control circuit of FIG. 1 receives the address signals from address 0 to address 31
The same signal as the row selection signal Xn and the column selection signal Yn of the microprogram ROM 1 by the conventional address control circuit shown in the figure becomes active, and as a result, the cells of the same microprogram ROM are selected, and therefore, for the input address. The same output result can be obtained.

The transistors 301-1 to 301-8 and 401-1 to 401-7 are used as load transistors, respectively.

〔The invention's effect〕

As described above, according to the present invention, the X decoder and the first row selection decoder circuit for outputting the row selection signal that designates the first specific address space by using a plurality of lower consecutive bits of the predetermined address signal and the lower order A second row selection decoder circuit for outputting a row selection signal for designating a second specific address space other than the first specific address space by using a plurality of bits obtained by combining a plurality of consecutive bits of A first column in which the Y decoder outputs a column selection signal corresponding to the first row selection decoder circuit by using the most significant bit of a plurality of lower consecutive bits and the most significant bit of a predetermined address signal. Since it comprises a selection decoder circuit and a second column selection decoder circuit which uses the most significant bit of a predetermined address signal as a column selection signal corresponding to the second row selection decoder circuit, Because it can provide a structure that does not require a predecoder circuit having an address decoding control circuit, it can be greatly reduced delay time Ru due to predecoder circuit. Further, the second X decoder circuit, which is one of the constitutional requirements of the present invention corresponding to the predecode circuit, can be designed in accordance with the pitch of the array of the microprogram ROM, so that the mask can be designed geometrically and regularly. ,
This has the effect of significantly reducing the area occupied by the semiconductor device.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional ROM address control circuit, and FIGS. 3 (a), 3 (b), 3 (c) are FIG. 4 is a circuit diagram showing in detail the X decoder circuit 4, Y decoder circuit 3, and predecoder circuit 6 shown in FIG. 2, respectively. FIG. 4 is a list of cell selection signals and output values of the microprogram ROM shown in FIG. 5
FIG. 7 is a truth table showing the operation of the predecoder circuit shown in FIG. 3 (c), and FIG. 6 is a list showing the operation of the second X decoder circuit with respect to the address signal in the embodiment of FIG. 1 ... Microprogram ROM array, 2 ... Y selector circuit, 3 ... Y decoder circuit, 3 ', 4,4' ... X decoder circuit, 5,5 '... address register, 6 ... predecoder circuit , 101, 102 ..., 301-1 to 301-8, 401-1 to 4
01-7 …… Transistor, Q _{A to} Q _E …… Transistor, Q ₁
〜 Q ₂₀ ,, Q _X0 〜 Q _X6 , Q _Z0 〜 Q _Z7 …… Driver transistor.

Claims (1)

[Claims] 1. A redundant data storage area which is mapped to a first specific address space designated by a plurality of bits other than the most significant bit of a predetermined address signal and has the same output data at a plurality of addresses designated by this address space. , The first
A non-redundant data storage area that is mapped to a second specific address space other than the specific address space and has different output data at a plurality of addresses designated by this address space. A read-only memory including an address register for temporarily storing a predetermined address signal, and an X decoder and a Y decoder for decoding the address register output and outputting the row selection signal and the column selection signal of the microprogram read-only memory, respectively. The X decoder includes a first row selection decoder circuit for outputting a row selection signal for designating a first specific address space by using a plurality of consecutive lower bits of a predetermined address signal, and the lower sequence. The next higher bit is combined with the A second row selection decoder circuit for outputting a row selection signal for designating a second specific address space other than the first specific address space by using the plurality of bits provided by the Y-decoder. A first column selection decoder circuit for outputting a column selection signal corresponding to the first row selection decoder circuit by using the most significant bit of the plurality of bits and the most significant bit of the predetermined address signal, and the predetermined address signal. Of the second row selection decoder circuit using the most significant bit of the second column selection decoder circuit as a column selection signal corresponding to the second row selection decoder circuit, and using the most significant bit of the predetermined address signal At least one of the second row selection decoder circuits is enabled to perform row selection, and the first and second column selection decoder circuits corresponding to this row selection are selected. Without even address control circuit of the read only memory, characterized by column selection enable one.