JPH073837B2 - Semiconductor integrated circuit - Google Patents

Description

Description: TECHNICAL FIELD OF THE INVENTION The present invention relates to a semiconductor integrated circuit having programmable chip functions.

[Technical background of the invention and its problems]

In recent years, the following LSIs have emerged in response to the demand for a large number of small quantities.

(1) Standard cell method The circuit block having the basic logic function used in the LSI is registered in the computer in advance, and these circuit blocks are arranged and wired by the automatic processing of the computer to obtain the desired final product. To get

(2) Gate array method The basic circuits that make up the logic gates are arranged in an array on the wafer in advance, and the wiring pattern is determined on this by automatic wiring as in the standard cell method, and the desired LSI
To get

Although these have a shorter development period than fully hand-designed LSIs, they require a manufacturing process using lithography technology.
There is a problem that it takes several weeks to several months from the completion of design to the completion of LSI.

On the other hand, the following method has been proposed by the applicant (Japanese Patent Application No. 58-157718).

That is, as shown in FIG. 2, a plurality of circuit blocks 1a, 1b, ...
The wiring process is completed by the method of C and it is built into the board,
The input and output signals of each circuit block are electrically turned on and off.
Guided by the switch matrix that can write the FF state,
All input signals of each circuit block can be connected via a switch element 7 such as an E ² PROM or a MOSFET having a 1-bit memory. Reference numeral 3 is a T-shaped signal output wiring, and 4 is a signal input wiring.

According to this method, since the method is field programmable, the user can obtain a desired LSI having a high function remarkably quickly by writing the logic function by himself. Moreover, the LSI can be designed in a form in which the input signal and the output signal of the circuit block having a certain fixed logic function are connected, which is easy for a designer who is accustomed to the logic design on the board to understand.

In this new method, as the input / output terminals of the completed LSI, there are signal terminals originally required for the operation of the LSI and signal terminals for writing ON / OFF information of the switch matrix. ON / OFF information of the switch matrix can be written by this write signal terminal. There is a problem that it is necessary to perform a complicated test using the input / output terminals of the completed LSI to judge whether or not the information is written correctly.

[Object of the Invention]

The present invention is an improvement of the above-mentioned drawbacks. Whether or not the ON / OFF information of the switch matrix is written correctly and what is wrong is added by adding a simple circuit and a few external terminals. It is an object of the present invention to provide an LSI that can be discriminated by various test patterns.

[Outline of Invention]

The present invention is directed to a switch matrix in which input signals and output signals of a plurality of circuit blocks having a basic logical function shown in Japanese Patent Application No. 58-157718 are electrically guided into a switch matrix, and a circuit is provided. In a logic circuit in which all output signals of a block can be connected to all input signals through switch elements, a first switch element row that electrically disconnects all output signals of the circuit block from the switch matrix, A first shift register for transmitting a signal to an output line of the circuit block; a second switch element row for reading information of an input line of the circuit block connected to the output line of the circuit block; The ON / OFF state of the switch matrix can be inspected by the shift register.

The first shift register may be connected to the input line and the second shift register may be connected to the output line.

〔The invention's effect〕

According to the present invention, whether or not a rewritable switch matrix used for realizing a desired logic function in a semiconductor integrated circuit capable of easily realizing a logic integrated circuit having a desired logic function is written as desired, By adding a simple circuit and some external terminals, it is possible to inspect by a simple test pattern. In addition, since it is possible to know what went wrong, it becomes easy to rewrite the switch matrix.

Example of Invention

 Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings.

First, the layout will be described with reference to FIG.

That is, the circuit blocks 1a, 1b ... 1N are formed on one side of the Si wafer, each circuit block has a 4-input NAND gate, etc., and the logic function element has a CMOS structure, and a dedicated IC, that is, a handwritten cell in the standard cell system. It is a standard cell or a wired gate array. The complex logic function element may be formed by combining standard cells by mutual wiring by the standard cell method.

The structure of the circuit block is as follows.

Block with 2 4-input NAND gates 15 blocks Block with 2 2-input NAND gates 14 Block with 8 input NAND gates 1 Block with 4 inverters 100 Blocks of 8 bit registers … 19 blocks with two D-type flip-flops… 19
Blocks with two 4-input AND gates Blocks with four 2-to-1 data selectors ... 13 Blocks with two 4-bit binary counters ... 11 Blocks with two 2-4 line decoders ... 7 3 Blocks with 8 line decoder ... 3 Blocks with 2 4-1 selectors ... 5 Blocks with 8-1 selectors ... 4 Blocks with 8-bit serial input-parallel output shift register ... 3 Blocks 8 bit parallel Block with input-serial output shift register ... 3 blocks with 8-bit serial input-serial output shift register ... 2 Block with two monostable multivibrator ... 4
Block with 4 2-input OR gates 4 Block with 4 2-input NOR gates 3 Block with 2 AND-OR inverters 3 Blocks of 64-bit RAM 3 3 2-input EXCLUSIVE-OR Blocks with 4 gates 2 blocks with 4 bit comparators 3 blocks with 2 JK flip-flops 4 blocks 9 bit even / odd parity generator / checker block 3 blocks 4 bit binary all Adder block ... Block with two 2-input multiplexers ...
5 blocks with 4 8-R latches 2 blocks ALU block 1 block 8-bit addressable latch block 1 block Look-ahead carriage generator block 1
That is, a circuit block consisting of 274 MSIs is provided.
It is made possible to create LSIs of all functions from seed chips. The average number of inputs of each circuit block is 8 and the number of outputs is 4. Input of logic function element,
The output section serves as an input section and an output section of the circuit block, but the output section is provided with an output buffer (not shown). The output portion is connected to the T-shaped signal output wiring 6, and the input portion is connected to the signal input wiring 4 intersecting with the T-shaped signal output wiring 6. Then, switch elements 7 and 8 that are ON / OFF controlled by a decoder are provided at the intersections. Therefore, the wiring between the input and output sections is basically one switch, and the equipotential wiring length associated with one current path is 2.5 l on average with the side length of the chip as l as can be seen from FIG. The delay due to the time constant is prevented by pressing.

In the circuit of FIG. 2, ON and O of the switch matrix 2
In order to check the FF state, a complicated test pattern considering the operation of the circuit block group 1 is required.

The present invention improves on this point, and a typical example thereof is
Shown in the figure. Here, the first switch element row 9 is shown in FIG.
And the first shift register 11 and the second shift register 14
And a second switch element row 17 are added.

The first switch element row 9 is electrically connected using the external terminal 10.
When turned off, the tested switch matrix 2 is not affected by the output 3 of the circuit block 1. Next, by operating the first shift register using the external input terminal 12 and the clock input 13, the output signal line 3 of the circuit block in the switch matrix can freely determine the High state and the Low state. These states are
When the second switch element row 17 is turned on by the external terminal 18, it is set to the input of the second shift register. Then, the second switch element array 17 is turned off by the external terminal 18, so that the second shift register 14 is not affected by the switch matrix 2. Here, the information of the second shift register is transferred to the external terminal 15 using the clock input 16.
Can be read one after another through. In this way, since it is possible to give and read signals to the switch matrix independently of the circuit block 1, it is possible to check the ON / OFF state of the switch matrix from this information.

This inspection method is shown in Figure 3,
This will be described with reference to FIG.

FIG. 3 shows an example of a circuit block having three output lines and six input lines. FIG. 4 shows a part of the connection analysis of the matrix of this circuit. First, the signal SI is set to LOW potential by the external terminal to electrically turn off the first switch row 9. At this stage, output 3 of circuit block 1
Are electrically disconnected from the signal 3'on the switch matrix. The shift registers 9 and 14 used here are
It is assumed that the shift is performed at the rising edges of the clock signals C1 and C2. The external input terminal 12 and the clock input terminal 13 are operated in the fourth manner. That is, C1 is clocked twice with DI kept LOW, then DI is driven High and C1 is clocked. As a result, the signal line 3-1 becomes High, 3-2, 3-3.
Goes low (point A). After that, when the signal S2 is set to High by the external terminal 18 and the second switch element 17 is turned on, only the input signal line 4 of the circuit block 1 connected to the signal 3-1 becomes High and the second shift is performed. The input of register 14 is set. Next, the second switch element row 17 is turned off by the external terminal 18, and the clock input 16 of the second shift register 14 is operated. In this case, the clock signal
The signal DO of the external output terminal 15 is High at the 1st and 6th times of C2.
become. Therefore, it can be seen that the output of the first circuit block 1 is connected to the inputs of the first and sixth circuit blocks.

[Other Embodiments of the Invention]

(1) When the second switch element row 17 is turned on, the data output from the first shift register 11 and the data output from the second shift register 14 overlap in the form of wired OR. If the drive capacity of the output Q of the first shift register 11 is sufficiently larger than the drive capacity of the output Q of the second shift register 14, the data of the first shift register 14 is correctly read into the second shift register 14. Be done.

Further, in order to ensure this operation, a shift register in which the output Q of the second shift register 14 can be turned on and off by an external terminal may be used.

Also, during normal circuit operation, the output of the circuit block 1 may overlap with the output of the shift register in the form of wired OR. In order to ensure the operation of the output of the circuit block 1, it is preferable to use a similar shift register as the first shift register 11.

FIG. 5 shows a conventional shift register, and FIG. 6 shows an embodiment of a shift register in which Q output can be turned on and off by an external terminal.

In FIG. 5, the output 20 of the ordinary shift register 19 is directly connected to the signal line 21 of the switch matrix 2. In FIG. 6, a switch element controlled by the external terminal 23
The output 20 of the shift register 19 is connected to the signal line 21 of the switch matrix 2 facing the line 22.

(2) The external terminal 10 of the first switch element row 9 and the external terminal 18 of the second switch element row 17 can be made common. That is, when the second switch element row 17 is turned on during the inspection of the switch matrix 2, the information of the switch matrix is taken into the second shift register row 14, and then the second switch element row 17 is turned off. I hope this information is available. Therefore, as shown in FIG. 7, the external terminal 24 is connected to the second switch element row 17, and further inverted by the inverter 25 to be connected to the first switch element row 9. When inspecting the switch matrix 2, the first switch element row 9 is turned off, and the second switch element row 9 is turned off.
The first shift register is turned on by turning on the switch element row 17 of
When data can be obtained for the signal 3 by 11, the data of the signal 4 is set in the second shift register 14. At this time, if the second switch element row 17 is turned off and the first shift register 11 is turned on by the external terminal 24, the output data of the circuit block 1 enters the switch matrix, but the second switch element row 17 is Since it is off, it does not affect the second shift register 14, and the data of the signal 4 can be read correctly.

The same thing can be done in the case of FIG. In FIG. 8, a delay circuit 26 is used instead of the inverter 25 shown in FIG. In the inspection method, the first and second switch element arrays 9 and 17 are turned off by the external terminal 24, and the data is written in the signal 3 by the first shift register array 11. After that, the switch element row 17 is turned ON and then turned OFF by the external terminal 24.
The data of the signal 4 during this period is the second shift register string 17
Is set to. At this time, the switch element row 9 is also turned on, and the output data of the circuit block 1 enters the switch matrix 2. However, since the delay circuit 26 shifts this timing, the data set in the second shift register row 14 Is unaffected.

Further, it goes without saying that a system combining FIG. 7 and FIG. 8 is also possible.

(3) Also, for example, the external input terminals 10, 12, shown in FIG.
Since 13,18 are the terminals for the switch matrix inspection, they are not relevant when operating as a normal LSI. Therefore, these terminals must be fixed so as not to affect them during normal operation. Because of this, it is not economical to use the pins of the LSI package. Therefore, unless touching these terminals except during the switch matrix inspection, it is desirable that they be fixed to a potential that does not interfere with normal operation.

This is the input buffer 27 as shown in FIG. 9 and FIG.
This can be realized by using a resistor 29 having one end connected to the power supply V _DD 28 or the ground line V _SS 30, depending on whether the switch is P-ch or N-ch.

[Brief description of drawings]

FIG. 1 is a plan view illustrating the present invention, FIG. 2 is a plan view of a programmable LSI, FIG. 3 is a small-scale plan view showing the present invention, and FIG. 4 is a switch matrix of FIG. Waveform diagram of the test program for inspecting
FIG. 6 is a circuit diagram showing a conventional shift register, FIG. 6 is a circuit diagram showing another embodiment of the present invention, FIGS. 7 and 8 are circuit diagrams showing another embodiment of the present invention, and FIG. , FIG. 10 is a circuit diagram showing another embodiment of the present invention. In the figure, 1 ... Functional block, 2 ... Switch matrix, 3 ... Output signal line of circuit block, 4 ... Input signal line of circuit block, 5 ... To connect output signal line 3 and input signal line 4 in switch matrix Signal line 6, contact point of output signal line 3 and signal line 5, 7 ... OFF state at intersection of switch matrix, 8 ... ON state, 9 ... First switch element row, 10 ... External terminal thereof, 11 ... 1 shift register, 12, 13, ... External data input terminal and clock input terminal of first shift register group, 14 ... Second shift register,
15 ... External output terminal of the final stage of the second shift register, 16
... Clock input external terminal of second shift register group, 17
... second switch element array, 18 ... external terminal thereof, 19 ... shift register, 20 ... output terminal thereof, 21 ... output signal line or input signal line of circuit block, 22 ... switch element, 23,2
4 ... External terminal, 25 ... Inverter, 26 ... Delay circuit, 27 ... Input buffer, 28 ... Power supply, 29 ... Ground, 30 ... Resistor.

Claims (5)

[Claims] 1. A plurality of circuit blocks, each having a logical function itself and having a signal input portion and a signal output portion, which are built in a substrate, and adjacent to a circuit block region formed by the plurality of circuit blocks. And a wiring region formed on the substrate, the circuit block region is composed of a set of a plurality of types of logic function elements, and the wiring region is a signal wiring group including signal input wirings and signal output wirings intersecting each other. The signal wiring group is connected to each circuit block, and this connection is made in the wiring region adjacent to the circuit block, and a switching element is provided at each intersection with the signal wiring group. O of this switch element
A semiconductor integrated circuit in which the input / output relationship of signals between the circuit blocks is determined by controlling the N and OFF states, and a desired integrated circuit is constructed, wherein the circuit block area and the wiring area are A first shift register is provided on either one of the signal input wiring or the signal output wiring via a first switch element row, and the signal output is provided at a position opposite to the circuit block area with respect to the wiring area. A semiconductor integrated circuit characterized in that a second shift register is provided on either one of the wiring and the signal input wiring via a second switch element row. 2. In at least one of the first and second shift registers, the connection between the output of the shift register and the input / output terminals of the circuit block can be electrically turned on and off by an external terminal. The semiconductor integrated circuit according to claim 1, wherein a shift register is used. 3. The first switch element row and the second switch element row are electrically turned on and off from the same external terminal, and their on and off relations are reversed or have a delay relation. The semiconductor integrated circuit according to claim 1 or 2, wherein the semiconductor integrated circuit is provided. 4. An input buffer for fixing an external terminal of a switch element array such that the first switch element array is in an electrically ON state and the second switch group is in an OFF state when there is no external input. The semiconductor integrated circuit according to any one of claims 1 to 3, wherein the semiconductor integrated circuit comprises: 5. An input buffer for fixing clock input external terminals of the first and second shift registers so that at least one of the first and second shift registers does not operate when there is no external input. The semiconductor integrated circuit according to any one of claims 1 to 4.