JPH0740311B2 - Image processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial field of use B Outline of the invention C Conventional technology D Problems to be solved by the invention E Means for solving problems (Fig. 1) F Action G Example G ₁ Description of image processing device ( Fig. 1) Description of the address generator of G ₂ PVP (30B) (Figs. 1 and 2)
Fig.) G ₃ Description of an example of three-dimensional processing (Figs. 3 and 4) H Effect of the invention A Industrial field of application This invention writes input image data into a memory once and performs various processings on it. The present invention relates to an image processing device that is configured to perform the processing.

B Outline of the Invention In the present invention, the first two-dimensional address signal (X, Y) is generated by the first address generating means, and the Z signal having a value corresponding to the first two-dimensional address signal is generated by the Z memory means. Output based on the first two-dimensional address signal and the Z signal, X ′ = X + Zsin θ (θ is a desired rotation angle) and Y ′ =
The second two-dimensional address signal is generated by Y by the second address generation means, and the first two-dimensional address signal (X, Y) is generated.
And the second two-dimensional address signal (X ′, Y ′) is supplied to the input image memory and the output image memory as a read address signal and a write address signal, respectively, and the two-dimensional input image represented by the input video signal is By storing in the output image memory as a two-dimensional output image that has been rotated and moved by the rotation angle θ in the three-dimensional space, 3
It is designed to effectively perform dimensional processing.

C Prior Art Various video image processing systems have been proposed (for example, IEICE Transactions 85/4 Vol.J68-D No. 4, JP-A-58-).
215813).

FIG. 5 shows an example of this video image processing apparatus.

In general, this type of processing apparatus has an input / output unit (1), an input image memory (2A) and an output image memory (2A) as shown in FIG.
Memory unit (2) consisting of B) and data processing unit (3)
It consists of and.

The input / output unit (1), for example, A / D-converts the video signal from the video camera (4) into digital image data, writes this in the input image memory (2A), and outputs it from the output image memory (2B). Read the processed image data, convert it to D / A and return to analog video signal, record it on VTR (5) or supply it to monitor receiver (6) so that video image can be monitored. To

Therefore, the write address of the input image memory (2A) and the read address of the output image memory (2B) of the input / output unit (1) are generated.

The processor of the data processing unit (3) is composed of one or a plurality of processors, and the microprogram as the contents of the microprogram memory can be exchanged when the range of processing is further expanded.

For this reason, the data processing unit (3) uses the input image memory (2A)
And a write address for the output image memory (2B) are generated, and a calculation process for processing the image data from the input image memory (2A) is performed.

Writing and reading to and from the memory unit (2) are performed in units of an image, that is, in units of one field or one frame. Therefore, each of the input image memories (2A) and (2B) has a plurality of memories each having a capacity of one field or one frame of image data.

In this case, since the monitor display of the video image is a two-dimensional display, the image processing is conventionally handled in a two-dimensional manner, and the address is generally generated from information in two directions, that is, two-dimensional information. .

D Problems to be Solved by the Invention As described above, the image is displayed two-dimensionally. However, it is a two-dimensional projection of what originally existed in the three-dimensional world by orthographic projection or single point projection. Therefore, although the original object often changes or moves three-dimensionally, if the image is handled two-dimensionally as in the conventional case, the situation of the three-dimensional change or movement state can be accurately identified. Processing that can be expressed in is difficult.

E Means for Solving Problems In the present invention, an input image memory (20A) for storing an input video signal, and an output image memory (20B) for storing a video signal output from the input image memory (20A)
And an address generator ((301), (302) for generating a read address signal of the input image memory (20A) and a write address signal of the output image memory (20B). 302) is a first address generating means (301) for generating a first two-dimensional address signal (X, Y), and a Z signal having a value corresponding to the first two-dimensional address signal (X, Y). Based on the first two-dimensional address signal (X, Y) and the Z signal, and Z '= X + Zsinθ (θ is a desired rotation angle) and Y' = The second two-dimensional address signal (X ′,
Y ') and second address generating means (302), and the first two-dimensional address signal (X, Y) and the second two-dimensional address signal (X', Y ') are read addresses. Are supplied to the input image memory (20A) and the output image memory (20B) as signals and write address signals, respectively.
The two-dimensional input image represented by the input video signal is stored in the output image memory (20B) as a two-dimensional output image that is rotated and moved by the rotation angle θ in the three-dimensional space.

F action The first two-dimensional address signal (X, Y) is generated by the first address generation means (301), and the Z signal having a value corresponding to the first two-dimensional address signal (X, Y) is Z. Memory means (30
Output in 3), and the first two-dimensional address signal (X, Y)
And the Z signal, the second two-dimensional address signal (X ′, Y ′) is converted into the second address generating means (X ′ = X + Zsin θ (θ is a desired rotation angle) and Y ′ = Y). 30
2), the first two-dimensional address signal (X, Y) and the second two-dimensional address signal (X ', Y') are respectively input as the read address signal and the write address signal in the input image memory (20A). And the two-dimensional input image shown by the input video signal supplied to the output image memory (20B),
It is stored in the output image memory (20B) as a two-dimensional output image that is rotated and moved by the rotation angle θ in the three-dimensional space.

G Embodiment G ₁ Description of Image Processing Device FIG. 1 shows an embodiment of the overall outline of a video image processing device in which the device of the present invention is operated. This example is an example of realizing high-speed data processing. Is.

That is, in this example, the data processing unit is mainly a processor system that calculates pixel values (hereinafter referred to as PIP) (30A) and a processor system that manages data flow management such as address management and timing of processing (hereinafter (PVP) (30
B) and divide.

In the conventional data processing section, the processing time that is the sum of the processing times of both is required, whereas if it is divided in this way, the processing time of the larger one of the two will be sufficient (Japanese Patent Laid-Open Publication No. Sho.
58-215803). Therefore, in the case of this example, high-speed processing that enables video data processing to be performed in real time can be performed.

Further, in the figure, (10) is an input / output unit (hereinafter referred to as IOC), (20) is a memory unit (hereinafter referred to as VIM), which is an input image memory (VIMIN) (20A) and an output image memory (VIA).
MOUT) (20B). (40) is a processor (hereinafter referred to as TC) as an overall controller that controls execution, stop, and program exchange of processing.

The IOC (10) A / D-converts the video signal from the video camera or VTR, writes it as an image image in the input image memory (20A), and outputs the processed image from the output image memory (20B) as described above. Read, D / A convert, and output to a monitor.

In this case, the signal that can be input / output to / from the IOC (10) is an NRSC system or R, G, B system video signal, and the system is designated by the TC (40). Further, one pixel is, for example, 8-bit data.

VIM (20) has multiple frame memories, eg 12 765
It consists of × 512 bytes of frame memory. In this example, these 12 frame memories are not used in a fixed manner, and the input image memory (20A) and the output image memory (2
0B) and can be freely assigned to. In addition, the memories are used as a set of two, and when one is in the writing state, the other can be read from, and the processing from the outside of the VIM (20) by the IOC (10),
Processing inside the VIM (20) by the PIP (30A) and PVP (30B) can be performed in parallel.

In this case, multiple frame memories of this VIM (20) are under the control of IOC (10) or PVP (30
The control mode signal which is under the control of B) is IOC (10).
More generated and supplied to VIM (20).

The PIP (30A) and PVP (30B) are basically the same architecture, and are independent processors consisting of a control unit, an arithmetic unit, a memory unit, and an input / output port, each of which has a multiprocessor configuration including a plurality of unit processors, Higher processing speed is mainly achieved by the parallel processing method.

The PIP (30A) has, for example, 60 PIP processors and several sub processors, and processes image data from the VIM (20) or generates image data inside this PIP.

PVP (30B) has, for example, about 30 processors, and VIM
It controls the flow of image data inside the VIM (20) such as allocation and collection of pixel data from (20) to PIP (30A).

That is, the PVP (30B) generates address data and control signals for the VIM (20), and these are generated by the VIM (20).
Supply to the PIP (30A) and generate input / output control signals for PIP (30A) and other control signals.
0A).

The input image memory (20
Not only when processing only the data from one frame of A) and writing the processed data to the output image memory (20B), but also using the data that spans multiple frames from the multiple frame memory May be done.

The number of calculation digits in PIP (30A) and PVP (30B) is 16 bits as standard, and the calculation processing of image data processing has a processing speed that can process one frame of image data within one frame, that is, real-time processing. Made possible. However, there are some processes that require a processing time of one frame or more.

In this case, the image data processing by PIP (30A) and PVP (30B) is performed in synchronization with the frame. Therefore, PVP (3
A processing start timing signal PS synchronized with the frame is supplied to 0B) from the IOC (10). On the other hand, from the PVP (30B), a signal OK indicating that one process is completed is supplied to the IOC (10). The processing start timing signal PS is generated at the IOC (10) from the frame start signal indicating the first line of each frame and the processing end signal OK.

When processing is performed in real time, the signal OK is always obtained at the end of each frame, so the signal PS becomes the same signal as the frame start signal FL.

On the other hand, if the processing time is longer than one frame, the signal PS
Is not the frame period and is obtained at the beginning of the next frame when the signal OK is output.

Then, the processing start timing signal PS from the IOC (10) is set to P
When the core processor of the VP (30B) detects it programmatically, this processor runs and other processors (PI
(Including P), a timing signal is output by a program to supply an address to VIM (20), image data is read from VIM (20), and processing is performed by PIP (30A).
When the processing is completed, the signal OK is output and the processing is stopped, and the next processing start timing signal PS is waited for.

In this case, only the image signal portion excluding the sync signal and the burst signal is targeted for processing, and the data read from the VIM (20) does not include the sync signal and the burst signal. For this reason, this IOC (10) has a built-in ROM that generates the synchronization signal, burst signal, and vertical blanking signal. In the case of the NTSC signal, the data from VIMOUT (20B) (recombined if necessary) Send to D / A converter together with sync signal, burst signal and vertical blanking signal.

Further, even in the case of the three primary color signals, an external synchronization signal is necessary, and this is also generated by this IOC (0) and supplied to a monitor or the like.

G ₂ PVP (30B) of the address generating unit of description PVP (30B) is the read address for the VIMIN (20A),
It generates a write address for VIMOUT (20B). Therefore, the first address generator (301)
A second address generator (302) is provided in the PVP (30B).

These first and second address generators (301) and (30
2) has an address calculation unit in three X, Y, and Z directions that are orthogonal to each other, and has a structure that enables three-dimensional address calculation.

That is, FIG. 2 shows an example of the structure of the first address generation unit (301), and the second address generation unit (302) has the same structure.

The address generation unit (301) includes an X-direction address calculation generation unit (301X) and a Y-direction address calculation generation unit (301Y).
And a Z-direction address calculation generator (301Z).
These X, Y, and Z address calculation units (301X) (301X
Since Y) (301Z) has exactly the same structure, the same number is assigned to the corresponding part in the address operation generation units (301X) (301Y) (301Z) in each direction, and the suffix X, Y, Z is added to this number. Is attached and shown. And in this case X
Only the directional address calculation generator (301X) will be described.

That is, the address calculation generation unit (301X) uses the multiplier (311X
X), an adder / subtractor (312X), a coefficient memory (313X), a data memory (314X), and 11 registers (321X) to (33X).
1X) and tristate buffers (341X) to (343X).

Whether to enable the outputs of registers (321X) to (329X), whether to operate the multiplier (311X), and registers (323X) (324X) (328X) (329X) (330X) (33
It depends on the microinstruction whether or not to take in the data to 1X).

The tri-state buffers (341X) to (343X) are also controlled by microinstructions.

Then, the input data is supplied to the register (321X), and the output data is taken out from the register (331X). Coefficient data such as cos θ and sin θ is stored in the coefficient memory (313X), and is appropriately fetched by microinstruction.

The data memory (314X) stores the output address data generated as needed.

Then, as shown in the figure, the calculation generator for the three directions (301X)
The (301Y) and (301Z) are connected to each other, and the address calculation result of the other direction is appropriately used for the address calculation generation of each direction.

In the case of this example, each adder / subtractor (312X) (312Y) (312X
The output of Z) is supplied to the register so that it becomes the input of the multiplier (311X) of the address calculation generator in the other two directions, and the output of each adder / subtractor (312X) (312Y) (312Z) is once What is captured in the register is supplied to the register so as to be input to the adder / subtractor of the address calculation generator in the other two directions.

It goes without saying that the method of connecting the respective operation generation units (301X) (301Y) (301Z) is not limited to this.

The two address generation units (301) (30) configured as above
2) can be used to generate addresses suitable for three-dimensional processing.

In this example, the PVP (30B) has X,
When represented by address information in the Y direction, three-dimensional position information of the original object appearing as this image, that is, depth information is stored in the memory (303). This depth information is obtained by calculation as Z = Z (X, Y), and this value is previously written and stored in the memory (303) from the host computer through the TC (40).

G ₃ Description of an example of a three-dimensional process A process of rotating an object in a three-dimensional space will be described below as an example of a three-dimensional process.

For example, consider a case where a rectangular parallelepiped in a three-dimensional space as shown in FIG. 3 is rotated by θ with respect to a straight line A parallel to the Y axis as shown in the figure. At this time, an arbitrary point (X ₁ , Y ₁ , Z ₁ ) on the rectangular parallelepiped is (▲ X ^' ₁ ▼, ▲ Y ^' ₁ ▼, ▲ Z ^' ₁
▼), but ▲ X ^′ ₁ ▼, ▲ Y ^′ ₁ ▼, ▲ Z ^′ ₁ ▼ can be obtained as follows.

Thus, from the first address generating unit (301) from X _1, Y ₁ the second address generator by giving a Z ₁ from the memory (303) to the second address generating unit (302) (302) ▲ X ^' ₁ ▼, ▲ Y ^' ₁ ▼, ▲ Z ^' ₁ ▼ can be obtained, and the rotated figure can be obtained in the output image memory (20B).

FIG. 4A is a flowchart of a program executed by the first address generator (301), FIG. 4B is a flowchart of a program executed by the PIP (30A), and FIG. 4C is a second address generator. The flowcharts of the programs executed in (302) are shown respectively.

That is, among the addresses in the three directions from the first address generation unit (301), the addresses in the X and Y directions are sequentially supplied to VIMIN (20A) from "0", and the input image data for all one screen is sequentially output. It is read and input to PIP (30A).

The image data input to PIP (30A) is VIMOUT
It is sent to (20).

On the other hand, the addresses in the X and Y directions from the first address generation unit (301) are supplied as inputs to the operation generation units (302X) and (302Y) in the X and Y directions of the second address generation unit (302). And supplied to the Z memory (303),
An address in the Z direction is obtained from this memory (303) by Z = Z (X, Y), and this is the second address generation unit (302).
The second address generation unit (302), which is supplied as an input to the Z direction operation generation unit (302Z), receives the address information in these three directions and performs the calculation (a) described above.
After the rotational movement, the address information in three directions is obtained, and among the addresses in the three directions, the addresses in the two directions ▲ X ^' ₁ ▼ and ▲ Y ^' ₁ ▼ (▲ X ^' ₁ ▼, ▲ Y ^' ₁ ▼) are used. (X ₁ ,
The data of Y ₁ ) is written to VIMOUT (20B). Therefore, the data written in this VIMOUT (20B) is X =
By sequentially reading from addresses 0 and Y = 0, an image after rotationally moving in the three-dimensional space by θ in FIG. 3 can be obtained on the monitor screen.

In the above example, the VIMIN (20A) address and VIMONT
The address of (20B) was read and written with the same two-direction X, Y address, but the address of memory (20A) is X, Y.
By changing the direction of the two-dimensional address such that the direction and the address of the memory (20B) are the X and Z directions, it is possible to easily obtain an image of the object viewed from different directions.

H Effect of the Invention In the present invention, the first two-dimensional address signal (X, Y) is generated by the first address generating means, and the Z signal having a value corresponding to the first two-dimensional address signal is stored in the Z memory. Output by the means and based on the first two-dimensional address signal and the Z signal, an arithmetic expression X ′ = X + Zsin θ (θ is a desired rotation angle)
And a second two-dimensional address signal is set to the second by Y '= Y.
Of the first two-dimensional address signal (X, Y) and the second two-dimensional address signal (X ',
Y ') supplies the read address signal and the write address signal to the input image memory and the output image memory, respectively, and the two-dimensional input image represented by the input video signal is rotated by the rotation angle θ in the three-dimensional space. The two-dimensional output image is stored in the output image memory. That is, 2
In order to generate a two-direction address for an image memory having a three-dimensional structure, the three-dimensional data is handled in the generation process so that the data in each direction are closely related to each other. It is possible to effectively perform the three-dimensional processing as if rotated by.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of an image processing apparatus according to the present invention, FIG. 2 is a block diagram of the configuration of an example of a main part thereof, and FIG.
FIG. 4 is a diagram for explaining an example of the three-dimensional processing, and FIG. 4 is a flowchart of the operation of each part for the three-dimensional processing.
FIG. 5 is a block diagram of an example of the image processing apparatus. (20A) is the input image memory, (20B) is the output image memory,
(301) is a first address generation unit, (302) is a second address generation unit, and (301X) (301Y) (301Z) is an X, Y, Z three-way address calculation generation unit.

Claims (1)

[Claims] 1. An input image memory for storing an input video signal, an output image memory for storing a video signal output from the input image memory, a read address signal of the input image memory and a write address of the output image memory. An address generation unit for generating a signal, wherein the address generation unit includes first address generation means for generating a first two-dimensional address signal (Y, Y), and the first two-dimensional address signal. Z memory means for outputting a Z signal having a value corresponding to (X, Y), and an arithmetic expression X '= X + Zsinθ (θ) based on the first two-dimensional address signal (X, Y) and the Z signal. A desired rotation angle) and second address generating means for generating a second two-dimensional address signal (X ', Y') according to Y '= Y. , Y) and The second
Two-dimensional address signals (X ', Y') are supplied to the input image memory and the output image memory as the read address signal and the write address signal, respectively.
The two-dimensional input image shown by the input video signal is 3
An image processing apparatus characterized by being stored in the output image memory as a two-dimensional output image rotated and moved by the rotation angle θ in a three-dimensional space.