JPH0748184B2 - Signal output circuit - Google Patents

Description

The present invention relates to a signal output circuit, and more particularly to a signal output circuit of a microcomputer.

[Conventional technology]

Conventionally, a signal output circuit of a microcomputer uses a watchdog timer as a means for detecting a program runaway, a system abnormality, or the like. This watchdog timer is a function to detect runaway or deadlock of the program, design the program with the instruction to clear the watchdog timer for each module of the program, and generate the watchdog timer interrupt By doing so, it is detected that the program or system is operating abnormally.

FIG. 5 is a block diagram of a signal output circuit including a watchdog timer for explaining such a conventional example.

As shown in FIG. 5, the signal output circuit inputs the clock signal φ and the watchdog timer clear signal CLR to the watchdog timer 6 and outputs the overflow signal when the watchdog timer circuit 6 overflows.
OVF is output to the external output terminal OUT1. The watchdog timer 6 is cleared by the programmable CLR signal, but is cleared by the clock signal φ until it counts up and overflows.
When the clear operation by CLR is not performed, the overflow signal OVF is output from the external output terminal OUT1.

[Problems to be Solved by the Invention]

The signal output circuit consisting of the conventional watchdog timer described above has a dedicated output terminal for the watchdog timer in order to notify the external system quickly and accurately to the external system without software. You need to be prepared. Therefore, there is a drawback in that the number of terminals cannot be increased because the terminals cannot be multiplexed with other functions.

An object of the present invention is to provide a signal output circuit that reduces the number of output terminals to the outside, and realizes miniaturization and economy.

[Means for Solving the Problems]

A semiconductor integrated circuit of the present invention includes an oscillation circuit and a CPU, in a signal output circuit of an integrated circuit device that operates based on the periodic signal from the oscillation circuit and the signal from the CPU, A counter composed of a watchdog timer that is cleared by a first input signal provided from a CPU; a flip-flop that is set by an overflow signal of the counter and that is reset by a second input signal provided by the CPU; A logic circuit that receives the periodic signal and the output of the flip-flop, and is configured to output or stop the periodic signal directly from the logic circuit to an external terminal by the output of the flip-flop. It

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a configuration diagram of a system abnormality control circuit of a microcomputer including a signal output circuit for explaining a first embodiment of the present invention.

As shown in FIG. 1, in the present embodiment, the abnormal operation output of the microcomputer 1 is detected by the comparator circuit 2 and the CPU 3 of the microcomputer 1 is reset by the reset signal 9. The microcomputer 1 includes a clock oscillation circuit 4 connected to a crystal oscillator, a signal output circuit 5 for inputting and outputting a clear (CLR) signal and a clock (φ) signal from the CPU 3, and further a signal output circuit 5 Has a watchdog timer 6 and a signal selection circuit 7. On the other hand, the comparator circuit 2 applies the signal output from the external output terminal OUT1 of the microcomputer 1 to one input via the integrating circuit composed of the resistor R ₁ and the capacitor C ₁ , and applies 1/4 VDD to the other input. It has a comparator 8 for making and comparing. Further, RES is the reset input terminal of the microcomputer 1, φ is the clock signal generated by the oscillation circuit 4, CLR is the watchdog timer clear signal output from the CPU 3, and OVF is the watchdog timer 6 overflows. The overflow signal, RESET, which is sometimes output, is an internal reset signal output from the CPU3.

FIG. 2 is a block diagram of the signal output circuit shown in FIG.

As shown in FIG. 2, the signal output circuit includes a watchdog timer 6 as a counter and a flip-flop (FF).
The signal selection circuit 7 is composed of 10 and an AND gate 11, and in particular, the signal selection circuit 7 is a circuit for outputting the clock signal φ or the watchdog timer interrupt request signal WDTO from the output terminal OUT1. Further, the set / reset type flip-flop circuit (FF) 10 uses the OVF signal and the RESET signal as set / reset signals, respectively, and outputs the watchdog timer interrupt request signal WDTO. If they match, the comparison signal is output to the external output terminal OUT1.

Next, the operation of the signal output circuit described in FIGS. 1 and 2 will be described.

FIG. 3 is a timing chart of the external output signals and the like in FIGS. 1 and 2.

As shown in FIG. 3, such a signal waveform shows the change of the signal from the normal operation state to the state in which the watchdog timer 6 detects the abnormality. In this example, the microcomputer 1 is operating normally during the period of a, and the abnormality is detected by the watchdog timer 6 at the timing of b.
The VDD level (1) is output to the F signal as a one-shot signal. The FF10 that has output the VDD level (1) state as the WDTO during the period of a is G as the WDTO when the OVF signal is output.
Outputs ND level (0). As a result, the output of the AND gate 11 changes from the clock signal φ to the GND level signal (0) and is output from OUT1. Therefore, if an abnormality is detected at point b, the GND level (0) is input to the comparator circuit 2 from the OUT1 terminal and the comparator output signal 9 is generated. Therefore, input the signal 9 to the RES terminal and reset the CPU3. Thus, the microcomputer 1 can be easily reset.

FIG. 4 is a configuration diagram of a signal output circuit similar to FIG. 2 for explaining the second embodiment of the present invention.

As shown in FIG. 4, in comparison with the first embodiment described above, this embodiment uses the positive phase output of FF10 and uses the clock signal φ.
And WDTO are the same except that OR gate 12 is used to take the logic. That is, the signal selection circuit 7 is a circuit for outputting the clock signal φ or the watchdog timer interrupt request signal WDTO from the output terminal OUT1. When the microcomputer is operating normally, the clock signal φ is selected and the output terminal OUT1 is selected.
In this example, when the watchdog timer 6 detects an abnormality, the OVF signal is output, and the WTDO signal is output, the VDD level (1) is output from the output terminal OUT1.

〔The invention's effect〕

As described above, in the signal output circuit of the integrated circuit device that operates based on the periodic signal, the present invention sets a counter that counts the periodic signal and is cleared by the first input signal, and an overflow signal of the counter. A flip-flop that is set by a second input signal and a logic circuit that receives the periodic signal and the output of the flip-flop, and outputs the output of the logic circuit to an external terminal to output a clock. And a watchdog timer interrupt request output can be output from one output terminal as a multiplexed signal,
There is an effect that the circuit can be made compact and economical.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a system abnormality control circuit diagram of a microcomputer including a signal output circuit for explaining a first embodiment of the present invention, and FIG. 2 is a signal output circuit shown in FIG. Configuration diagram of
FIG. 3 is a timing chart of the external output signals and the like in FIGS. 1 and 2, and FIG. 4 is a configuration diagram of a signal output circuit similar to FIG. 2 for explaining the second embodiment of the present invention. FIG. 5 is a block diagram of a signal output circuit including a watchdog timer for explaining an example of the related art. 1 ... Microcomputer, 2 ... Comparator circuit, 3 ... CPU, 4 ... Oscillation circuit, 5 ... Signal output circuit, 6 ... Watchdog timer, 7 ... Signal selection circuit, 8 ... Comparator, 9 …… Comparator output signal, 10 …… Flip-flop (FF) circuit, 11,12 …… Logic circuit, φ …… Clock signal, CLR …… Watchdog timer clear signal, OVF …… Overflow signal, R
ESET …… Internal reset signal, OUT1 …… External output terminal, WD
TO …… Watchdog timer interrupt request signal, a ……
Normal operation period, b ... Interrupt request timing.

Claims (1)

[Claims] 1. A signal output circuit of an integrated circuit device comprising an oscillation circuit and a CPU, which operates based on the periodic signal from said oscillation circuit and the signal from said CPU, counts said periodic signal and gives it from said CPU. A counter comprising a watchdog timer that is cleared by a first input signal, a flip-flop that is set by an overflow signal of the counter and that is reset by a second input signal provided by the CPU, and the periodic signal And a logic circuit having the output of the flip-flop as an input, and the output of the flip-flop outputs the periodic signal directly from the logic circuit to an external terminal,
A signal output circuit characterized by being stopped.