JPH0758465B2 - Pipeline processing type information processing device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bipline processing type information processing apparatus.

[Prior Art] In the conventional bi-line processing type information processing apparatus, the update of the software visible register is delayed as much as possible until the update of the instruction counter to update the instruction counter and the software visible (operable from software) register ( Although the non-retry period until the first update of the base register, general-purpose register, etc.) is shortened, the non-retry region that recognizes the stage on the pipeline where the failure occurs is not reduced.

[Problems to be solved by the invention]

In the conventional bi-line processing type information processing apparatus described above,
Since the processing stage is not recognized, there is a disadvantage in that it cannot be retried even if a failure occurs in any of the pipeline stages during the period in which the retry is not possible and the retry rate cannot be substantially improved.

[Means for Solving Problems] The present invention is a cause of a failure when an update instruction holding means that holds an identification number of an instruction that updates a software visible register and a failure occurs during pipeline processing. The fault instruction notifying means for notifying the instruction identification number and the instruction retry when the identification number notified by the fault instruction notifying means when the software visible register is updated and the identification number held by the update instruction holding means are the same It is characterized in that it has an instruction retry judging means for judging as impossible.

[Work]

By recognizing the failure occurrence stage on the pipeline and the instruction being processed in the stage, and enabling the instruction retry for the failure related to the subsequent instruction that is not related to the execution instruction even during the instruction retry impossible period, The retry rate is improved.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 3 is a diagram showing an example of pipeline processing. It is divided into 6 stages from stage IF to stage ST. Stage IF fetches an instruction, stage AC generates an operand address, stage AT translates a logical address into a real address, stage CA reads an operand, stage EX computes the read operand. Then, the stage ST is a process of storing the calculation result.

FIG. 4 is a diagram showing an instruction ID register provided corresponding to each pipeline stage shown in FIG. Each pipeline stage register AIC, IR, ~, IC corresponds to the instruction ID register ID0 ~ ID6, respectively. P1 represents a "+1" counting circuit for updating the IDs of the instruction ID register ID0 and ID6.

FIG. 1 is a block diagram of essential parts of an embodiment of a pipeline processing type information processing apparatus of the present invention.

When the software visible register (not shown) is updated before the instruction counter 2 is updated, the retry impossible display bit 3 is set by the arithmetic control unit 1 by a signal line 101.
The instruction counter update control unit 4 is activated by the instruction to update the instruction counter 2 (signal line 102) at the end of the instruction, and the instruction counter 2 is updated by the signal line 103 (by the counter circuit 5) together with a non-retry display bit. 3 is reset. However, when the fault processing control unit 6 issues a fault detection notification through the signal line 104, updating of the instruction counter 2 and resetting of the retry non-display bit 3 are suppressed, and the retry non-display bit 3 is used for retry determination.

Further, the fault occurrence notification is sent from the signal line 104 to the instruction ID registers ID0, ID1, ID2, ID3, ID4, ID5 and ID6 of each stage, and each ID register ID0 to ID6 holds the ID value of each stage. The ID selection circuit 7 is connected to the signal line 10 from the failure processing control unit 6.
The instruction ID of the failure occurrence stage is selected according to the failure occurrence stage information sent through 5. The ID comparison circuit 8
The instruction ID of the fault occurrence stage selected by the ID selection circuit 14 is compared with the value of the ID register ID6 holding the execution instruction ID, and when they match, the signal line 106 is turned on. The AND circuit 9 takes the logical product of the output of the retry impossible display bit 3 (the signal line 107) and the output of the ID comparison circuit 8 (the signal line 106), and the failure processing control unit 6 indicates whether the instruction retry is possible or not. Report by. That is, even if the retry impossible display bit 3 indicates that retry is not possible, as a result of the comparison in the ID comparison circuit 8, the signal line 106 is off, that is, when the failure occurrence stage is different from the execution instruction, it is the output of the AND circuit 9. The signal line 108 becomes "0", and the failure processing control unit 6 is notified that the instruction retry is possible.

FIG. 4 is a timing chart showing the flow of each pipeline stage in this embodiment. After the instruction address of instruction A is set in the pipeline stage register AIC in cycle I, cycle II and subsequent cycles VI
I indicates that the software visible register is updated. At this time, the instruction ID register is also set to the instruction ID register ID0 to the instruction ID register ID5 in cycle I, and then to the instruction ID register ID5 in cycle VI to cycle VII.
To instruction ID register ID6 + 1 to the content of instruction ID register ID5
It indicates that "1" is set by counting. This time chart shows the case where the instruction C updates four software visible registers. The ID of the instruction C also becomes the same value (2 here) for 4 cycles at each stage, and the instruction C is a 4 cycle instruction. It can be seen that it is. Retry disabled display The retry disabled display of bit 3 is performed at the time of the first software visible register update in the instruction C, that is, from the cycle IX. During this display, the instruction retry is disabled when a failure related to the execution of the instruction C occurs. However, processing in a pipeline stage not related to the instruction C (for example, a cycle
IR stage of IX or LAR stage of cycle X, etc.)
When a failure occurs in, the instruction retry possible can be considered as ignoring the retry impossible display bit shown in the figure.

〔The invention's effect〕

As described above, the present invention recognizes a failure occurrence stage on a pipeline and an instruction being processed in the stage, and performs an instruction retry for a failure related to a subsequent instruction unrelated to an execution instruction even during an instruction retry unavailable period. As a result, the retry rate is improved.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part of an embodiment of a pipeline processing type information processing apparatus of the present invention, FIG. 2 is a timing chart of the flow of each pipeline stage, and FIG. 3 is an example of a pipeline. 4 and 5 are diagrams showing the instruction ID register provided corresponding to each pipeline stage shown in FIG. 1 ... Arithmetic control unit, 2 ... Instruction counter, 3 ... Retry impossible display bit, 4 ... Instruction counter update control unit, 5 ... Counter circuit, 6 ... Fault processing control unit, 7 ... ID selection circuit, 8 ... ID comparison circuit, 9 ... AND gate, 101-108 ... Signal line, ID0-ID6 ... Instruction ID register.

Claims (1)

[Claims] 1. Update instruction holding means for holding an identification number of an instruction that updates a software visible register, and when a failure occurs during pipeline processing, the identification number of the instruction causing the failure is notified. When the fault instruction notifying means and the software visible register are updated, it is determined that the instruction retry is not possible when the identification number notified by the fault instruction notifying means and the identification number held by the update instruction holding means are the same. A pipeline processing type information processing apparatus having an instruction retry determination means.