JPH0769822B2 - Calculation register bypass check method - Google Patents

Description

The present invention relates to a bypass check system for arithmetic registers,
In particular, when an instruction to update the arithmetic register is followed by an instruction to access the same arithmetic register, processing is performed by directly supplying the arithmetic result data of the preceding instruction as the operand data of the succeeding instruction by bypassing the arithmetic register. The present invention relates to a bypass check method for an arithmetic register in an information processing device that is designed to increase the processing speed.

[Conventional technology]

Conventionally, as shown in FIG. 2, for example, an information processing apparatus of this type has an instruction control device 110, a main storage device 120, an arithmetic register 130, an address register 131, and a bypass control circuit.
It comprises 140, registers 141, 142 and 143, a selector 147, and an arithmetic processing unit 150.

The arithmetic processing unit 150 includes data registers 151, 152, 153 and
154, an addition / subtraction processing device 155, a multiplication / division processing device 156,
It is composed of data registers 157 and 158 and a selector 159.

The arithmetic register 130 is composed of a register group of a plurality of words having an address, and its read / write address is indicated by the address register 131.

In such a conventional information processing device, when the instruction is executed,
The instruction control device 110 decodes the instruction and sets the register address of the arithmetic register 130 as an operand in the address register 131. As a result, the target operand data is read from the arithmetic register 130 and the selector 14
It is supplied to the arithmetic processing unit 150 via 7. Further, the instruction control device 110 outputs the register address of the arithmetic register 130, which is an operand, to the register 141. The register address output to the register 141 is carried around in each stage of calculation via the registers 141, 142 and 143.

The arithmetic processing unit 150 stores the operand data supplied via the selector 147 in the data registers 151 and 153, and the operand data supplied from the main storage unit 120 in the data registers 152 and 154, respectively, and adds / subtracts the addition / subtraction instruction. The multiplication / division instruction is executed by the device 155 and the multiplication / division processing device 156 is executed. The operation result data is stored in the data register 1
Stored in 57 and 158 respectively. Based on the instruction from the instruction control unit 110, the selector 159 selects the operation result data of the data register 157 in the case of the addition / subtraction instruction, and selects the operation result data of the data register 158 in the case of the multiplication / division instruction. The selected calculation result data is sent from the calculation processing device 150 to the calculation register 130 and the main storage device 120 and stored at the target address.

On the other hand, the bypass control circuit 140, based on the register address held in the registers 141, 142, and 143 while being carried around in each stage of the operation, becomes the operand of the preceding instruction, the register address of the arithmetic register 130, and the succeeding instruction. The register address of the arithmetic register 130 which is an operand is compared, and when the same register address is present, the arithmetic result data of the preceding instruction is used as the operand data of the succeeding instruction, and the data registers 151 and 153 of the arithmetic processing unit 150. Selector to send directly to
In addition to controlling 147, the instruction control unit 110 sends a signal indicating that the instruction can be correctly executed.

In this way, the arithmetic register that the preceding instruction updates
If the register address of 130 and the register address of the operation register 130 that is the operand of the subsequent instruction match, the operand of the subsequent instruction without waiting for the operation result data to be written to the operation register 130 by the preceding instruction You can get the data.

[Problems to be Solved by the Invention]

In the conventional information processing apparatus described above, the bypass control circuit 14
When the selector 147 bypasses the invalid data as the operand data of the subsequent instruction due to the malfunction of 0, there is no means for checking the validity of the data, so that there is a disadvantage that the error of the bypass operation cannot be detected. .

In view of the above points, an object of the present invention is to add instruction IDs (identifiers) to data on registers and data paths, and to write instruction execution result data to an arithmetic register when the arithmetic register is bypassed. Provides an operation register bypass check method that enables error detection of bypass operation by comparing the instruction ID of the operation register with the instruction ID added to the instruction execution result data and carried around. To do.

[Means for Solving the Problems]

According to the bypass check method of the arithmetic register of the present invention, the arithmetic register composed of a register group of a plurality of words and the preceding first register.
The final operation result of the first operation instruction when the register address of the operation register for storing the operation result data of the operation instruction and the register address of the operation register accessed by the subsequent second operation instruction match. In the information processing apparatus having a data path for supplying the data determined as the operand data of the second operation instruction by bypassing the operation register, the instruction ID for each instruction is read when the data is read from the operation register. A command control device that generates and outputs, and a command ID output from this command control device and bypass information indicating bypass information indicating that the data is bypassed when the data is bypassed through the data path. With the rotation means for carrying around with the operation register and the operation register when writing data to the operation register. Command ID storage means for storing the instruction ID carried along with the last written data corresponding to the register of the register, and the write data by the bypass information carried along with the write data at the time of writing the data to the arithmetic register. Is indicated to be bypassed data, the last written instruction ID held corresponding to the register of the operation register and the instruction ID carried along with the write data are compared and different. And a comparison means for detecting an error in the bypass operation.

[Action]

In the bypass check method for the arithmetic register of the present invention, the instruction control device generates and outputs an instruction ID for each instruction when reading data from the arithmetic register, and the rotation means outputs the instruction ID and data path output from the instruction control device. When the data is bypassed via, the bypass information indicating that the data is bypassed is carried along with the bypassed data, and the instruction ID storage means is added to the register of the operation register at the end when writing the data to the operation register. It stores the instruction ID carried around with the written data, and the comparison means indicates that the write data is bypassed data by the bypass information carried along with the write data when writing the data to the arithmetic register. Write to the end of the operation register that is held in the case of To detect errors in the bypass operation when the instruction ID is different by comparing the instruction ID that Mochimawara with the write data.

〔Example〕

 Next, the present invention will be described in detail with reference to the drawings.

FIG. 1 is a circuit block diagram showing a configuration of an information processing apparatus to which a bypass check method for an arithmetic register according to an embodiment of the present invention is applied. This information processing apparatus includes an instruction control device 10, a main storage device 20, an arithmetic register 30, an address register 31, a bypass control circuit 40, and registers 41, 42 ,.
43, 44, 45 and 46, a selector 47, and an arithmetic processing unit 50
And a comparator circuit 60 and registers 61 and 62.

The instruction control device 10 decodes the instruction, sets the register address of the operand in the address register 31, and sets the register address in the register 41. The instruction control device 10 also generates an instruction ID and sets it in the register 44. As a method of generating the instruction ID, various methods such as placing a counter in the instruction control device 10 that counts up each time the instruction is executed and using the count value as the instruction ID can be considered.

The arithmetic register 30 is composed of a register group of a plurality of words having an address, and its read / write address is indicated by the register address set in the address register 31. Further, the arithmetic register 30 has an instruction ID storage unit 30a for storing the instruction ID carried along with the last written data corresponding to each register (address) when the data is written in the arithmetic register 30. There is.

The registers 41, 42 and 43 carry around the register address in the operation register 30 of the operand data held in each stage of the operation.

The registers 45, 46, and 62 have a flag (hereinafter referred to as a bypass flag) that holds information indicating that the data is bypassed data, and are carried around together with the instruction ID.

The bypass control circuit 40 has a register address of the arithmetic register 30 which is an operand of an instruction executed first based on the register addresses held in the registers 41, 42 and 43, and an operand of an instruction executed subsequently. When the same register address exists, the selector 47 is controlled so as to directly send the operation result of the preceding instruction to the data registers 51 and 53 of the arithmetic processing unit 50. In addition, the instruction control device 10 can execute the instruction correctly.
A signal indicating that is sent to 10.

The processor 50 includes data registers 51, 52, 53 and 54.
The adder / subtractor processing unit 55, the multiplication / division processing unit 56, the data registers 57 and 58, and the selector 59, operate in the same manner as the conventional arithmetic processing unit 150 shown in FIG.

The comparator circuit 60 corresponds to the register of the arithmetic register 30 indicated by the register address when the write data indicates that the write data is bypassed when the data is written to the arithmetic register 30. The last written instruction ID held and the instruction ID carried along with the write data are compared, and if different, an error signal is output to the signal line 63.

Next, the operation of the bypass check method of the arithmetic register of the present embodiment configured as described above will be described.

The instruction control device 10 decodes the instruction and outputs the register address of the arithmetic register 30 as an operand to the address register 31.
Set to. As a result, the target operand data is read from the arithmetic register 30 and supplied to the arithmetic processing unit 50 via the selector 47. Also, the command control device 10
Outputs the register address of the arithmetic register 30 which is an operand to the register 41. The register address output to the register 41 is carried around in each stage of calculation via the registers 41, 42 and 43. In addition, the command controller
10 creates an instruction ID for each instruction executed and
Output to. The instruction ID output to the register 44 is transferred to the registers 45, 46 and 6 via the selector 47 at each stage of the operation.
It is carried around to 2 in sequence.

On the other hand, the bypass control circuit 40 follows the register address of the operation register 30 which becomes the operand of the preceding instruction based on the register address held in the registers 41, 42 and 43 while being carried around in each stage of the operation. The register address of the arithmetic register 30 that is the operand of the instruction is compared, and if the same register address exists, the arithmetic result data of the preceding instruction is used as the operand data of the succeeding instruction, and the data register 51 of the arithmetic processing unit 50. The selector 47 is controlled so as to send it directly to the control unit 53 and 53, and at the same time, the instruction control unit 10 sends out a signal to that effect so that the instruction can be correctly executed.

The selector 47, which is controlled so as to directly send the operation result data of the preceding instruction to the data registers 51 and 53 of the operation processing device 50 as the operand data of the following instruction, the selector 47 supplied through the data path from the operation processing device 50. Select the operation result data of the instruction to
Also select the instruction ID that was carried around 44, 45 and 46. At the same time, the selector 47 sets the bypass flag of the register 45 to "1". The set bypass flag “1” can be carried around the registers 45, 46 and 62 at each stage of the operation together with the instruction ID.

In the comparison circuit 60, when the data is written to the arithmetic register 30, the bypass flag carried along with the instruction ID is “1”.
, The instruction ID of register 61 and the instruction ID of register 62
Compare with. In the register 61, when the data is written in the arithmetic register 30, the instruction ID held corresponding to the register having the register address at that time is stored in the arithmetic register.
It is read from the instruction ID storage unit 30a of 30 and held.

When the comparison circuit 60 detects that the instruction ID of the register 61 and the instruction ID of the register 62 are different, it is considered that the bypass operation by the bypass control circuit 40 is abnormal, and the signal line 63 is An error signal is output.

For example, when executing the instruction sequence shown in FIG.
When the ADD instruction is executed, "1" is output as the instruction ID from the instruction control device 10 and is carried around to the registers 44, 45, 46 and 62. The operation result data of the ADD instruction, which is the output of the operation processing device 50, is written together with the instruction ID “1” in the register address R1 of the operation register 30, and at the same time, is selected by the bypass control circuit 40 as the bypass data by the selector 47. It is supplied to the arithmetic processing unit 50 as operand data of the second MLT instruction. At this time, the selector 47 sets the bypass flag of the register 45 to “1” and sets the instruction ID of the ADD instruction to “1” instead of the instruction ID of the MLT instruction to “2”.

The instruction ID “1” and bypass flag “1” set in the register 45 are carried around with the registers 45, 46, and 62 as the MLT instruction is executed, and the final result data of the operation is written to the operation register 30 as write data. It is set in register 62 when written. On the other hand, at the same time, the address register 31 indicates the register address R1, and the instruction ID corresponding to the register indicated by the register address R1 is set in the register 61. In this case, the register of the arithmetic register 30 is executed by executing the ADD instruction. The instruction ID "1" is included in the register indicated by address R1.

The comparison circuit 60 compares the instruction ID “1” of the register 61 with the instruction ID “1” of the register 62, and when the bypass operation is normal, the instruction circuit has the same instruction ID and therefore does not output an error signal to the signal line 63. If there is an abnormality in the bypass operation and the operation result of an instruction other than the ADD instruction is bypassed, the instruction IDs will also be different, so the comparison circuit 60 outputs an error signal to the signal line 63.

〔The invention's effect〕

As described above, according to the present invention, when the instruction ID is added to the data on the arithmetic register and the data path and the arithmetic register is bypassed, the instruction of the arithmetic register is written when the execution result data of the instruction is written to the arithmetic register. ID
And the instruction that was carried around by being added to the execution result data of the instruction
By comparing with the ID, it is possible to effectively detect an error in the bypass operation.

[Brief description of drawings]

FIG. 1 is a circuit block diagram showing the configuration of an information processing apparatus to which the bypass check method for an arithmetic register of one embodiment of the present invention is applied, and FIG. 2 is a circuit block diagram showing an example of a conventional information processing apparatus. FIG. 3 is a diagram showing an example of an instruction sequence executed by the information processing apparatus shown in FIG. In the figure, 10 ... Instruction control device, 20 ... Main memory device, 30 ... Operation register, 30a ... Instruction ID storage unit, 31 ... Address register, 40 ... Bypass control circuit, 41-46 ... Register , 47
...... Selector, 50 …… Arithmetic processing unit, 51 to 54 …… Data register, 55 …… Addition and subtraction processing unit, 56 …… Multiplication and division processing unit, 57,58 …… Data register, 59 …… Selector, 60…
… Comparison circuit, 61,62 …… Register, 63 …… Signal line.

Claims (1)

[Claims] 1. An arithmetic register comprising a register group of a plurality of words, a register address of the arithmetic register in which a preceding first arithmetic instruction stores operation result data, and a subsequent second.
When the register address of the arithmetic register accessed by the arithmetic operation instruction No. 2 matches, the data determined as the final arithmetic result of the first arithmetic instruction is used as the operand data of the second arithmetic instruction to bypass the arithmetic register. In an information processing device having a data path for supplying, an instruction control device that generates and outputs an instruction ID for each instruction when reading data from the arithmetic register, and an instruction ID output from this instruction control device, When the data is bypassed via the data path, a carry-out means for carrying around bypass information indicating that the data is bypassed data together with the bypassed data, and a register of the operation register when writing the data to the operation register. The instruction ID carried around with the last written data for the correspondence is stored. Command ID storage means and a register corresponding to the arithmetic register when it is indicated that the write data is bypassed data by the bypass information carried along with the write data at the time of writing the data to the arithmetic register. Comparing the last written instruction ID held and the instruction ID carried around with the write data, and comparing means for detecting an error in the bypass operation when there is a difference. Register bypass check method.