JPH0758713B2 - Method for manufacturing bipolar semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device suitable for high integration density and capable of high speed operation.

(Prior Art) In order to improve the operating speed of a bipolar semiconductor integrated circuit device, it is effective to reduce the base resistance of a transistor as a constituent element and also reduce the parasitic capacitance, especially the base-collector junction capacitance. is there.

In order to reduce the base resistance, it is necessary to reduce the width of the emitter to reduce the resistance of the active base portion and to bring the high-concentration or low-resistance inactive base as close to the emitter as possible. In addition, in order to reduce the base-collector junction capacitance, it is required to reduce the area of the active base / inactive base as much as possible to reduce the junction area with the epitaxial layer serving as the collector.

Therefore, a manufacturing method using various self-alignment techniques that enables fine processing exceeding the accuracy of photo-etching has been proposed.

As an example of this type of manufacturing method, for example, Proc. Of 12th Conf. On Solid State Device.
The manufacturing method disclosed in Aug. 1980PP155-159) will be described below as a conventional technique.

2A to 2H are process cross-sectional views showing a method of manufacturing a conventional bipolar semiconductor integrated circuit device according to the above technique.

First, as shown in FIG. 2A, a P ⁻ type silicon substrate 1
Then, an N ⁺ type buried diffusion layer 2, an N ⁻ type epitaxial layer 3, a P ⁺ type element isolation region 4 and a collector electrode extracting N ⁺ type diffusion layer 5 are formed, and then a thermal oxide film 6 and a CVD nitride film 7 are formed. Then, a CVD oxide film 8, boron-doped polycrystalline silicon 9, and a CVD nitride film 10 are sequentially formed, and a part of the nitride film 10 is removed by photo-etching.

Then, using the nitride film 10 as a mask, an unnecessary portion of the boron-doped polycrystalline silicon 9 is thermally oxidized to be converted into an oxide film 11.
By photo-etching again, the nitride film 10 is left only in the base electrode window of the transistor and the electrode window portion of the resistor to obtain the structure of FIG. 2B.

Next, as shown in FIG. 2C, the portions of the boron-doped polycrystalline silicon 9 forming the emitter and collector are removed by photo-etching, and the CVD oxide film 8 is side-etched.

When aluminum 12 is vapor-deposited from the direction perpendicular to the substrate, the aluminum 12 is cut off by the overhanging boron-doped polycrystalline silicon 9 formed by the side etching of the CVD oxide film 8, and the structure shown in FIG. 2D is obtained.

Next, as shown in FIG. 2E, the nitride film 7 is selectively removed using the aluminum as a mask, and after removing the aluminum, the active base 13 is formed by boron ion implantation and the oxide film 6 is etched. , Boron-doped polycrystalline silicon 9'is again deposited on the entire surface.

Then, the boron-doped polycrystalline silicon 9'is etched by using ion milling to leave the boron-doped polycrystalline silicon 9'only under the overhang. Second
In FIG. F, the remaining boron-doped polycrystalline silicon 9 ′ and the existing boron-doped polycrystalline silicon 9 are combined and shown as boron-doped polycrystalline silicon 9.

Next, the boron-doped polycrystalline silicon 9 is thermally oxidized to form a relatively thick oxide film 14. Emitter. collector. Since the electrode extraction portion of the base is covered with the nitride films 7 and 10, it is not oxidized. In addition, boron is diffused from the boron-doped polycrystalline silicon 9 by this heat treatment, and the heat treatment shown in FIG.
To form an inert base 14.

Next, the nitride films 7 and 10 and the thin oxide film 6 are removed by etching,
As shown in FIG. 2H, an emitter 16 is formed by diffusion from arsenic-doped polycrystalline silicon 15, and finally a metal electrode wiring 17 is formed.

According to the above manufacturing method, the distance between the emitter and the inactive base can be made close to the thickness of the oxide film 14,
Since the area of the inactive base region is also small, the base resistance can be reduced as well as the base-collector junction capacitance.

(Problems to be Solved by the Invention) However, the manufacturing method described above is different from FIGS. 2A to 2G.
It has been pointed out that there is a drawback that the process leading to is extremely complicated and there is a problem in reproducibility. Further, in the above manufacturing method, the reduction of the emitter width with respect to the opening due to photo-etching is not so remarkable, so that it is difficult to reduce the active base component of the base resistance, and the reduction of the resistance of the polycrystalline silicon layer for drawing out the base electrode is achieved. However, there is a limitation that the base resistance cannot be reduced so much.

In view of the above problems, the present invention forms a structure essentially equivalent to that shown in FIG. 2G with good reproducibility in a simple process, reduces the emitter width, and lowers the resistance of the extraction electrode to reduce the base resistance. It is an object of the present invention to provide a manufacturing method capable of being significantly reduced.

(Means for Solving the Problem) The present invention is a method for manufacturing a bipolar semiconductor integrated circuit device, in which a thin thermal oxide film and a nitride film are laminated on a substrate surface, and then a resist pattern narrower in a lower portion than in an upper portion is formed,
After selectively removing the above-mentioned two-layer film using the resist as a mask, silicon and refractory metal or refractory metal silicide are vapor-deposited, and a part of the resist is lifted off by the resist to form a so-called polycide structure base. The extraction electrode layer is formed and will be described below in detail with reference to the drawings.

(Operation) According to the present invention, since the number of manufacturing steps can be reduced, the manufacturing cost of the bipolar semiconductor integrated circuit device can be significantly reduced.

(Embodiment) FIGS. 1A to 1F are process sectional views showing an embodiment of the present invention.

The manufacturing method of the present invention is particularly suitable for a structure in which elements are separated by a thick oxide film, and FIG. 1 also uses the oxide film separation method.

First, as shown in FIG. 1A, an N ⁺ type buried diffusion layer 102, an N ⁻ type epitaxial layer 103 and an isolation oxide film 10 are formed on a P ⁻ type silicon substrate 101.
4, N ⁺ type diffusion region 105 for extracting the collector electrode is formed.
The surface is oxidized to form a thin oxide film 106 having a thickness of 100 to 500Å, and a nitride film 107 having a thickness of 500 to 2000Å is laminated by a CVD method, and then a resist 108 having a narrower width than the upper portion is formed. Conventionally, a resist layer having such a cross-sectional shape can be easily formed by using a resist called LMR (Low Molecular weight Resist) described in Kawazu et al., IEICE Technical Report SSD83-178 (1984). be able to. According to the same document, LMR is a negative resist for deep ultraviolet light, which can resolve lines and spaces to 0.5 μm, and the amount of overhang can be freely controlled by changing the development time. There is.

Next, as shown in FIG. 1B, the nitride film 107 and the oxide film 106 are selectively removed using the resist 108 as a mask.

After that, silicon 109 of about 2000 to 5000 Å and refractory metal (for example, molybdenum) or refractory metal silicide (for example, molybdenum silicide) 116 of 100 to 1000 Å are deposited on the entire surface by a method such as sputter deposition. At this time,
By selecting appropriate conditions, the silicon 109 wraps under the overhang of the resist 108, and the cross-sectional shape as shown in FIG. 1C can be obtained. At this point, the silicon 109 is generally in an amorphous state.
Further, boron is ion-implanted on the entire surface at about 10 ¹⁵ to 10 ¹⁶ cm ^-2 .

Subsequently, when 108 and the high melting point metal or the high melting point metal silicide 116 deposited on the resist 108 are removed by lift-off, the shape shown in FIG. 1D is obtained. If 116 is a refractory metal, then heat treatment at several hundreds of degrees C
Reacts with 109 to form a silicide.

Next, unnecessary portions of silicon 109 and refractory metal silicide 1
16 is selectively removed by photo-etching and thermal oxidation is performed to form an oxide film 110 of 1000 to 3000 Å on the surface. By this heat treatment, the amorphous silicon 109 is polycrystallized, the silicide layer 116 is combined to form a so-called polycide structure, and boron is diffused to form the inactive base 111 as shown in FIG. 1E. Further, boron of 10 ¹³ to 10 ¹⁴ cm ^-2 is ion-implanted through the nitride film 107 and the oxide film 106, and annealed in an inert atmosphere to perform active base 11
Form 2.

Alternatively, after selectively removing unnecessary portions of the silicon 109 and the silicide layer 116, the surface is thinly oxidized, boron is ion-implanted to form the active base 112, and thermal oxidation is performed again to increase the oxide film thickness. , The structure of FIG. 1E can be obtained.

The structure of FIG. 1E is essentially equivalent to the structure of FIG. 2G.

Therefore, thereafter, similarly to the conventional example, the nitride film 107 and the oxide film 1 are formed.
06 is removed, and an emitter 114 is formed by diffusion from arsenic-doped polycrystalline silicon 113, and then a contact hole in the base is opened and a metal electrode wiring 115 is formed to obtain the structure of FIG. 1F.

(Effects of the Invention) As described above in detail, in the manufacturing method of the present invention, the vapor-deposited silicon layer and the refractory metal or its silicide are processed by lift-off using the resist layer having a narrower width in the lower portion than in the upper portion. 1A to 1E of the present invention, which forms a polycide layer for drawing out the base electrode, and corresponds to the steps of the conventional manufacturing method shown in FIGS. 2A to 2G.
This has the effect of significantly simplifying the process.

That is, the conventional method required six film forming steps by CVD and vapor deposition, whereas the method of the present invention can obtain an essentially equivalent structure in only three steps.

In addition, in the conventional method, the width of the emitter depends on the resolution of the photo-etching process and there is a problem in reproducibility.
According to the method of the present invention using a resist referred to as, the overhang amount on the resist layer can be freely controlled by the development time. It can be formed well. Furthermore, by making the base electrode lead-out layer polycide, the layer resistance of this layer, which was conventionally limited to about 100 Ω / □, can be reduced to several Ω / □. Due to the above two points, the resistances of the active base portion and the extraction electrode portion are both significantly reduced, and there is an advantage that a transistor having an extremely low base resistance can be obtained.

As described above, according to the manufacturing method of the present invention, it is possible to form a semiconductor integrated circuit device having an operation speed improved as compared with the conventional one in a simple process, and is widely applied as a high speed and highly integrated bipolar VLSI. There are fields.

[Brief description of drawings]

1A to 1F are process sectional views showing a method for manufacturing a bipolar semiconductor integrated circuit device according to the present invention, and FIGS. 2A to 2H are process sectional views showing a method for manufacturing a conventional bipolar semiconductor integrated circuit device. is there. 101 ... P ^- type silicon substrate, 102 ... N ⁺ type buried diffusion layer, 103 ... N
^- -type epitaxial layer, 104 ... separation oxide film, 105 ... N ⁺ -type diffusion region, 106 ... oxide film, 107 ... nitride film, 108 ... resist, 1
09 ... Amorphous silicon or polycrystalline silicon, 110 ...
Oxide film, 111 ... Inert base, 112 ... Active base, 113 ...
Polycrystalline silicon, 114 ... Emitter, 115 ... Metal electrode wiring,
116 ... Refractory metal or refractory metal silicide.

Claims (1)

[Claims] 1. A two-layer film composed of a thin oxide film and a nitride film is formed on a semiconductor substrate having a first conductivity type island region on one main surface, and a two-layer film formed on the two-layer film is selected from above. A first step of forming a resist layer having a lower cross-sectional shape with a narrow width, a second step of selectively removing the two-layer film using the resist layer as a mask, and the entire main surface of the semiconductor substrate A third step of depositing a semiconductor material on the resist, a fourth step of depositing a refractory metal or a refractory metal semiconductor compound, and removing the resist layer by removing the resist layer (the semiconductor A method for manufacturing a bipolar semiconductor integrated circuit device, comprising: a material; and a fifth step of simultaneously removing a film made of a refractory metal or a refractory metal semiconductor compound).