JPH0785475B2 - Method for manufacturing bipolar semiconductor integrated circuit device - Google Patents

Description

The present invention relates to a method for manufacturing a bipolar semiconductor integrated circuit device suitable for high integration and high density and capable of high speed operation.

(Prior Art) In order to improve the operating speed of a bipolar semiconductor integrated circuit device, it is effective to reduce the base resistance of a transistor as a constituent element and also reduce the parasitic capacitance, particularly the junction capacitance between the base and collector. Is. Therefore, (1) In order to reduce the base resistance, it is necessary to reduce the width of the emitter to reduce the resistance of the active base portion, and to bring an inactive base of high concentration, that is, low resistance, as close to the emitter as possible. Is.

(2) To reduce the base-collector junction capacitance, reduce the area of the active base / inactive base as much as possible,
It is required to reduce the junction area with the epitaxial layer serving as the collector.

Therefore, a manufacturing method using various self-alignment techniques that enables fine processing exceeding the accuracy of photo-etching has been proposed.

As a conventional manufacturing method of this kind, `` Proceedings of the 12th Conference on Solid Stat
e Devices, Tokyo, 1980; Japanese Journal on Applied P
hysics, Volume 20 (1981) Supplement 20-1, pp155-15
9 ”.

The configuration will be described below with reference to the drawings.

FIG. 2 is a manufacturing process diagram of such a conventional bipolar semiconductor integrated circuit device.

First, as shown in FIG. 2 (a), P ^- -type silicon substrate 1 to the N ⁺ -type buried diffusion layer 2, N ^- -type epitaxial layer 3, P ⁺
After forming the type element isolation region 4 and the N ⁺ type diffusion layer 5 for extracting the collector electrode, a thermal oxidation (SiO ₂ ) film 6, a CVD nitride (Si ₃ N ₄ ) film 7, a CVD oxidation (SiO ₂ ) film 8, A boron-doped polycrystalline silicon 9 and a CVD nitride (Si ₃ N ₄ ) film 10 are sequentially formed, and a part of the CVD nitride film 10 is removed by photo-etching.

Then, as shown in FIG. 2 (b), the CVD nitride film 10 is formed.
The unnecessary portion of the polycrystalline silicon 9 is thermally oxidized by using the mask as a mask and converted into an oxide (SiO ₂ ) film 11, and CV is again applied only to the base electrode window of the transistor and the electrode window portion of the resistor by photoetching.
D nitride film 10 is left.

Next, as shown in FIG. 2C, the portions of the polycrystalline silicon 9 forming the emitter and collector are removed by photo-etching, and the CVD oxide film 8 is side-etched.

Next, as shown in FIG. 2D, when aluminum 12 is vapor-deposited from the direction perpendicular to the substrate, the aluminum 12 is removed by the overhang-like polycrystalline silicon 9 formed by the side etching of the CVD oxide film 8. Cut off.

Next, as shown in FIG. 2 (e), the nitride film 7 is selectively removed using the aluminum 12 as a mask, and after the aluminum 12 is removed, an active base 13 is formed by boron ion implantation, and an oxide film 6 is formed. Then, boron-doped polycrystalline silicon 9'is deposited again on the entire surface.

Next, as shown in FIG. 2 (f), the polycrystalline silicon 9'is etched by using ion milling to leave the polycrystalline silicon 9'only under the overhang.

In FIG. 2 (f), the remaining polycrystalline silicon 9'and the existing polycrystalline silicon 9 are shown together as polycrystalline silicon 9 ".

Next, as shown in FIG. 2 (g), the polycrystalline silicon 9 ″ is thermally oxidized to form a relatively thick acid compound film 14. In this case, the electrode extraction portions of the emitter, collector and base are nitrided. It is not oxidized because it is covered with the films 7 and 10. This heat treatment also diffuses boron from the polycrystalline silicon 9 ″ to form the inactive base 15.

Next, as shown in FIG. 2 (h), the nitride films 7 and 10 and the thin oxide film 6 are removed by etching, the emitter 17 is formed by diffusion from the arsenic-doped polycrystalline silicon 16, and finally the electrode wiring is formed. Forming 18.

According to the manufacturing method described above, the emitter 17 and the inert base are
Since the distance from 15 can be made close to the thickness of the oxide film 14 and the area of the inactive base region is small, the base capacitance can be reduced as well as the junction capacitance between the base and the collector.

(Problems to be Solved by the Invention) However, according to the above-described conventional manufacturing method, there is a problem that the steps from FIG. 2 (a) to FIG. 2 (g) are extremely complicated, Moreover, there is also a problem in reproducibility in the manufacturing process.

Further, in the above-mentioned manufacturing method, there is a problem that it is difficult to reduce the active base component of the base resistance because the reduction of the emitter width due to the photo-etching is not so remarkable.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a bipolar semiconductor integrated circuit, which eliminates the above-mentioned problems, is simple to manufacture, has high reproducibility, and can significantly reduce the emitter width.

(Means for Solving Problems) In order to solve the above problems, the present invention provides a method for manufacturing a bipolar semiconductor integrated circuit, in which a thin thermal oxide film and a nitride film are stacked on a substrate surface and then an upper portion is formed. After forming a resist pattern having a width narrower than the lower part, and selectively removing the thermal oxide film and the nitride film using the resist as a mask,
By depositing silicon and partially lifting off with the resist, a polycrystalline silicon layer for a base electrode is formed.

(Function) According to the present invention, the thermal oxide film and the nitride film are selectively removed using a resist layer having a lower width than the upper part, and then silicon is vapor-deposited to lift off a part of the silicon by the resistor. Thus, the polycrystalline silicon layer for the base electrode is formed, so that the manufacturing process can be simplified and the emitter with a narrow width can be formed with good reproducibility.

(Example) Hereinafter, the Example of this invention is described in detail, referring drawings.

FIG. 1 is a manufacturing process drawing of a bipolar semiconductor integrated circuit device showing an embodiment of the present invention.

First, as shown in FIG. 1A, an N ⁺ type buried diffusion layer 102 and an N ⁻ type epitaxial layer 10 are formed on a P ⁻ type silicon substrate 101.
3. An isolation oxide film 104 is formed, and an N ⁺ type diffusion layer 105 for extracting a collector electrode is formed. And oxidize the surface, 100-500
A thin Å oxide film 106 is formed, and further 500 by CVD method.
After a silicon nitride film 107 having a thickness of up to 2000 Å is laminated, a resist layer (resist pattern) 108 having a lower width than the upper part is formed.

The resist layer with such a cross-sectional shape is LMR (Low
It can be easily formed by using a resist called a molecular weight resist. This LM
R is "Ryuji Kawazu, 8 others, IEICE Technical Report, SSD83-178"
(1984), pp. 1-8 ", a line-and-space of 0.5 μm can be resolved with a negative resist for deep ultraviolet light, and the amount of overhang can be freely controlled by changing the development time. it can.

Next, as shown in FIG. 1B, the resist layer 108.
Using the as a mask, the nitride film 107 and the oxide film 106 are selectively removed.

Next, as shown in FIG. 1 (c), silicon is deposited on the entire surface by a method such as sputter deposition to form a silicon layer.
Form 109. At this time, the silicon layer 109 wraps under the overhang of the resist layer (resist pattern) 108 by selecting appropriate conditions.

At this point, the silicon layer 109 is generally in an amorphous state, and a film thickness of about 2000 to 5000Å is suitable.
Further, boron (boron B) is ion-implanted on the entire surface at about 10 ¹⁵ to 10 ¹⁶ cm ^-2 .

Subsequently, as shown in FIG. 1 (d), the register layer
The silicon layer deposited on 108 is removed by lift-off.

Next, as shown in FIG. 1 (e), the unnecessary portion of the silicon layer 109 is selectively removed by photo-etching, and thermal oxidation is performed to form an oxide film 110 of 1000 to 3000 Å on the surface.
By this heat treatment, the amorphous silicon layer 109 is formed.
Becomes polycrystalline, and at the same time boron is diffused and inert base 11
1 is formed.

Further, 10 ¹³ to 10 ¹⁴ cm ⁻² of boron is ion-implanted through the nitride film 107 and the oxide film 106 and annealed in an inert atmosphere to form an active base layer 112. Alternatively, after selectively removing the unnecessary portion of the silicon layer 109, after thermally oxidizing the surface thinly,
The structure shown in FIG. 1E can also be obtained by ion-implanting boron to form the active base 112 and performing thermal oxidation again to increase the oxide film thickness on the surface. The structure of FIG. 1 (e) is essentially equivalent to the structure of the conventional FIG. 2 (g) described above. Therefore, thereafter, as shown in FIG. 1 (f), the nitride film 10 is formed in the same manner as in the conventional technique.
7 and oxide film 106 are removed, and arsenic-doped polycrystalline silicon 11
After forming the emitter 114 by diffusion from 3, the base and resistor contact holes are opened, and the metal electrode wiring 115 is formed to manufacture the bipolar semiconductor integrated circuit device according to the present invention.

The present invention is not limited to the above embodiment,
Various modifications are possible based on the spirit of the present invention, and these are not excluded from the scope of the present invention.

(Effect of the Invention) As described in detail above, according to the present invention, a two-layer film including a thin oxide film and a nitride film is formed on a semiconductor substrate having an island region of the first conductivity type on one main surface, A first step of forming a resist layer having a cross-sectional shape in which a width of a lower portion is narrower than that of an upper portion in a selected region on the two-layer film, and the two-layer film is selectively removed using the resist layer as a mask. A second step, a third step of depositing a semiconductor material on the entire one main surface of the semiconductor substrate, and a step of simultaneously removing the semiconductor material deposited on the resist layer by removing the resist layer. Since the fourth step is performed, (1) the manufacturing process can be significantly simplified. That is, according to the conventional manufacturing method, the film forming step of 6 times by CVD and vapor deposition was required, but according to the present invention, the bipolar semiconductor which is basically equivalent to the conventional one with only 2 steps. An integrated circuit device can be obtained.

(2) A narrow emitter can be formed with good reproducibility, and the base resistance of the active base can be significantly reduced. That is, according to the conventional manufacturing method, the emitter width depends on the resolution of the photo-etching process, and there is also a problem in reproducibility, whereas according to the present invention, a resist called LMR described above is used, Since the overhang layer above the layer can be freely controlled by the development time, a narrow emitter can be formed with good reproducibility, and the base resistance of the active base portion can be remarkably reduced.

As described above, the present invention makes it possible to form a bipolar semiconductor integrated circuit device having an operation speed improved as compared with the conventional one in a simple process, and is widely used as a bipolar VLSI having high speed, high integration, and high density. It has application fields.

[Brief description of drawings]

FIG. 1 is a manufacturing process diagram of a bipolar semiconductor integrated circuit device according to the present invention, and FIG. 2 is a manufacturing process diagram of a conventional bipolar semiconductor integrated circuit device. 101 …… P ^- type silicon substrate, 102 …… N ⁺ type buried diffusion layer, 10
3 …… N ^- type epitaxial layer, 104 …… Separation oxide film, 105
...... Collector electrode extraction N ⁺ type diffusion layer, 106 …… Thin oxide film, 107 …… Silicon nitride film, 108 …… Resist layer, 109
...... Silicon layer, 110 ・ ・ ・ Oxide film, 111 …… Inactive base, 112 …… Active base, 113 …… Arsenic-doped polycrystalline silicon layer, 114 …… Emitter, 115 …… Metal electrode wiring.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 29/73

Claims (7)

[Claims] 1. A two-layer film composed of a thin oxide film and a nitride film is formed on a semiconductor substrate having a first conductivity type island region on one main surface,
A first step of forming a resist layer having a cross-sectional shape in which a width of a lower portion is narrower than that of an upper portion in a selected region on the two-layer film, and the two-layer film is selectively removed using the resist layer as a mask. A second step, a third step of depositing a semiconductor material on the entire one main surface of the semiconductor substrate, and a step of simultaneously removing the semiconductor material deposited on the resist layer by removing the resist layer. And a fourth step of manufacturing the bipolar semiconductor integrated circuit device. 2. The method for manufacturing a bipolar semiconductor integrated circuit device according to claim 1, further comprising the step of introducing a second conductivity type impurity into the semiconductor material in the third step. 3. A step of thermally oxidizing the surface of the semiconductor material in the fourth step and forming a first region of the second conductivity type in a part of the island area by diffusion from the semiconductor material; A step of introducing a second conductivity type impurity into the surface of the island region immediately below the layer film to form a second region of the second conductivity type extending to the first region. 2. A method of manufacturing a bipolar semiconductor integrated circuit device according to item 2. 4. A step of introducing a second conductivity type impurity into the surface of the island region immediately below the two-layer film in the fourth step to form a second region of the second conductivity type; Forming a first conductivity type first region extending to the second region in a part of the island region by thermal oxidation and diffusion from the semiconductor material. 2. A method of manufacturing a bipolar semiconductor integrated circuit device according to item 2. 5. A step of removing the two-layer film to expose the surface of the second region, and forming a semiconductor material layer containing a first conductivity type impurity on a selected surface including on the second region, 5. A bipolar semiconductor according to claim 3 or 4, further comprising the step of forming a third region of the first conductivity type in the second region by diffusion from the semiconductor material layer. Manufacturing method of integrated circuit device. 6. The semiconductor substrate is a silicon substrate, the semiconductor material is silicon, the first conductivity type is N type, and the second conductivity type is P.
6. The method for manufacturing a bipolar semiconductor integrated circuit device according to claim 2, wherein the bipolar semiconductor integrated circuit device is a die. 7. The method for manufacturing a bipolar semiconductor integrated circuit device according to claim 6, wherein the first conductivity type impurity is arsenic and the second conductivity type impurity is boron.