JPH0758909B2 - Analog digital conversion circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention will be described in the following order.

A Industrial Field B Outline of the Invention C Prior Art (Fig. 8) D Problems to be Solved by the Invention (Figs. 9 and 10) E Means for Solving Problems (Fig. 1) And Fig. 3) F action (Figs. 1 and 3) G embodiment (G1) First embodiment (Figs. 1 to 5) (G2) Second embodiment (Figs. 6 and 6) FIG. 7) (G3) Other embodiment H Effect of the invention A Industrial field of use The present invention relates to an analog digital conversion circuit, and more particularly to an analog digital conversion circuit for converting the upper bit part and the lower bit part of output digital data separately. It is suitable to be applied to.

B. SUMMARY OF THE INVENTION The present invention provides an analog digital conversion circuit for converting the upper bit part and the lower bit part of output digital data separately, at a comparison time for obtaining a first comparison result corresponding to the upper bit part of output digital data. for,
The second corresponding to the lower bit part of the output digital data
By increasing the comparison time for obtaining the comparison result of, the conversion accuracy of the output digital data can be improved as a whole.

C Conventional Technology Conventionally, as a high-speed analog digital conversion circuit for converting an analog signal such as a video signal into digital data, a so-called two-step direct conversion for converting an analog signal by dividing it into an upper bit portion and a lower bit portion of the digital data is performed. A so-called parallel type has been proposed (Japanese Patent Laid-Open No. 58-9426).

That is, as shown in FIG. 8, in the case of the analog digital conversion circuit 1 for converting the input video signal VD _IN into the 8-bit digital data DG _OUT , the input video signal VD _IN is switched to the switch circuit 2A, the holding capacitor 2B and the buffer. The hold voltage V _HD received by the sample and hold circuit 2 composed of the circuit 2C and sampled and held by the holding capacitor 2B is used as the comparators CC _{1 to} CC of the upper bit comparison circuit unit 3 and the lower bit comparison circuit unit 4, respectively. ₁₅ , CF _{1 to} CF ₁₅ are applied to the inverting input terminals.

Here, the comparators CC _{1 to} C that compose the upper bit comparison circuit section 3
The non-inverting input terminal of the C _15, upper bits comparison reference voltage VC _REF1 ~VC _REF15 obtained from the reference voltage generating circuit 5 is input.

The reference voltage generating circuit 5 includes 256 resistors R1 (n) and R2 having the same resistance value between the first and second voltages V _RT and V _BT according to the voltage level of the input video signal VD _IN.
(N), ..., R15 (n), R16 (n) (n = 1 to 16) are connected in series, and every 16 resistors R1 (n) and R2 (n),
R2 (n) and R3 (n), ..., R14 (n) and R15
(N), R15 (n), and R16 (n), the voltage obtained at the midpoint of connection is the upper bit comparison reference voltage VC in order from the lower voltage side.
It is designed to be sent as _{REF1 to} VC _REF15 .

As a result, the comparators CC _{1 to} CC of the high-order bit comparison circuit unit 3
_The comparison results RC _{1 to} RC ₁₅ obtained from ₁₅ are input to the upper bit latch / encoder circuit 6, and thus the comparison result RC ₁
~ Digital data DG _H corresponding to RC ₁₅ is sent as upper 4 bits of output digital data DG _OUT .

In this way, the upper bit comparison circuit 3 hold voltage
V _HD causes the first and second voltages V _RT and V _BT to
By detecting which of the divided voltage values the divided voltage value corresponds to, the hold voltage V _HD is converted into the digital data DG _H in the coarse division mode to obtain the upper 4 bits of the output digital data DG _OUT .

Also, in the reference voltage generation circuit 5, 256 resistors R1
(N), R2 (n), ..., R15 (n), R16 (n) (n =
1 to 16) are connected in series so as to form a matrix, and every 16 resistors R1 (n) and R2 forming the column are connected.
Resistances Rm (1) and Rm (2), Rm (2) and Rm forming a row with respect to (n), ..., R15 (n), R16 (n)
(3), ..., Rm (14) and Rm (15), Rm (15) and Rm
(16) The connection midpoints between (m = 1 to 16) are, for example,
Switch circuit with MOS (metal oxide semiconductor) structure
, Sm (1), Sm (2), ..., Sm (14), Sm (15) are connected to the non-inverting input terminals of the comparators CF _{15 to} CF ₁ of the lower bit comparison circuit unit 4. .

The switch circuit Sm (1) of the reference voltage generating circuit 5,
Sm (2), ......, Sm (14), Sm (15) , first logic comparison result RC ₁ to RC ₁₅ for upper bits comparator circuit part 3 "L"
1 corresponding to the level comparator CC _i (i = 1 to 15)
Row switch circuits Si (1), Si (2), ..., Si (1
4), Si (15) is on-controlled, and resistors R16 (1) to R1
Switch circuits S16 (1) to S16 (15) corresponding to 6 (16)
1 column is the comparison result RC _{1 to} RC of the upper bit comparison circuit unit 3.
_When all ₁₅ are logic "H" levels, they are turned on.

As a result, the comparators CF _{15 to} CF of the lower bit comparison circuit unit 4
Lower bit comparison reference voltage V input to the non-inverting input terminal of ₁
F _{REF15 to} VF _REF1 are the upper bit comparison reference voltage VC in which the hold voltage V _HD detected by the upper bit comparison circuit section 3 exists.
The voltage value between _{REF1 to} VC _REF15 is further divided into 16 by a resistor to obtain it.

Thus, the comparison results RF _{1 to} RF of the lower bit comparison circuit unit 4
₁₅ is input to the lower bit latch / encoder circuit 7,
The digital data DG _L corresponding to the comparison results RF _{1 to} RF ₁₅ is transmitted as the lower 4 bits of the output digital data DG _OUT .

In this manner, the input video signal VD _IN having a high frequency of, for example, about 10 to 20 [MHz] can be accurately converted into the 8-bit digital data DG _OUT by using the minimum necessary comparator as a whole. It is done like this.

D. Problems to be Solved by the Invention By the way, the two-step serial / parallel analog digital conversion circuit 1 having such a configuration actually has two clocks of a predetermined cycle.
The input video signal VD _IN is subjected to analog digital conversion in every cycle and 8-bit digital data DG _OUT is sent out.

That is, in the analog digital conversion circuit 1,
Sampling pulse P _SM (FIG. 9 (B)) rising during the rising period (time points t _{0 to} t ₁ , t _{4 to} t ₅ ) of the clock CK1 (FIG. 9 (A)) every two cycles, and its sampling pulse After P _SM , sequentially delayed by 1/2 clock cycle at time t ₁
~t _2, t ₅ ~t ₆ upper bits comparison pulse P _CC rising period of (Figure 9 (C)), the time t ₂ ~t _3, t ₆ during the period ~t ₇ rises switch changeover pulse P _ST (Fig. 9 (D))
And a lower bit comparison pulse P _FC (FIG. 9 (E)) which rises during the period of t _{3 to} t ₄ and t _{7 to} t ₈ .

As a result, first, the switch circuit 2A of the sample-hold circuit 2 is on-controlled during the rising period of the sampling pulse P _SM (time points t _{0 to} t ₁ , t _{4 to} t ₅ ), and as a result, the input video signal VD _IN is sampled. Then, during the period when the sampling pulse P _SM falls (time points t _{1 to} t ₄ and t _{5 to} t ₈ ), the switch circuit 2A is turned off and the hold voltage V _HD sampled and held by the hold capacitor 2B is , High-order bit comparison circuit section 3 and low-order bit comparison circuit section 4.

Subsequently, during the period (time points t _{1 to} t ₂ and t _{5 to} t ₆ ) at which the bit comparison pulse P _CC rises, the upper bit latch / encoder circuit 6 compares the comparison results RC ₁ to RC ₁ obtained from the upper bit comparison circuit section 3. The digital data DG _H corresponding to RC ₁₅ is sent as the upper 4 bits of the output digital data DG _OUT .

Also during the subsequently switch changeover pulse P _ST rises period (time _{t 2 ~t 3, t 6 ...} t 7), according to the comparison result RC ₁ to RC ₁₅ obtained from the comparator CC ₁ to CC _15, a reference The switch circuits Sm (1), Sm (2), ..., Sm (1 of the voltage generation circuit 5
4), one of the columns of Sm (15) is selectively turned on, so that the comparison result RC from the reference voltage generation circuit 5
Lower bit comparison reference voltage according to _{1 to} RC ₁₅ VF _{REF1 to} VF
_REF15 is supplied to the lower bit comparison circuit section 4.

The further Subsequently, during the lower bits comparison pulse P _FC rises period (time _{t 3 ~t 4, t 7 ~t} 8), the lower Bitsutoratsuchi / encoder circuit 7 compares the results obtained from the lower bits comparing circuit 4 RF Digital data according to _{1 to} RF ₁₅ DG _L
Is sent as the lower 4 bits of the output digital data DG _OUT , and in this way, the analog digital conversion circuit 1
Is designed to convert the input video signal VD _IN into an analog digital signal every two cycles of the clock CK1 and send out 8-bit digital data DG _OUT .

However, the comparators CC _{1 to} CC of the high-order bit comparison circuit unit 3
Comparator CF ₁ ～CF ₁₅ of ₁₅ and lower bits comparator circuit 4, the first
As shown in FIG. 0, there is a time characteristic T _COMP that the comparison time becomes longer as the compared potential difference becomes smaller.

Therefore, for the comparison time t _C corresponding to the comparison potential difference ΔV _C given to the comparators CC _{1 to} CC ₁₅ of the upper bit comparison circuit section 3, the comparators CF _{1 to} CF ₁₅ of the lower bit comparison circuit section 4 are given. The comparison time t _F corresponding to the comparison potential difference ΔV _F becomes significantly long, and as described above, high comparison accuracy is required when comparing the upper bit and the lower bit at the same time. There is a problem that the comparison accuracy of the lower bits cannot be higher than that of the upper bits. Further, if the frequency of the clock is increased, it is not possible to obtain sufficient comparison accuracy of the lower bits. I got it.

The present invention has been made in consideration of the above points, and by making the comparison time for the lower bits longer than the comparison time for the upper bits, the accuracy is significantly higher than that of the conventional one. It is intended to propose an analog digital conversion circuit that can perform analog digital conversion at high speed.

E Means for Solving the Problems In order to solve the problems, in the present invention, the predetermined reference potential V _RT is synchronized with the first clock pulse P _CC.
And a plurality of resistors R1 (n), R2 connected in series between V and V _BT
(N), ..., R15 (n), R16 (n) (n = 1 to 16) for each predetermined number of connection points R1 (n) and R2 (n) and R3
(N), ..., R14 (n) and R15 (n), multiple potentials obtained from R15 (n) and R16 (n) VC _{REF1 to} VC
_REF15 is _compared with the input analog signal VD _IN to obtain the first comparison result RC _OUT (RC _{1 to} RC ₁₅ ), and then the first clock pulse P _CC and the second clock pulse P having a different duty ratio. While synchronizing with _FCO , the first comparison result RC _OUT (RC ₁ ~ RC
₁₅ ) Multiple resistors Ri within a specified range set based on
(1), Ri (2), ..., Ri (15), Ri (16) (i = 1
To 16) connection points Ri (1) and Ri (2), Ri (2) and Ri
(3), ..., Ri (14) and Ri (15), Ri (15) and Ri
A plurality of potential VF _REF1 ~VF _REF15 obtained from (16), a second comparison result by comparing the input analog signal VD _IN RF _OUT
(RF _{1 to} RF ₁₅ ) is obtained, and the first and second comparison results RC _OUT (RC
_{1 to} RC ₁₅ ) and RF _OUT (RF _{1 to} RF ₁₅ ), the first and second digital data DG _H and DG _L are combined to obtain output digital data DG _OUT. In the first comparison result RC _OUT (RC ₁ ~
Relative comparison time _{t 1 ~t 2, t 5 ~t} 6 to obtain a RC _15), the second comparison result RF _OUT (RF ₁ ~RF ₁₅₎ comparing gain time t ₂₁ ~t _4, t
_61- t ₈ has been lengthened.

F action Comparison time t ₁ to obtain the first comparison result RC _OUT (RC _{1 to} RC ₁₅ )
For t ₂ and t _{5 to} t ₆ , the second comparison result RF _OUT (RF _{1 to} R
By increasing the comparison times t _{21 to} t ₄ and t _{61 to} t ₈ for obtaining F ₁₅ ), the conversion accuracy of the lower bit part of the output digital data DG _OUT can be improved, and conversely the lower bit part can be converted. If the accuracy is selected to the same level as the conventional one, analog digital conversion can be performed at high speed.

G Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) First Embodiment In FIG. 1 in which parts corresponding to those in FIG. 8 are designated by the same reference numerals, 10 indicates an analog digital converting circuit according to the present invention as a whole, in which case the input video signal VD _IN is , And is supplied directly to the ₁₅ comparators CC _{1 to} CC ₁₅ and CF _{1 to} CF _{15 of} the upper bit comparison circuit unit 3 and the lower bit comparison circuit unit 4, respectively, without going through the sample hold circuit 2 (FIG. 8). ing.

Each of the comparators CC _{1 to} CC ₁₅ and CF _{1 to} CF ₁₅ is a so-called checker type comparator circuit CMP using COMS (complementary MOS) inverter circuits INV ₁ , INV ₂ and INV ₃ as shown in FIG. Composed of.

In the comparison circuit CMP, the input video signal VD _IN and the comparison reference voltage V _REF are supplied to the first holding capacitor C via the first and second switch circuits SW ₁ and SW ₂ , respectively.
_It is connected to one end of _H1 and the other end is connected to the input end of the first inverter circuit INV ₁ of CMOS configuration.

The input terminal and the output terminal of the first inverter circuit INV ₁ are
Is connected via the switch circuit SW _3, and whose output end is connected to one end of the second holding capacitor C _H2,
The other end is connected to the input end of the second inverter circuit INV ₂ .

Further, the input terminal and the output terminal of the second inverter circuit INV ₂ are connected via the fourth switch circuit SW _4, and the output terminal thereof is connected to the input terminal of the _third inverter circuit INV ₃ .

As a result, the first, third and fourth switch circuits SW are
By turning ON ₁ , SW ₃ and SW ₄ for a predetermined period, the input video signal VD _IN is sampled and held by the first and second hold capacitors C _H1 and C _H2 , and then the second video signal is held during the second predetermined period. By turning on only the switch circuit SW ₂ of, the first and second hold capacitors C _H1 and C
Hold voltage held at _H2 and comparison reference voltage V _REF
From the output end of the _third inverter circuit INV ₃
The comparison result RT _OUT is transmitted.

In this way, the comparators CC _{1 to} CC ₁₅ and CF ₁ to respectively of the upper bit comparison circuit unit 3 and the lower bit comparison circuit unit 4 are
CF _15, by switching control of the first to fourth switch circuits SW ₁ to SW _4, respectively, the input video signal VD _IN the sampled and held to each other at an arbitrary timing, the hold voltage and the comparison voltage V _REF ( Practically upper bit comparison reference voltage
VC _{REF1 to} VC _REF15 and lower bit comparison reference voltage VF _{REF1 to} V
F _REF15 ), and the comparison result RT _OUT (actually consisting of the upper bit comparison result RC _OUT (RC _{1 to} RC ₁₅ ) and the lower bit comparison result RF _OUT (RF _{1 to} RF ₁₅ )). It is designed to be able to output.

Here, the analog digital conversion circuit 10 is designed to operate at the timing shown in FIG. 3 in which parts corresponding to those in FIG.

In this case, the sampling pulse P _SM (FIG. 3 (B)) and the high-order bit comparison pulse P _CC (FIG. 3 (C)) are each two cycles of the clock CK1 (FIG. 3 (A)) as in the conventional case. Rising period (time points t _{0 to} t ₁ , t _{4 to} t ₅ ) and the trailing edge period of clock CK 1 delayed by 1/2 clock cycle every two cycles (time points t ₁ to t ₂ , t ₅ ~). Selected as the pulse waveform that rises during t ₆ ).

On the other hand, switch switching pulse P _STO (Fig. 3 (D))
Is a switch circuit S of the reference voltage generating circuit 5 having a MOS structure.
Based on the switching characteristics of m (1), Sm (2), ..., Sm (15), Sm (16), the conventional switch switching pulse P
It rises at the same timings t ₂ and t ₆ as _ST (Fig. 9 (D)), and the pulse width changes from 1/2 cycle of the conventional clock CK1.
The pulse width has been changed to 1/4 cycle.

The lower bit comparison pulse P _FCO (Fig. 3 (E)) is
A pulse that rises at a time t ₂₁ , t _{61 that} is 1/4 cycle earlier than clock CK1 with respect to the conventional lower bit comparison pulse P _FC (Fig. 9 (E)), and is longer by 1/4 cycle of clock CK1. Selected for width.

As a result, the analog digital conversion circuit 10 compares the upper bits in the upper bit comparison circuit section 3 with the same comparison time as the conventional one, and compares the lower bits in the lower bit comparison circuit section 4 with the longer comparison time than the conventional one. ing.

In this embodiment, the sampling pulse P _SM , the upper bit comparison pulse P _CC , the switch switching pulse P _STO and the lower bit comparison pulse P _FCO are clocked in the pulse generation circuit 11 as shown in FIGS. 4 and 5. It is designed to occur using CK1.

That is, in the pulse generation circuit 11, the input clock CK1 (FIG. 5 (A)) and the clock CK1 are connected to the inverter circuit.
Inversion clock CK2 obtained via 12 (Fig. 5 (B))
Together with the 1/2 clock CK3 (FIG. 5 (C)) obtained by dividing the clock CK1 through the 1/2 divider circuit 13, together with the first and second AND (AND) circuits 14A and 14B. The sampling pulse P _SM and the upper bit comparison pulse P _CC (FIGS. 5 (D) and 5 (E)) are obtained as the logical output.

Further, the 1/4 cycle delay clock CK4 (FIG. 5 (F)) obtained by inputting the inverted clock CK2 through the 1/4 cycle delay circuit 15 is input to the NAND circuit 16 together with the clock CK1. 1st pulse signal P _X1 (Fig. 5 (G))
The / 2 clock CK3 is input to the first NOR circuit 17A, and the switch switching pulse P _STO (FIG. 5 (H)) is obtained as its logical output.

Furthermore, the above-mentioned first pulse signal P _X1 is ½ clock.
The second pulse signal P _X2 (Fig. 5 (I)) and the 1/2 clock CK3, which are input to the EXNOR (exclusive NOR) circuit 18 together with CK3 and are obtained as a result, are the second NOR (NOR). The lower bit comparison pulse P _FCO (FIG. 5 (J)) is input to the circuit 17B and its logical output is obtained.

In the above configuration, when the input video signal VD _IN is subjected to analog digital conversion, first, during the period when the sampling pulse P _SM rises (time points t _{0 to} t ₁ and t _{4 to} t ₅ ), the upper bit comparison circuit unit 3 and the lower bit each comparator CC ₁ to CC ₁₅ and CF ₁ ~CF ₁₅ of bit comparator circuit unit 4, an input video signal VD
After sampling _IN , the sampled input video signal VD _{IN is held} for the period when the sampling pulse P _SM falls (time points t _{1 to} t ₄ , t _{5 to} t ₆ ).

Subsequently, during the period when the upper bit comparison pulse P _CC rises (time points t _{1 to} t ₂ and t _{5 to} t ₆ ), the comparison units CC _{1 to} CC ₁₅ of the upper bit comparison circuit unit 3 hold the input video signal VD held.
It compares the _IN, the upper bits comparison reference voltage VC _REF1 ~VC _REF15 obtained from the reference voltage generating circuit 5, the comparison result RC
_OUT (RC _{1 to} RC ₁₅ ) is sent to the upper bit latch / encoder circuit 6, and the digital data D corresponding to the comparison result RC _OUT
GH is output as the upper 4 bits of output digital data DG _OUT . Further, subsequently, during the period when the switch switching pulse P _STO rises (time points t _{2 to} t ₂₁ , t _{6 to} t ₆₁ ), the switch of the reference voltage generation circuit 5 is switched according to the comparison result RC _OUT of the upper bit comparison circuit section 3. Circuit Sm (1), Sm (2), ..., Sm (1
5), one of a row of Sm (16) is selectively on-controlled, low-order bits compare lower bits comparison reference voltage VF _REF1 ~VF _REF15 that thereby the reference voltage generating circuit 5 according to the comparison result RC _OUT It is supplied to the circuit unit 4.

Further subsequently lower bits comparison pulse P _FC rises period (time _{t 21 ~t 4, t 61 ~t} 8) between the lower bit comparing circuit comparator CF ₁ ~CF ₁₅ of 4-held input video signal VD _iN, compared with the lower bits comparison reference voltage VF _REF1 ~VF _REF15 obtained from the reference voltage generating circuit 5, and sends the comparison result RF _OUT to (RF ₁ ~RF ₁₅₎ to the lower Bitsutoratsuchi / encoder circuit 7 In the lower bit latch / encoder circuit 7, the digital data DG _L corresponding to the comparison result RF _OUT is sent as the lower 4 bits of the output digital data DG _OUT .

In this manner, the analog digital conversion circuit 10 compares the upper bits in the upper bit comparison circuit section 3 with the same comparison time as the conventional one, and the lower bits in the lower bit comparison circuit section 4 with the longer comparison time than the conventional one. By doing so, it is possible to obtain 8-bit digital data DG _OUT by analog-digital converting the input video signal VD _IN with much higher accuracy than in the past.

According to the above configuration, by comparing the upper bits with the same comparison time as the conventional one and lengthening the comparison time of the lower bits, the input video signal VD _{IN is changed} to the analog digital every two cycles of the clock CK1. By converting and obtaining 8-bit digital data DG _{OUT, it} is possible to realize an analog digital conversion circuit capable of performing analog digital conversion with much higher accuracy than before.

To do this, as analog digital conversion accuracy,
When configuring the one with the same accuracy as before, if the comparison time of the lower bits is the same as the conventional comparison time, the frequency of clock CK1 can be increased by that much, and it is much faster than before. An analog digital conversion circuit capable of analog digital conversion can be realized.

(G2) Second Embodiment In FIG. 6 in which parts corresponding to those in FIG. 1 are designated by the same reference numerals, reference numeral 20 indicates the invention as a whole as proposed in Japanese Patent Application No. 63-16269. An analog digital conversion in which two sets of lower bit conversion means are provided, conversion of the upper bits is performed at twice the speed of conversion of the lower bits, and conversion of the lower bits is alternately executed for each conversion of the upper bits. The case where it is applied to a circuit is shown.

In this analog digital conversion circuit 20, the upper bit comparison circuit section 3 and the upper bit latch / encoder circuit 6 have the same configuration as in the case of FIG. 1, and the digital signals transmitted as the upper 4 bits of the output digital data DG _OUT. the data DG _H, and sends the data selector circuit 21.

Further, the lower bit comparison circuit section and the lower bit latch / encoder circuit are provided with two sets having the same configuration as in the case of FIG. 1, and the first and second lower bit comparison circuit sections 4A and 4B, The first and second lower bits of the output digital data DG _OUT are obtained from the second and second lower bit latch / encoder circuits 7A and 7B, respectively.
Digital data DG _L1 and DG _L2 are data selector circuits
Sent to 21.

The data selector circuit 21 latches the inputted upper 4-bit digital data DG _H and the alternately inputted lower 4-bit first and second digital data DG _L1 and DG _L2 at a predetermined timing. Combine and send as output digital data DG _OUT .

In the case of this embodiment, the analog digital conversion circuit 20
The upper bit comparison circuit section 3 and the first and second lower bit comparison circuit sections 4A and 4B operate at the timing shown in FIG.

That is, as shown in FIG. 7 (B), the bit comparison circuit section 3 has a rising period (time points t _{0 to} t ₁ , t _{2 to} t ₃ , t ₄ ) of the clock CK1 (FIG. 7 (A)). ~ T ₅ , t ₆ ~ t ₇ , t ₈ ~
Sample operation SC1, SC2, SC for sampling the input video signal VD _IN in the comparators CC _{1 to} CC ₁₅ during t ₉ , ...)
3, after ...... executed, followed by the fall of the period of clock CK1 (time _{t 1 ~t 2, t 3 ~t} 4, t 5 ~t 6, t 7 ~t 8, t 9 ~t 10,
During ...), the comparator CC ₁ to CC input video signal VD _IN sampled at _15, the bit comparison operation CC1 to be compared with the upper bits comparison reference voltage VC _REF1 ~VC _REF15 input from the reference voltage generating circuit 5 , CC2, CC3, ... Are executed, and the comparison result RC _OUT obtained as a result is sent to the upper bit latch / encoder circuit 6.

In this way, the upper bit comparison circuit unit 3 and the upper bit latch / encoder circuit 6 output the digital data DG _H obtained by analog-digital converting the input video signal VD _IN for each cycle of the clock CK1.
It is sent to the data selector circuit 21 as the upper 4 bits of G _OUT .

The switch circuits Sm (1), Sm of the reference voltage generation circuit 5
(2), ..., Sm (15), Sm (16) are the comparison operations CC1 and C1 of the bit comparison circuit section 3 as shown in FIG. 7 (C).
C2, CC3, after ...... is completed, followed by 1/4 cycle period of clock CK1 (time _{t 0 ~t 01, t 2 ~t} 21, t 4 ~t 41, t 6 ~
During t ₆₁ , ...), the switch switching operation SW0, SW1, SW2, ... for selectively turning on any of the columns is executed, and the result of comparison RC _OUT of the upper bit comparison circuit unit 3 The lower bit comparison reference voltages VF _{REF1 to} VF REF15 are _supplied to the first and second lower bit comparison circuit sections 4A and 4B, respectively.

Here, the first lower bit comparison circuit section 4A, as shown in FIG. 7 (D), first rises every two cycles of the clock CK1 (time points t _{0 to} t ₁ , t _{4 to} t ₅ , t ₈ ~t _9, ......)
During the period, the first lower bit sampling operation SF for sampling the input video signal VD _IN in the comparators CF _{1 to} CF ₁₅
1, SF3, SF5, after running the ..., followed by the fall of the period of the clock CK1 (time _{t 1 ~t 2, t 5 ~t} 6, t 9 ~t 10, ...
...) and subsequent 1/4 cycle period of clock CK1 it (time _{t 2 ~t 21, t 6 ~t} 61, during ...), the input video signal VD _IN sampled at the comparator CF ₁ ~CF ₁₅ First lower bit hold operation to hold HF1, HF3, HF5, ...
Execute ...

Further, the period (1/4 cycle) of the clock CK1 that follows this (time point
t _{21 to} t ₃ , t _{61 to} t ₇ , ...) and the subsequent clock CK1
Fall period (time _{t 3 ~t 4, t 7 ~t} 8, ......) between the first lower bits comparator circuit unit 4A, the lower bit reference voltage input from the reference voltage generating circuit 5 VF _REF1 ~ VF
The first lower bit comparison operation CF1, CF3, CF5, ... Which compares _REF15 with the held input video signal VD _IN is executed, and the comparison result RF _OUT1 obtained as a result is the first lower bit switch / encoder circuit 7A. Send to.

On the other hand, the second lower bit comparison circuit section 4B is
Lower bit comparison circuit section 4A sampling operation SF1, SF
3, delayed by one cycle of clock CK1 against SF5, ...
Rising period of clock CK1 every two cycles (time t _{2 to} t
_3, t ₆ ~t _7, during ...), comparator CF ₁ second lower bits sampling operation SF2 for sampling an input video signal VD _IN in ~CF _15, SF4, after executing the ...... continues clock the fall of the period of CK1 (time _{t 3 ~t 4, t 7 ~t} 8, ...
...) and subsequent 1/4 cycle period of clock CK1 it (time _{t 4 ~t 41, t 8 ~t} 81, during ...), the comparator CF ₁ input video signal sampled at ~CF ₁₅ VD _IN The second lower bit hold operation HF2, HF4, ...

Further, the period (1/4 cycle) of the clock CK1 that follows this (time point
t _{41 to} t ₅ , t _{81 to} t ₉ , ...) and the subsequent clock CK1
Fall period (time _{t 5 ~t 6, t 9 ~t} 10, ......) between the second lower bits comparing circuit 4B, the lower bit reference voltage input from the reference voltage generating circuit 5 VF _REF1 ~ VF
The second lower bit comparison operation CF2, CF4, ... for comparing _REF15 with the held input video signal VD _IN is executed, and the resultant comparison result RF _OUT2 is sent to the second lower bit latch / encoder circuit 7B. .

Thus, the first and second lower bit comparison circuit sections 4A and
4B is clock C that is shifted by one cycle of clock CK1.
The input video signal VD _IN is converted to analog digital every two cycles of K1, and the first and second comparison results RF _OUT1 and RF
The first and second digital data DG _L1 and DG _L2 obtained based on _OUT2 are sent to the data selector circuit 21 as the lower 4 bits of the output digital data DG _OUT .

Thus, in this analog digital conversion circuit 20, two sets of lower bit conversion means are provided, the conversion of the upper bits is performed at a speed twice as high as the conversion of the lower bits, and the conversion of the lower bits is performed. By performing the conversion alternately for each conversion, analog digital conversion can be performed with a simple configuration at a speed equivalent to that of a so-called flash-type analog digital conversion circuit using 256 conventional comparators. There is.

Furthermore, an analog digital conversion circuit according to this embodiment
At 20, as in the case of FIG. 1, the above bits are compared in the upper bit comparison circuit section 3 at the same comparison time as the conventional one, and the lower bits are compared in the first and second lower bit comparison circuit sections 4A and 4B. By performing comparison with a longer comparison time than before, it is possible to obtain 8-bit digital data DG _OUT by analog-digital converting the input video signal VD _IN with much higher accuracy than before. .

According to the above configuration, by comparing the upper bits with the same comparison time as the conventional one and lengthening the comparison time of the lower bits, the input video signal VD _IN is converted to the analog digital every cycle of the clock CK1. By converting and obtaining 8-bit digital data DG _{OUT, it} is possible to realize an analog digital conversion circuit capable of performing analog digital conversion with much higher accuracy than before.

Further, according to the above configuration, when the conversion accuracy of the analog digital conversion is equivalent to the conventional one, it is possible to increase the frequency of the clock CK1 by making the comparison time of the lower bits the same as the conventional time. In this way, in practice, an analog digital conversion circuit capable of accurately converting the input video signal VD _IN having a high frequency of 40 [MHz] or higher into the 8-bit digital data DG _OUT can be realized.

(G3) Other Embodiments (1) In the above embodiment, when the comparison time of the lower bit is selected longer than the comparison time of the upper bit, the lower bit comparison reference voltage generation switching in the reference voltage generation circuit is performed. The case where the switching time of the switch is shortened by 1/4 cycle of the clock has been described, but the shortening of the switching time of the switching switch is not limited to this, and may be arbitrarily selected as necessary.

In addition to this, not only the switching time of the switching switch is shortened, but also the sampling time of the input video signal and / or the comparison time of the upper bits are shortened so that the comparison time of the lower bits is compared with the comparison time of the upper bits. You can make it longer.

(2) In the above-mentioned embodiment, the case where a chip type comparator circuit having a CMOS inverter circuit configuration is used as a comparator of the upper bit comparison circuit section and the lower bit comparison circuit section is described. If it is a comparator designed to hold while sampling,
Other configurations may be used.

(3) In the above embodiment, the present invention is applied to the case where the input analog signal consisting of the video signal is converted into the digital data consisting of 8 bits, but the analog digital conversion circuit according to the present invention is not limited to this. It is suitable for wide application when converting various input analog signals into various digital data such as 4 or 16 bits.

H. Effect of the Invention As described above, according to the present invention, the second comparison result corresponding to the lower bit portion is obtained for the comparison time for obtaining the first comparison result corresponding to the upper bit portion of the output digital data. By increasing the comparison time, the conversion accuracy of the lower bit part of the output digital data can be improved,
As a result, an analog digital conversion circuit that can perform analog digital conversion with high accuracy and high speed as a whole can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
FIG. 4 is a connection diagram showing the internal configuration of the comparison circuit, FIG. 3 is a timing chart showing the operation of the analog digital conversion circuit of the first embodiment, and FIG. 4 is pulse generation for generating the control pulses shown in FIG. FIG. 5 is a connection diagram showing a circuit, FIG. 5 is a timing chart for explaining the operation thereof, FIG. 6 is a block diagram showing a second embodiment of the present invention, and FIG. 7 is a timing chart for explaining the operation. FIG. 8 is a connection diagram showing a conventional analog digital conversion circuit, FIG. 9 is a timing chart showing its operation, and FIG. 10 is a characteristic curve diagram showing the relationship between the comparison potential difference and comparison time of each comparator. 1, 10, 20 ... Analog digital conversion circuit 3, 4, ...
… Comparison circuit part, 5 …… Reference voltage generating circuit, 6,7 …… Latch / encode circuit, VD _IN …… Input video signal, VC
_{REF1 to} VC _REF15 , VF _{REF1 to} VF _REF15 ...... Comparison reference voltage, RC
_OUT , RC _{1 to} RC ₁₅ , RF _OUT , RF _{1 to} RF ₁₅ …… Comparison result, D
_GH , DG _L , DG _L1 , DG _L2 , DG _OUT ...... Output digital data.

Claims (1)

[Claims] 1. An input analog signal is compared with a plurality of potentials obtained from connection points of a predetermined number of a plurality of resistors connected in series between predetermined reference potentials in synchronization with a first clock pulse. After obtaining the first comparison result, in synchronization with the first clock pulse and the second clock pulse having a different duty ratio, the plurality of resistors within a predetermined range set based on the first comparison result. The first and second digital data obtained based on the first and second comparison results by comparing a plurality of potentials obtained from the connection points In a serial-parallel type analog digital conversion circuit that obtains output digital data by combining the second comparison value with the second comparison time for obtaining the first comparison result.
The analog digital conversion circuit is characterized by a long comparison time for obtaining the comparison result of.