JPH0760851B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a semiconductor device having a wiring structure formed of a plurality of conductive layers with an insulating layer therebetween. The present invention relates to a manufacturing method thereof.

[Prior Art] FIG. 3 is a partial cross-sectional view showing an example of a wiring structure in a conventional semiconductor device. In the figure, a first insulating film 2 is formed on a semiconductor substrate 1 such as silicon. First wiring layers 3 are formed on the first insulating film 2 with a predetermined space therebetween. A second insulating film 4 is formed on the first insulating layer 2 so as to cover the first wiring layer 3. The second wiring layer 5 and the first wiring layer 3 formed thereon are insulated from each other through the second insulating film 4.

In the conventional wiring structure shown in FIG. 3, the second insulating film 4 formed on the first wiring layer 3 has good patterning of the second wiring layer 5 formed thereon. West,
In addition, sufficient flatness is required to improve the reliability of the wiring. Hereinafter, a method of manufacturing the wiring structure shown in FIG. 3 will be described, focusing on the formation of the second insulating film 4. 4A to 4D are partial cross-sectional views showing the formation of the above wiring structure in the order of steps. For the first wiring layer 3 and the second wiring layer 5, a metal wiring layer of aluminum, a refractory metal or the like, a refractory metal silicide wiring layer, a polycrystalline silicon wiring layer, or the like is used, but here, A case where the first wiring layer 3 and the second wiring layer 5 are aluminum wiring layers will be described.

Referring to FIG. 4A, the first formed on the semiconductor substrate 1
A first wiring layer 3 is formed on the insulating film 2.

Next, referring to FIG. 4B, on the first wiring layer 3, for example, silane (SiH ₄ ) and oxygen (O ₂ ) or nitrous oxide (N ₂ O) are used to A silicon oxide film 11 is deposited by a thermal CVD method or a plasma CVD method at a film deposition temperature of ˜450 ° C.

Referring to FIG. 4C, on the silicon oxide film 11, an inorganic coating insulating film 12 containing silanol {Si (OH) ₄ } or the like as a main component is formed.
Is applied. After that, a baking process is performed at a temperature of 400 ° C. or higher to flatten the surface.

Referring to FIG. 4D, silicon oxide film 13 is deposited on inorganic coating insulating film 12 by a method similar to the method shown in FIG. 4B.

Finally, an aluminum wiring layer, for example, is formed as the second wiring layer 5 on the second insulating film 4 including the silicon oxide films 11 and 13 and the inorganic coating insulating film 12. In this way, the wiring structure shown in FIG. 3 is completed.

[Problems to be Solved by the Invention] When the second insulating film 4 in the conventional wiring structure is formed by the method described above, there are the following problems.

As the wiring becomes finer, the wiring interval becomes narrower. When this wiring interval is on the order of submicron, the thickness t ₀ of the inorganic coating insulating film 12 laminated between the wiring layers becomes large. Therefore, if the baking process is performed in the subsequent process, the
As shown in the figure, cracks 14 occur in the coated insulating film 12. This is because the coating insulating film 12 is accompanied by abrupt volume contraction in the baking process. For example, in the case of the coated insulating film 12 containing silanol {Si (OH) ₄ } as a main component, cracks 14 are likely to occur when the thickness t ₀ is 0.5 μm or more.

As described above, when the crack 14 is generated in the coating insulating film 12, even if the silicon oxide film 13 is deposited on the crack 14, the coating insulating film 12
Formation is reflected in the silicon oxide film 13, and the second wiring layer 5
Patterning is disturbed. As shown in FIG. 6, since the step coverage deteriorates in the portion where the crack 14 is generated, the second wiring layer 5 is disconnected. Thus, the cracks generated in the second insulating layer seriously affect the reliability of the wiring.

Therefore, as a method of eliminating such defects of the coated insulating film 12, a chemical vapor deposition method (Chemical Vapor Depos
ition; hereinafter abbreviated as CVD method. There is an attempt to achieve planarization only with the insulating film formed by (1). As one of them, an organic silane, for example, TEOS {(t etra e thylorth
o s ilicate, _{tetraethoxysilane; Si (OC 2 H 5)} 4} and using oxygen, silicon oxide film deposited by a plasma CVD method at a film deposition temperature of 300 to 450 ° C. is used for the planarization. Further, as another example, similarly, an organic silane such as TEOS and ozone (O ₃ ) are used, and a silicon oxide film deposited by a thermal CVD method at a film deposition temperature of 300 to 450 ° C. is used for planarization. To be

The above silicon oxide films have a step coverage higher than that of the conventional silane (SiH ₄ ) because the ratio of the reaction on the substrate surface during the chemical vapor reaction increases by using the organic silane. It becomes an excellent silicon oxide film.

However, the former TEOS + O ₂ system plasma CVD silicon oxide film (referred to as TEOS + O ₂ system oxide film) 21 is, as shown in FIG. 7B, a conventional silicon oxide film 20 using silane (SiH ₄ ). Compared with Fig. 7A), the step coverage is good, but it is not possible to bury the gaps between sub-micron-order wirings and planarize. This is because the film formed by the plasma CVD method has a relatively large proportion of chemical vapor reaction in plasma. Therefore,
In the portion where the wiring interval is narrow, a cavity 22 is created as shown in FIG. 7B.

The latter TEOS + O ₃ system thermal CVD silicon oxide film (hereinafter referred to as TEOS + O ₃ system oxide film) 23, as shown in FIG. 8, tends to have cracks 24 when the film thickness becomes large. . This is because the chemical vapor phase reaction (surface condensation reaction) on the surface of the substrate is mainly present, and therefore exhibits very good step coverage. However, when the film thickness increases, the shrinkage stress of the film itself acts.

Therefore, the present invention has been made in order to solve the above problems, and has excellent crack resistance and good flatness as the second insulating film formed on the first wiring layer. It is an object of the present invention to provide a semiconductor device in which a transparent insulating layer is formed and a manufacturing method thereof.

[Means for Solving the Problems] A semiconductor device according to the present invention includes a semiconductor substrate, a first insulating layer, a first conductive layer, a second insulating layer, and a second conductive layer. Prepare The first insulating layer is formed on the main surface of the semiconductor substrate. The first conductive layer is selectively formed on the first insulating layer at intervals. The second insulating layer is formed on the semiconductor substrate and the first conductive layer. The second insulating layer is formed by alternately stacking first silicon oxide film layers and second silicon oxide layers. The first silicon oxide layer is a chemical vapor phase thin film grown by plasma excitation from a vapor phase containing organic silane and oxygen as main components. The second silicon oxide layer is a chemical vapor phase thin film grown by thermal excitation from a vapor phase containing organosilane and ozone as main components. Second
A second conductive layer is formed on the insulating layer. First
The thickness of each of the silicon oxide layer and the second silicon oxide layer is 500 Å or more and 2000 Å or less.

According to the method of manufacturing a semiconductor device according to the present invention, first, the first insulating layer is formed on the main surface of the semiconductor substrate. First conductive layers are selectively formed on the first insulating layer at intervals. A second insulating layer is formed on the semiconductor substrate and the first conductive layer. The second insulating layer is formed by alternately stacking the first silicon oxide layer and the second silicon oxide layer. The first silicon oxide layer and the second silicon oxide layer each have a thickness of 50
Layers are stacked alternately so that the length is 0 Å or more and 2000 Å or less.
A second conductive layer is formed on the second insulating layer.

[Operation] In the present invention, since the film thickness of the first silicon oxide layer, which is a plasma CVD silicon oxide film using organic silane and oxygen, is 2000 Å or less, it is possible to achieve a wiring interval of submicron order. The deposition of the first silicon oxide layer does not result in a noticeable overhang feature that would result in the cavity 22 as shown in Figure 7B. Further, since the thickness of the second silicon oxide layer, which is a thermal CVD silicon oxide film using organic silane and ozone, is 2000 Å or less, there is a large margin for crack resistance. Further, when the second silicon oxide layer is deposited on the step portion having the wiring interval of submicron level, the step portion is flattened by the chemical vapor phase reaction (surface condensation reaction) on the substrate surface. be able to.

The thickness of each of the first silicon oxide layer and the second silicon oxide layer is set to 500 Å or more in order to improve work efficiency from the viewpoint of productivity.

Therefore, the second insulating layer is formed by the laminated structure in which the first silicon oxide layer having excellent crack resistance and the second silicon oxide layer having excellent flatness are alternately deposited. The second conductive layer formed above is stably patterned, and the reliability of the wiring made of the second conductive layer is also improved.

[Embodiment] An embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a partial sectional view showing a wiring structure according to the present invention. In the figure, a first insulating film 2 is formed on a semiconductor substrate 1. First wiring layers 3 are formed on the first insulating film 2 at a distance from each other. A second insulating film 100 is deposited on the first insulating film 2 so as to cover the first wiring layer 3. The second insulating film 100 is TEOS
+ O ₂ -based oxide films 101, 103, 105, 107 and TEOS + O ₃ -based oxide film 10
It consists of 2,104,106. The second wiring layer 108 is formed on the second insulating film 100.

Next, a method of forming the second insulating film in the wiring structure shown in FIG. 1 will be described. 2A to 2F,
FIG. 7 is a partial cross-sectional view showing a method of forming the wiring structure shown in FIG. 1 in process order. The case where the first wiring layer 3 and the second wiring layer 108 are aluminum wiring layers will be described.

First, referring to FIG. 2A, first wiring layers 3 spaced apart from each other are formed on a first insulating film 2 formed on a semiconductor substrate 1 made of silicon or the like.

Referring to FIG. 2B, TEOS + is formed so as to cover the first wiring layer 3.
An O ₂ based oxide film 101 is formed. The formation of the first-layer silicon oxide film is performed by plasma CVD using TEOS and oxygen at a film deposition temperature of 300 to 450 ° C.

This silicon oxide film has excellent crack resistance,
Step coverage is not sufficient. In Figure 9A, TE
The case where the film thickness t _{1 of the} OS + O ₂ -based oxide film 101 is 2000 Å or less is shown. As shown in FIG. 9B, TEOS + O ₂ system oxide film 109
If the film thickness t ₁ of the first wiring layer 3 becomes larger than 2000 Å, an over-hank 110 is generated at the step portion between the first wiring layers 3. Therefore, when the TEOS + O ₂ based oxide film is formed on the first wiring layer 3 having a wiring interval of submicron order, the film thickness t ₁ needs to be 2000 Å or less.

Referring to FIG. 2C, a _second film is formed on the TEOS + O ₂ -based oxide film 101.
A TEOS + O ₃ based oxide film 102 is deposited as a silicon oxide film of the layer. The formation of this silicon oxide film is performed by a thermal CVD method using TEOS and ozone at a film deposition temperature of 300 to 450 ° C.

This silicon oxide film is very excellent in step coverage, but inferior in crack resistance. FIG. 10A shows the case where the film thickness t ₂ of the TEOS + O ₃ based oxide film 102 is 2000 Å or less. As shown in FIG. 10B, when the film thickness t ₂ of the TEOS + O ₃ -based oxide film 111 increases to more than 2000 Å, the crack 112 causes the first crack 112 due to the shrinkage stress of the film itself.
Will occur at the step portion between the wiring layers 3. for that reason,
In the case where the TEOS + O ₃ based oxide film 102 is formed in the step portion between the first wiring layers 3 having a wiring interval of submicron order,
The film thickness t ₂ needs to be 2000 Å or less in the flat portion.

Further, as shown in FIG. 2D, as in the step shown in FIG. 2B, a TEOS + O ₂ -based oxide film 103 is deposited on the TEOS + O ₃ -based oxide film 102 as a third-layer silicon oxide film. It Also in this case, for the same reason as above, the thickness of the silicon oxide film is set to 2000 Å or less.

Referring to FIG. 2E, as in the step shown in FIG. 2C, the TEOS + O ₃ based oxide film 104 is used as the fourth silicon oxide film.
Are deposited on the TEOS + O ₂ -based oxide film 103. Also in this case, for the same reason as above, the thickness of the silicon oxide film is set to 2000 Å or less in the flat portion.

As shown in FIG. 2F, the TEOS + O ₂ -based oxide film 105 of the fifth layer, the TEOS + O ₃ -based oxide film 106 of the sixth layer, and the seventh layer are formed by repeatedly depositing a silicon oxide film in the same manner. The TEOS + O ₂ -based oxide film 107 of the eye is sequentially formed. In this way, the second insulating film 1 in which the TEOS + O ₂ based oxide films 101, 103, 105, 107 and the TEOS + O ₃ based oxide films 102, 104, 106 are alternately laminated
00 is formed.

Finally, the second wiring layer 108 is formed on the second insulating film 100. As a result, the wiring structure shown in FIG. 1 is completed.

In the above process, the formation of the second insulating film is
It can be easily carried out using the chemical vapor phase reactor shown in FIG. Referring to FIG. 11, a gas dispersion head 202 and a substrate holder 204 are arranged inside the reaction chamber chamber 201 so as to face each other. A semiconductor substrate 203 on which an insulating film is to be deposited is placed on the substrate holder 204. The substrate holder 204 is provided with a heater 205 for heating the semiconductor substrate 203 to a desired temperature. The gas dispersion head 202 includes a TEOS gas supply line valve 206, an O ₂ gas supply line valve 207, and an O ₃ gas supply line valve 208.
The respective gas supply lines are connected via and. A high-frequency power source 209 is connected to the gas dispersion head 202 to generate plasma inside the reaction chamber chamber 201. This high-frequency power source 209 has high-frequency power ON / OF.
An F switch 210 is provided. The substrate holder 204 facing the gas dispersion head 202 is kept at the ground potential. The reaction chamber chamber 201 is connected to a vacuum exhaust system 211 as indicated by an arrow in order to keep the inside of the reaction chamber chamber 201 in a predetermined vacuum state.

Using such a chemical vapor phase reaction device, the semiconductor substrate 203
After being placed on the substrate holder 204, it is heated to the desired temperature, eg 300-450 ° C. After that, evacuation system
Using 211, the inside of the reaction chamber chamber 201 has a desired degree of vacuum,
For example, it is exhausted until it reaches about 10 ^-4 Torr.

When depositing a TEOS + O ₂ -based oxide film, the TEOS gas supply line valve 206 and the O ₂ gas supply line valve 207 are opened. TEOS gas and O ₂ gas are supplied at a predetermined flow rate through the gas dispersion head 202 to the inside of the reaction chamber chamber 201 for 10 to 100 Tor.
Supplied under pressure of about r. In this state, by turning on the high frequency power ON / OFF switch 210, plasma is generated inside the reaction chamber chamber 201.
By this plasma excitation, a silicon oxide film is grown on the semiconductor substrate 203 by chemical vapor deposition.

When depositing a TEOS + O ₃ -based oxide film, the high-frequency power ON / OFF switch 210 is turned off and the O ₂ gas supply line valve 20
After the 7 is closed, the O ₃ gas supply line valve 208 is opened. Reaction chamber chamber 2 via bath dispersion head 202
Inside 01, under a pressure of about 10 to 100 Torr, a gas having a predetermined flow rate, for example, O containing 10000 to 50000 ppm of O _3
2 Gas is supplied. As a result, a chemical vapor phase reaction due to thermal excitation occurs on the surface of the semiconductor substrate 203, and a silicon oxide film is deposited.

In order to continuously and alternately deposit the TEOS + O ₂ -based oxide film and the TEOS + O ₃ -based oxide film in the same reaction chamber, the above operation may be repeated alternately. Therefore, according to the present invention, the chemical vapor phase reactor shown in FIG.
It becomes possible to easily deposit the types of silicon oxide films alternately.

In the above embodiment, the case where the lowermost layer and the uppermost layer of the second insulating film 100 are both TEOS + O ₂ -based oxide films is shown. However, the object of the present invention is to
It is to alternately deposit two kinds of silicon oxide films having a film thickness of 2000 Å or less, and either the bottom layer or the top layer or both of them are TEOS + O ₃ type oxide films,
Has the same effect.

Further, in the above embodiment, the TEOS + O ₂ -based oxide film and the TEOS
The case where all of the second insulating film is formed by alternately depositing + O ₃ -based oxide film is described. However, for the purpose of further improving the flatness of the second insulating film, the insulating film made of the two types of silicon oxide films may be combined with the coating insulating film, or the insulating film made of the two types of silicon oxide films may be used. The same effect can be obtained even if the film is deposited and then etched back using reactive ion etching, sputter etching, or the like.

Further, in the above-mentioned examples, the case where TEOS is used is shown as an example of the organic silane. However, other organosilanes, such as Si (OCH ₃ ) ₄ [tetramethoxysilane], Si (OiC ₃ H ₇ ) ₄ [tetraisopropoxysilane], (tC ₄ H ₉ O ₂ ) Si (OOCCH ₃ ) ₂ The same effect can be obtained by using an organic silane such as [DADBS, ditertiarybutoxyacetoxysilane].

In the above embodiment, the case where the film is formed using only the organic silane and oxygen or ozone is described. PO (OCH ₃ ) ₃ [Phosphorus] is used as a means for doping impurities into the silicon oxide film, containing these gases as the main components and further improving the crack resistance of the film, such as phosphorus (P) and boron (B). Acid trimethyl ester], B
Even when (OC ₂ H ₅ ) ₃ [boron ethylate] or the like is added, the same effect is obtained.

In the above embodiments, the case where the first wiring layer and the second wiring layer are aluminum wiring layers has been described, but those wiring layers are made of refractory metal (W, Mo, Ti, etc.), The same effect can be obtained even with a refractory metal silicide (WSi ₂ , MoSi ₂ , TiSi _2, etc.) wiring layer or a polycrystalline silicon wiring layer.

[Effects of the Invention] As described above, according to the present invention, the step coverage is not sufficient, and the first silicon oxide layer having excellent crack resistance and the step coverage are very good. An inferior second silicon oxide layer,
The second insulating layer having both crack resistance and flatness can be formed because the layers are alternately and repeatedly deposited with a relatively thin film thickness of 2000 Å or less. Therefore, the patterning of the second wiring layer formed on the second insulating layer becomes stable, and the reliability of the wiring is improved. As a result, a semiconductor device having high yield and high reliability can be provided.

[Brief description of drawings]

FIG. 1 is a partial sectional view showing an embodiment of a wiring structure of a semiconductor device according to the present invention. 2A, 2B, 2C, 2D, 2E, 2F,
FIG. 3 is a partial cross-sectional view showing a method of forming an insulating film in the wiring structure shown in FIG. 1 in step order. FIG. 3 is a partial cross-sectional view showing a wiring structure in a conventional semiconductor device. FIG. 4A, FIG. 4B, FIG. 4C, and FIG. 4D are partial cross-sectional views showing a method of forming an insulating film in the order of steps in the conventional wiring structure shown in FIG. FIG. 5 and FIG. 6 are partial cross-sectional views showing the problems of the coated insulating film in the conventional wiring structure. FIGS. 7A and 7B show TEOS and a silicon oxide film formed by using silane and nitrous oxide in the conventional wiring structure.
3 is a partial cross-sectional view showing a problem of a silicon oxide film formed by using oxygen and oxygen. FIG. 8 is a partial cross-sectional view showing a problem of the silicon oxide film formed by using TEOS and ozone in the conventional wiring structure. FIG. 9A and FIG. 9B are partial cross-sectional views showing the differences in the thickness of the silicon oxide film formed using TEOS and oxygen for comparison. FIG. 10A and FIG. 10B are partial cross-sectional views showing the differences in the thickness of the silicon oxide film formed by using TEOS and ozone for comparison. FIG. 11 is a schematic configuration diagram showing an example of a chemical vapor deposition reactor capable of carrying out the method for depositing an insulating film in a wiring structure according to the present invention. In the figure, 1 is a semiconductor substrate, 2 is a first insulating film, 3 is a first wiring layer, 100 is a second insulating film, and 101, 103, 105 and 107 are
TEOS + O ₂ system oxide film, 102, 104, 106 are TEOS + O ₃ system oxide film, 1
08 is a second wiring layer. In each drawing, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A semiconductor device having a wiring structure composed of a plurality of conductive layers formed with an insulating layer interposed therebetween, comprising: a semiconductor substrate having a main surface; and a semiconductor substrate formed on the main surface of the semiconductor substrate. A first insulating layer, a first conductive layer selectively formed on the first insulating layer at intervals, and an organic silane on the semiconductor substrate and the first conductive layer. A first silicon oxide layer grown by chemical vapor deposition from a gas phase containing oxygen as a main component by plasma excitation, and a chemical vapor deposition thin film by thermal excitation from a gas phase containing organic silane and ozone as main components. A second insulating layer in which grown second silicon oxide layers are alternately stacked; and a second conductive layer formed on the second insulating layer, The thickness of each of the silicon oxide layer and the second silicon oxide layer is It is 500Å or more 2000Å or less, the semiconductor device. 2. A method of manufacturing a semiconductor device having a wiring structure composed of a plurality of conductive layers formed with an insulating layer interposed therebetween, which is a step of forming a first insulating layer on a main surface of a semiconductor substrate. And a step of selectively forming a first conductive layer on the first insulating layer with a space between the first insulating layer and the semiconductor substrate and the first conductive layer. The first silicon oxide layer, which was chemically vapor-deposited by plasma excitation from the component gas phase, and the chemical vapor-phase thin film, which was thermally excited from the gas phase containing organosilane and ozone as the main components. A step of forming a second insulating layer by alternately stacking second silicon oxide layers, and a step of forming a second conductive layer on the second insulating layer; One silicon oxide layer and the second silicon oxide layer are each Thickness as is 500Å or more 2000Å or less, it is alternately laminated, a method of manufacturing a semiconductor device.