JPH0628424B2 - Image display device drive circuit - Google Patents

Description

The present invention relates to a drive circuit for an image display device such as a liquid crystal matrix panel.

(B) Prior art FIG. 4 is a diagram showing a drive circuit of a liquid crystal display device using an active matrix liquid crystal panel used in a liquid crystal TV device, and such a circuit is described in, for example, Japanese Patent Laid-Open No. 57-41078. ing.

In the figure, an active matrix type liquid crystal panel (1) has pixels in n columns in the x direction and m rows in the y direction.
T composed of × n amorphous silicon (a-si)
FT (thin film transistor) (1a) and liquid crystal electrode (1
b) are connected in a matrix as shown, and each row (G ₁ , G ₂ ... Gm) and each column (D ₁ , D ₂ ... Dn) is connected to a row driver (2) and a column driver (3), respectively. Has been done. The row driver is an m-stage shift register (2
a) and an output circuit (2b), and the column driver includes an n-stage shift register (3a), a sample hold circuit (3b), and an output circuit (3c). (4) is a synchronization control circuit, which is a horizontal synchronization signal (H
p) and the vertical synchronization signal (Vp) based on the first and second
A start pulse (ST ₁ ) (ST ₂ ) and first and second clock pulses (CP ₁ ) (CP ₂ ) are created.

FIG. 5 is a diagram showing each waveform of the row driver.
Represents a video signal, on which a vertical synchronizing signal (Vp) and a horizontal synchronizing signal (Hp) are superimposed. In the figure, T ₁ is a vertical synchronizing signal section, T ₂ is a vertical blanking section, and T ₃ is a video signal section.

The shift register (2a) has a first start pulse (ST ₁ ) synchronized with the vertical synchronizing signal shown in FIGS.
And the first clock pulse (CP
₁ ) and each row G ₁ , G ₂ ... Has (d) (e)
As shown in (f), voltage waveforms shifted by 1H (one horizontal period) are applied. With this voltage waveform, the TFTs (1a) in each row are sequentially turned on in the horizontal blanking interval to apply the liquid crystal drive voltage to each pixel.

On the other hand, the waveform of each part of the column driver (3) is as shown in FIG. The column drive repeats the same operation in each 1H section. FIG. 8A is a video signal drawn by extending the 1H section at T ₃ . In the figure, T ₄ is a horizontal synchronizing signal section and a horizontal blanking section, and T ₅ is a section containing video information.

The shift register (3a) has a second start pulse (ST ₂ ) synchronized with the horizontal synchronizing signal shown in FIGS. 6 (b) and 6 (c).
And a second clock pulse having a frequency of its period τ = T ₅ / n is given, and the output of each stage of the shift register (3a) is sequentially incremented by τ as shown in (d), (e) and (f) of FIG. The staggered pulses are output. Sample and hold circuit (3
Each stage of b) is controlled by the output of the shift register of the corresponding stage, and the voltage value of the video signal is sampled by the fall of the output and held until the next sampling time (for 1 H). The output circuit (3c) receives the output of the sample-hold circuit, buffers and increases the width, and drives the column electrode.

The output circuit (2b) in the above-mentioned row driver (2) is composed of, for example, an FET circuit as shown in FIG. 7 (the figure shows only one row). This circuit is general as an output circuit.

On the other hand, generally, in an active matrix using TFTs, when selecting each row, it is desired that only the row to be selected be high and all other rows be low.

In the output circuit, when the input is high, the FET
When (T ₁₄ ) is on and the FET (T ₁₆ ) is off, the output becomes high, but at this time, the FET that becomes a load
Only a relatively small current flows through (T ₁₃ ) and the inverting FET (T ₁₄ ), and no current flows through the amplification FET (T ₁₆ ). On the other hand, when the input is low, the FET (T ₁₄ ) is off and the FET (T ₁₆ ) is on and the output is low. At this time, the FET (T ₁₅ ) which becomes a load and the F
A relatively large current flows through ET (T ₁₆ ).

That is, in the case of a 240-row matrix, almost no current flows through the output circuit for the selected one row, but the remaining 239
A large current is constantly flowing through the output circuits for the rows, which has a drawback that the power consumption becomes very large.

An output circuit as shown in FIG. 8 can be considered as a method for solving the above-mentioned drawbacks, that is, a pair of first and second cascade-connected output circuits.
One of the FETs (T ₁₇ ) (T ₁₈ ) (T _18
17 ) applies an input signal to the gate of the FET, applies a signal obtained by inverting the input signal via the inverters (T ₁₉ ) (T ₂₀ ) to the other FET gate, and outputs an output signal from the connection point of both FETs. ing. According to this circuit, no current flows in the steady state when the output signal is high or low, so that the power consumption can be greatly reduced.

However, in the above circuit, the other FET
Since one FET is inserted as an inverter in the gate of (T ₁₈ ), the switching timing of this FET delays the switching timing of the other FET. Therefore, when the output signal switches from low to high,
Since the pair of FETs are simultaneously turned on for a short time, a large transient current flows. Further, the FE for the inverter
The switching time is doubled because of T.

(C) Problems to be Solved by the Invention The present invention has been made in view of the above-mentioned points, and when the output signal is switched, a large transient current does not flow in the output circuit, and the switching time becomes long. The present invention provides a drive circuit that does not have such a problem.

(D) Means for Solving the Problems The present invention is directed to a counter for counting clock pulses to derive a binary count value and its inverted output, and a pair of pulses for decoding the output to sequentially shift and having opposite polarities. And a first FET and a second FET in which the pair of pulses are applied to each gate.
And an output circuit for outputting an output signal increased from the connection point to the active matrix panel.

(E) Action The above-mentioned means acts so that a current does not flow in each FET of the output circuit in a steady state and a transient current does not flow during switching.

(F) Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a drive circuit of a liquid crystal display device in the present embodiment. The same parts as those in FIG.

In the figure, (50) is the first clock pulse (C) generated by the first start pulse (ST ₁ ) from the synchronization control circuit (4).
Start counting P ₁ ) and output binary count (A)
It is a first counter that outputs (B) and reverse output () (). For example, IC manufactured by Tokyo Sanyo: LC4520B
And LC4049B. (51) is a first decoder that decodes the output of the first counter and outputs pulses that sequentially become high and low for each first clock pulse (CP ₁ ) to the left and right of each row G ₁ , G _2, ... (60) is a second counter that outputs a binary count output based on the second start pulse (ST ₂ ) and the second clock pulse (CP ₂ ) from the synchronous control circuit (4), and (61) is this second counter. A second counter that decodes the output of the two counters and outputs a pulse that sequentially goes high for each second clock pulse (CP ₂ ) to each of the columns D ₁ , D _2, ...
It is a decoder. In this embodiment, the function corresponding to the conventional shift register is replaced with a binary counter and a decoder. Therefore, the first counter (50), the first decoder
A row driver (5) is constituted by the (51) and the output circuit (52), and a column driver (6) is constituted by the second counter (60), the second decoder (61), the sample hold circuit (62) and the output circuit (63). ) Is configured. Then, the first and second decoders
(51) (61), output circuit (52) (63) and sample hold circuit
(62) is formed of a-SiTFT on the same substrate as the liquid crystal panel (1) and in the same step.

FIG. 2 shows a specific circuit of the row driver. First counter
The code signal lines of the binary count output (A) (B) and the inverted output () () from (50) are the lines (L ₁ ) provided corresponding to the rows G ₁ , G ₂ ... Of the matrix panel. To (L ₄ ) are crossed in a matrix and TFTs (T ₁ ) that form two AND gates for each line
To (T ₈ ) are arranged, and each of the lines (L ₁ ) to (L ₄ ) is arranged.
, A high level is output when any _{one of} the rows G ₁ , G _2, ... Is selected.

Further, the code signal lines are provided in the rows G ₁ , G _2, ...
Corresponding to the lines (L ₁ ) to (L ₄ ), the lines (L ₁ ′) (L ₄ ′) provided adjacent to the lines (L ₁ ′) to (L ₄ ′) intersect in a matrix, and each line similarly has a TFT. (T ₁ ′) 〜
(T ₈ ′) are arranged and each of the lines (L ₁ ′) to
Low is output to (L ₄ ′) when any _{one of} the rows G ₁ , G ₂ ... Is selected. That is, the output of the opposite phase appears on two adjacent lines (L ₁ ) (L ₁ ′).

Output circuit (52) each line _{G 1,} G 2 _... first are a pair of cascaded for each, row _G 1 from the first _{FET 42} (T 17) connecting point of both FET consists of _{(T 18), G 2} ... Are connected. Lines (L ₁ ) to (L ₄ ) are coupled to the gates of the first FET (T ₁₇ ) and lines (L ₁ ′) to (L ₄ ′) are coupled to the gates of the second FET (T ₁₈ ). Has been done.

Next, the operation will be described. Now, when the counter output is "00" (A) (B) both in "0" () () are "1" _{TFT (T} 1) (T ₂₎ (T 4) _{(T 5)} and (T
_{1 ') (T 2')} (T 4 ') (T 5') because is on line _{(L 1)} is high, the line _{(L 2) ~ (L 4} ) is low, further lines _(L 1) Is low, line (L ₂ ') ~
(L ₄ ′) goes high. Therefore, the first FET
(T ₁₇ ) is turned on, the second FET (T ₁₈ ) is turned off, and a high output is output to the row G ₁ . At this time, the first FETs in the other rows are all off and the second FETs are all on,
All outputs are low.

The next time the counter output is "01" (A) () is "0", () (B ) is "1" TFT _(T 2)
(T ₃ ) (T ₄ ) (T ₇ ) and (T ₂ ′) (T ₃ ′)
Since (T ₄ ′) and (T ₇ ′) are turned on, the line (L ₂ )
Is high, line (L ₁ ) (L ₃ ) (L ₄ ) is low, line (L ₂ ′) is low, line (L ₁ ′) (L ₃ ′)
(L ₄ ′) goes high. Therefore, the first of the second line (G ₂ )
The FET (T ₁₇ ) is turned on, the second FET (T ₁₈ ) is turned off, and a high output is output to the row G ₂ .

As described above, when the counter output is sequentially incremented, the next row becomes high sequentially and is selected, and the TFT in the liquid crystal panel of that row is driven.

Then, when the driving of all the rows is completed and the first counter (50) is reset by the next start signal, the next frame scanning is started.

In the above row driver, since the decoder simultaneously outputs two signals of opposite phases corresponding to each row, the first and second F
Since a completely opposite phase signal is applied to each gate of ET, current does not flow at all in the steady state and switching delay of one FET does not occur as shown in FIG. They do not turn on at the same time and a large transient current does not flow. FIG. 3 shows another embodiment of the row driver. In this embodiment, the decoder (51) and the first and second FETs (T ₁₇ ) (T ₁₈ ) of the output circuit (52) are separately arranged on both sides of the liquid crystal panel (1).
When integrated with the liquid crystal panel substrate, it can be formed symmetrically.

The operation is exactly the same as in the case of FIG.

It should be noted that although the above two embodiments have been described with respect to the row driver, it is obvious that the present invention can be applied to the column driver as well.

(G) Effect of the Invention As described above, according to the present invention, the output circuit has no current flowing at all in a steady state, and no large transient current flows at the time of switching. Can be reduced to Moreover, the switching time does not become unnecessarily long.

[Brief description of drawings]

FIG. 1 is a block diagram of a drive circuit of a liquid crystal display device according to an embodiment of the present invention, FIG. 2 is a concrete circuit diagram of a row driver, and FIG. 3 is a concrete circuit diagram of another embodiment of the row driver. FIG. 4 is a diagram showing a conventional drive circuit, FIG. 5 is a waveform diagram of essential parts of a row driver, FIG. 6 is a waveform diagram of essential parts of a column driver, and FIG. 7 is a first conventional example of an output circuit. 8 and 9 are diagrams showing a second conventional example of the output circuit. (1) …… Liquid crystal panel, (4) …… Synchronous control circuit,
(2) (5) …… row driver, (3) (6) …… column driver, (51) (61) …… decoder, (52) (53) …… output circuit,
(T ₁₇ ) (T ₁₈ ) ... First and second FETs.

Claims (1)

[Claims] 1. A method for driving each pixel by selecting each row and each column of an active matrix panel, in which a plurality of pixels are arranged in a matrix, by a clock pulse of a predetermined frequency. A counter that counts and derives a binary count value and its inverted output, and a counter output that decodes the counter output and sequentially shifts a pair of pulses of opposite polarity to each row and / or column in synchronization with the clock pulse. A decoder which is generated at the same time, and a pair of first and second FETs in which the pair of pulses having the opposite polarities are respectively applied to the respective gates and which are connected in cascade.
And an output circuit for outputting an output signal, which is amplified from the connection point of both FETs, to the active panel.