JPH0772964B2 - Head amplifier for control signal - Google Patents

Description

The present invention relates to a control signal head amplifier for amplifying a control signal from a video tape.
In particular, the present invention relates to a control signal head amplifier capable of accurately detecting a control signal.

(B) Conventional technology Generally, a CTL signal with a duty of 50% to 60% is recorded on a control (hereinafter referred to as CTL) track of a video tape, and the CTL signal during playback controls the rotary head or capstan. Is used for. However, recently, a device has been introduced in which the duty of the CTL signal is changed to a predetermined ratio and used as a cue signal for a video tape. The cueing signal can be always recorded at the start of VTR recording, or can be superposed and recorded on the CTL signal once recorded. FIG. 2 is a circuit diagram showing the VTR when the cue signal is re-recorded on the CTL signal. First, when the first switch (1) is switched to the side shown, the CTL head (2) Is applied to the CTL amplifier (3) and the positive polarity amplifier (4) via the first switch (1) and is amplified. The output signal of the positive polarity amplifier (4) is used as a control signal for the rotary head or capstan, and is applied to the gate pulse generation circuit (5). Then, the gate pulse generating circuit (5) generates a delay for a certain period of time from the CTL signal,
A gate pulse that ends before the next CTL signal is generated. The gate pulse is applied to the second switch (6), and when the second switch (6) is turned on by a write command which is a command to input the cue signal from the terminal (7), the gate pulse is turned on. It is applied to the first switch (1) via the second switch (6) to switch the movable terminal of the switch (11). Then, the cue signal from the cue signal recording circuit (8) which operates according to the output signal of the gate pulse generating circuit (5) is applied to the CTL head (2) through the first switch (1), CTL Rewrite the CTL signal duty of the track. Therefore, according to the circuit shown in FIG. 2, the cue signal can be recorded at a desired position on the CTL track.

The circuit shown in FIG. 2 is described in Japanese Patent Publication No. 60-48811.

(C) Problem to be Solved by the Invention By the way, the level of the CTL signal from the CTL head (2) in FIG. 2 is usually several mV, which is a very small signal.
Therefore, the CTL amplifier (3) requires a high gain of about 60 dB. In this state, when a bipolar transistor is used as the first switch (1), a base current flows, so that an offset occurs and a large switching noise occurs in the output. Then, the switching noise may be erroneously determined to be the CTL signal. Therefore, the first switch (1) is usually MOS
Type transistor was used. However, since the other circuits in FIG. 2 are all composed of bipolar transistors and built in one integrated circuit, there is a problem in that the entire head amplifier cannot be formed in a single integrated circuit.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned points. Therefore, a current output type amplifier circuit for amplifying a control signal from a control head, and the amplifier circuit according to a read / write pulse. It is characterized by comprising a bias supply circuit for supplying a bias to and a power source for applying a voltage to the output terminal of the amplifier circuit via a resistor.

(E) Action According to the present invention, a constant voltage is applied to the output terminal of the current output type amplifier circuit composed of the bipolar transistor through the resistor to supply the bias to the amplifier circuit when the control signal is reproduced. Therefore, the DC level of the output terminal can be made constant regardless of the read / write switching operation.

(F) Embodiment FIG. 1 is a circuit diagram showing an embodiment of the present invention. (9) is a CTL head for recording / reproducing a CTL signal on / from a CTL track of a video tape (not shown), (10) And (11) are the CTL
A transistor to which the CTL signal from the head (9) is applied to the base, (12) and (13) transistors to which a common bias is applied to the base and the CTL signal is applied to the emitter, and ( 14 ) is the transistor ( Current mirror circuit for detecting the difference current between the input currents from (12) and (13), (15)
Is the transistor (10), (11), (12), and (1
An amplifier circuit consisting of 3) and a current mirror circuit ( 14 ), (16)
Is an output terminal of the amplifier circuit (15), (17) is a power supply for applying a constant voltage to the output terminal (16) via a resistor (18), and (19) is an input signal from the output terminal (16). operational amplifier for amplifying a, (20) the feedback circuit of a resistor (21) and (22) and the operational amplifier comprising a capacitor (23) (19), (24) is a waveform for waveform shaping the output signal of the operational amplifier (19) Shaping circuit, (25) is the waveform shaping circuit (24)
Three timing pulses P ₁ , P ₂ and P depending on the output signal of
_A first timing pulse generation circuit for generating ₃ (26) is composed of a delay circuit (27), an AND gate (28) and an OR gate (29), and generates two read / write pulses according to the first timing pulse P _1. A second timing pulse generating circuit, ( 30 ) a bias supply circuit for supplying a bias to the transistors (12) and (13) according to the output signal (first read / write pulse) of the orgade (29), (31) is gain control means for controlling the gain of the operational amplifier (19) according to the output signal (second read / write pulse) of the AND gate (28), and (32) is the first timing pulse generation circuit ( In response to the second and third timing pulses P ₂ and P ₃ from 25), the CTL signal corresponding to the cue signal is recorded in the CTL head (9) C
TL signal recording circuit.

First, the case of reproducing the CTL signal recorded on the CTL track with a duty of 50% will be described. When reproducing, the operation of the first timing pulse generation circuit (25) is stopped. Then, the transistor (33) of the bias supply circuit ( 30 ) is turned off, the transistor (35) of the differential amplifier circuit ( 34 ) is turned off, and the transistor (36) is turned on. Then, a constant voltage is applied as a bias from the collector of the transistor (36) to the bases of the transistors (12) and (13) of the amplifier circuit (15), and the amplifier circuit (15) is in an operating state. Then, the CTL signal from the CTL head (9) is applied to the bases of the transistors (10) and (11),
It is applied from its emitter to the emitters of transistors (12) and (13) via resistors (37) and (38), respectively. Therefore, a current according to the CTL signal flows through the collectors of the transistors (12) and (13), and the output terminal (1
In 6), a difference current between the two currents is generated. The differential current, that is, the amplified CTL signal is applied to the operational amplifier (19) via the output terminal (16), further amplified, and led to the output terminal (39). The CTL signal derived to the output terminal (39) is used to control the rotary head or the capstan.

Next, a case where the cue signal is recorded on the CTL track in which the CTL signal with a duty of 50% is once recorded as shown in FIG. 3A will be described. In this case, the first timing pulse generation circuit (2
5) starts operation. At this time, since it is in the reproducing state, the output terminal (39) has a duty cycle as shown in FIG.
A 50% CTL signal is generated and applied to the waveform shaping circuit (24). An output signal as shown in FIG. 3C is generated at the output end of the waveform shaping circuit (24) and applied to the first timing pulse generation circuit (25). Then, the first
The timing pulse generator (25) three timing pulses from P _1, P ₂ and P ₃ generated, Figure 3 a first timing pulse P ₁ to be delayed from the signal (d) (FIG. 3 (e) ) Is applied to the second timing pulse generation circuit (26). Then, an output signal as shown in Fig. 3 (e) is generated at the output end of the delay circuit (27), and the input signals of the AND gate (28) and the OR gate (29) are shown in Fig. 3 (d) and (e). ) Signal is applied. Then, at the output end of the OR gate (29), a signal of FIG. 3 (f) corresponding to a read / write pulse is generated, inverted by the inverter (40), and then applied to the base of the transistor (33). On the other hand, the CTL signal recording circuit (32) should be recorded with the second timing pulse P _{2 as} shown in FIG. 3 (H) for determining the recording timing of the cueing signal from the first timing pulse generation circuit (25). In order to determine the duty of the CTL signal, a third timing pulse P _{3 as} shown in (i) of FIG. 3 for polarity inversion is applied. The period T _{1 in} FIG. 3F is a period for reading the CTL signal, and the transistor (33) is turned off during the period T ₁ . Then, the transistor (3) of the differential amplifier circuit ( 34 )
Since 5) is turned off and the transistor (36) is turned on, a bias is applied to the bases of the transistors (12) and (13), and the amplifier circuit (15) is in an operating state. Therefore, CTL
The CTL signal from the head (9) is amplified by the amplifier circuit (15) and applied to the operational amplifier (19) via the output terminal (16). At this time, the DC potential of the output terminal (16) is not determined by the output of the amplifier circuit (15), but is regulated by the voltage of the power supply (17). Then, the amplified CTL signal is output to the output terminal (3
9) is derived. Next, a period T _{2 in} FIG. 3F is a writing period of the cue signal, and the transistor (33) is turned on during the period T ₂ . Then, since the transistor (35) of the differential amplifier circuit ( 34 ) is turned on and the transistor (36) is turned off, bias is not applied to the transistors (12) and (13), and the amplifier circuit (15) does not operate. It becomes a state. Therefore, the CTL head (9) and the CTL signal recording circuit (3
The signal from 2) is not transmitted to the output terminal (16) of the amplifier circuit (15), and the DC potential of the output terminal (16) is regulated by the voltage of the power supply (17). Therefore, the output terminal (1
The DC potential of 6) can be kept constant regardless of the CTL signal reading period T ₁ and the cueing signal writing period T ₂ . To write the cue signal, use the CTL signal recording circuit (3
2). The CTL signal recording circuit (32)
Is a recording current C that causes the CTL track to become the N pole in response to the rising edge of the second timing pulse P _{2 in} FIG.
Supply to TL head (9). The third view (Li) Third falling subsequent timing pulse P ₃ of the CTL track recording current such that S pole is supplied to the CTL head (9). Therefore, the CTL track has a magnetization pattern as shown in FIG.

Therefore, according to the circuit of FIG. 1, the CTL signal can be accurately detected without being affected by the switching noise and the cue signal can be rerecorded.

By the way, although the case where the offset current of the amplifier circuit (15) is zero has been described in the above-described embodiment, in reality, even if an equal voltage is applied to the bases of the transistors (12) and (13), equal current does not flow. That is, the amplifier circuit (15)
The DC level of the output terminal (16) when the device is operating differs from the DC level of the output terminal (16) when the device is not operating. When the change is amplified by the operational amplifier (19), the reproduced CTL signal is level-shifted, and in extreme cases, the CTL signal may not be detected. Therefore, according to the present invention, the operational amplifier (19) is of variable gain type, the gain immediately after the operation of the amplifier circuit (15) is small, and the gain is large during the CTL signal reading period. Then, the change caused by the offset current is
The level is relatively negligible compared to the level of the CTL signal, and the level shift can be virtually zero. The state will be described with reference to FIG.
Now, when the amplifier circuit (15) of FIG. 1 is in a biased state, the transistor (13) is compared with the collector current of the transistor (12).
It is assumed that the collector current of is large. Then, the CTL signal appearing at the output terminal (16) of the amplifier circuit (15) becomes the third signal.
As shown in the figure (l), the DC level of the recorded CTL signal in the reading period T ₁ becomes smaller than the DC level of the cue signal writing period T ₂ . When the first timing pulse P _{1 of} FIG. 3 (d) is applied to the second timing pulse generation circuit (26) at the time of rewriting the cue signal, the output terminal of the AND gate (28) is shown in FIG. An output signal such as (g) is generated and applied to the base of the transistor (42) via the inverter (41). Then, in the period T ₃ in FIG. 3 (g), the transistor (43) and (44) is turned on,
One end of the capacitor (23) is connected to the power supply (17). The gain G ₁ of the operational amplifier (19) at this time is And the gain G ₁ is usually set to about 50 to 60 dB. Therefore, the CTL signal can be amplified at a very large level.

Next, in the period T ₄ of FIG. 3 (g), the transistors (43) and (44) are turned off, one end of the capacitor (23) is opened, and the gain G ₂ of the operational amplifier (19) is G ₂ = 1 ... (2) The change caused by the level shift of the direct current at the times t ₁ and t ₂ can be passed through as it is.

As a result, the output terminal of the operational amplifier (19) is shown in FIG.
As described above, a CTL signal amplified to a large level without level shift can be obtained.

In the embodiment of FIG. 1, the switching timing of the gain control means (31) (FIG. 3 (g)) is made narrower than that of the signal of FIG. 3 (f), so that it is stable against circuit variations. However, in the case of an ideal circuit, the signal of FIG. 3 (g) may be the same as the signal of FIG. 3 (f).

(G) Effect of the Invention As described above, according to the present invention, the DC level of the output terminal of the amplification circuit for amplifying the CTL signal can be kept at a constant level regardless of whether the CTL signal is read or written. Therefore, the CTL signal can be accurately detected without being erroneously detected. Further, according to the present invention, the switching operation between recording and reproduction is performed depending on whether or not the bias is applied to the amplifier circuit, so that the switching means is entirely formed of bipolar transistors without requiring the switch of the MOS transistor. I can.

Furthermore, according to the present invention, a variable gain amplifier circuit is provided in the subsequent stage of the amplifier circuit, and when the operation of the amplifier circuit is started or stopped,
Since the gain of the variable gain amplifier circuit is set small,
Even if an amplifier circuit having an offset is used, it is possible to prevent the DC level fluctuation of the output signal and prevent erroneous discrimination of the CTL signal.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram showing a conventional control signal head amplifier, and FIG. 3 is a waveform diagram for explaining FIG. (9) …… CTL head, (10) to (13) …… transistor, ( 14 ) …… current mirror circuit, (15) …… amplifier circuit, (16) …… output terminal, (17) …… power supply , (18) ……
Resistance, (19) …… Op Amp, ( 20 ) …… Feedback circuit,
(24) …… waveform shaping circuit, (25) …… first timing pulse generation circuit, (26) …… second timing pulse generation circuit, ( 30 ) …… bias supply circuit, (31) …… gain control means , (32) CTL signal recording circuit.

Claims (2)

[Claims] 1. A control head for detecting a control signal from a video tape, a current output type amplifying circuit for amplifying a control signal from the control head, and a bias to the amplifying circuit according to a read / write pulse. A bias supply circuit, a power supply for supplying a voltage to the output terminal of the amplifier circuit via a resistor, and a read / write pulse for generating the read / write pulse having a predetermined duty according to a signal from the output terminal of the amplifier circuit. A head amplifier for a control signal, characterized in that a control circuit having a constant DC level is obtained from an output terminal of the amplifier circuit. 2. The variable gain amplifier circuit according to claim 1, wherein a variable gain amplifier circuit for amplifying a signal from the output terminal of the amplifier circuit is provided.
2. The control signal head amplifier according to claim 1, wherein the gain of the variable gain amplifier circuit is switched according to a read / write pulse.