JPH077364B2 - Address translation buffer control method - Google Patents

Description

The present invention relates to an information processing device address translation buffer control system, and more particularly to a process for invalidating an entry for a specified real address in an address translation buffer (hereinafter referred to as partial. (Referred to as a purging process).

[Conventional technology]

Conventionally, the invalidation of the entry corresponding to the designated real address in the address translation buffer is disclosed in Japanese Patent Laid-Open No. 57-16428
As described in Japanese Patent Publication No. JP-A-2003-264, there is known a method in which the contents of the memory are read one by one and compared with the corresponding real address, and if a match is detected, the entry in which the match is detected is invalidated.

Furthermore, in JP-A-60-138654, a memory structure that can simultaneously refer to a plurality of TLB entries is adopted, a plurality of entries can be read at the same time, and a comparison circuit corresponding to the number of read entries is provided. Speeding up is achieved by parallelizing the comparison process. For example, if 1 TLB entry is referenced at the same time, the time required for TLB read / comparison is smaller than that for 1 entry read / comparison.
It is 1 / l time. When a match is detected in one or more of the l entries that are compared at the same time, the invalidation process is activated and the entire l entry is invalidated.

[Problems to be solved by the invention]

The method of invalidating the entire l entry when there is an entry that matches the real address in the read l entries can achieve a reduction in invalidation time, but invalidates even valid entries that are not the target of invalidation excessively. There is a problem that ends up.

An object of the present invention is to speed up processing by parallel comparison of a plurality of entries and improve the accuracy of entry invalidation.

[Means for solving problems]

One column in the address translation buffer (1 is an integer 1 ≧ 2)
When m entries (m is an integer of m ≧ 2) are used to invalidate the entry for the specified real address, the contents of the entries (m entries) in the same column of the m memories are read simultaneously. When the number of entries for which a match is detected by comparison with the corresponding real address is not smaller than a predetermined value n (n is an integer of 2 ≦ n ≦ m), the entire entries of the same column of the m memories are Invalidate, and if less than n, then m
Only the matching entry among the entries in the same column of each memory is invalidated.

[Action]

In the invalidation process of the address translation buffer, when the number (p) of entries in which a match is detected is smaller than a predetermined value n, the matched entries are invalidated one by one. At this time, p cycles are required for invalidation, only the entries that should be truly invalidated are invalidated, and excessive invalidation is not performed.

On the other hand, when the number p of entries for which a match is detected is not smaller than n, all the compared entries are invalidated. At this time,
Invalidation processing is performed in one cycle, and excessive invalidation is performed for (m−p) entries even though they are not targets of invalidation. The former case improves the precision of invalidation, and the latter case shortens the invalidation processing time.
Each has an emphasis. By appropriately setting the value of n, it is possible to optimize the invalidation time and accuracy as a whole.

〔Example〕

An embodiment of the present invention will be described below. FIG. 1 is a block diagram of an embodiment. For the sake of convenience, FIG. 1 shows an address conversion buffer having eight structures of a 64-column memory. The same applies when the number of columns and the number of memories are different and when there are several rows. In FIG. 1, 1 is a logical address register (LAR), 2 is a comparison address register (CAR), 3 is an address translation buffer (TLB), and the logical address and the real address are represented by byte and bit (0, 1) ~ (3,
It is assumed to consist of 31 bits in 7). 1 byte is 8
For example, (0,1) means the first bit of 0 byte, and (3,7) means the seventh bit of 3 bytes. The TLB 3 is composed of 64-column memories 4-11 and comparison circuits 12-19. Each 64-column memory has logical addresses (1,6) to (2,
3) is referred to as an address. 64-column memory 4-1
1 has an entry corresponding to each column, and each entry has a logical address field (bits (0,1) to (1,
3)) and the real address field (bits (0,1) to (2,
3)) and the V field. Other fields, eg segment table origin STO, change (C)
The bits are omitted because they are not directly related to the present invention.

FIG. 2 shows the substrate operation during TLB writing. WE (W
rite Enable) When the input is '1', write operation is performed. There are the following two write modes.

(1) Specified 1 out of 8 64-column memories
A mode in which writing is performed for each piece (selective writing mode).

(2) Mode in which data is written to all eight 64 column memories (all write mode). FS (Full Selec
t) When the input is '0', the selective write mode is selected and C
The column memory to be written is designated by S <0-2> (Column Select). When the FS input is 1 ', the full write mode is selected and writing is done to all 64 column memories. The following four processes are performed on TLB3.

1, read.

2. Entry registration at address conversion.

3, all purge processing.

4. Partial purge processing.

Only the partial purge process that is particularly relevant to the present invention will be described below. Prior to starting the operation of the partial purge process, a real address for designating an entry to be invalidated is set in the comparison address register 2 as an initial value. When the partial purge process is activated, the values of the logical addresses (1,6) to (2,3) are sequentially incremented to 0 to 63 by, for example, the purge control means, and the entries of the 64 column memories 4 to 11 are columnized. 0 to 63 are read in order and the real address of each entry is compared with the real address of the comparison address register 2 by the comparison circuits 12 to 19, respectively. The comparison results of the comparison circuits 12 to 19 are transmitted to the coincidence entry number detection circuit 21 and the coincidence 64 column memory number holding register 24. When the coincidence entry number detection circuit 21 detects a coincidence, the logical address stepping operation is suspended. 8-entry invalid register when the value of the matching entry number detection circuit 21 is not smaller than a predetermined value n
Set 22 to '1'. The TLB invalidation processing control circuit 25 sends a signal for invalidating 8 entries to the write control circuit 27. The write control circuit 27 receives this signal and sets FS to "1" to TLB3.
The 8 entry V fields are set to "0" and invalidated. When the value of the matching entry number detection circuit 21 is smaller than the value n given in advance, the 1-entry invalid register 23 is set to "1". TL
The B invalidation processing control circuit 25 transmits a signal for invalidating each entry to the write control circuit 27 and the 64-column memory number selection circuit 26. The 64-column memory number selection circuit 26 uses the value of the coincident 64-column memory number holding register 24 to determine the second
Determine the value of CS (0-2) as shown in the figure, and write control circuit 27
Tell. The write control circuit 27 is the TLB invalidation processing control circuit 2
In response to the signals from the 5th and 64th column memory number selection circuits 26, FS is '0', WE is '1', CS (0-
1) of TLB3 by specifying 2) to correspond to the memory number.
The V field of the entry is set to "0" and invalidated. n is 3
If the value is above, repeat this procedure to invalidate other entries. After the invalidation of all the entries for which a match is detected in this way is completed, the logical address stepping operation is reunited and the search operation of the subsequent columns of the 64-column memories 4 to 11 is continued. In this way, the search of 0 to 63 columns of the 64 column memories 4 to 11 is completed at the same time, and the partial purge process of the TLB entry including the predetermined real address is completed.

〔The invention's effect〕

According to the present invention, the TLB partial purge execution time and accuracy are optimized, and the overhead of the computer system due to the partial purge can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is
It is a figure explaining the basic operation at the time of TLB writing. 1 ... Logical address register (LAR), 2 ... Comparison address register (CAR), 3 ... Address conversion buffer (TLB), 4-11 ... 64 column memories 0-7, 12-19 ... Comparison circuit, 20 …… Write address register, 21 …… Matched entry number detection circuit, 25 …… TLB invalidation processing control circuit, 27 …… Write control circuit.

Continuation of front page (56) Reference JP-A-56-107377 (JP, A) JP-A-56-80869 (JP, A) JP-A-60-142451JP, A) JP-A-63-269242 (JP, A) )

Claims (1)

[Claims] 1. An address translation buffer for registering at least a translation pair of a virtual address and a real address. When referring to a main memory device, it is checked whether or not the corresponding virtual address is registered in the address translation buffer. In an information processing device for obtaining a target real address, a specified real address is used by using one column (1 is an integer of 1 ≧ 2) of m memories (m is an integer of m ≧ 2) in the address translation buffer. When invalidating the entry for, the contents of the entries (m) in the same column of the m memory are read at the same time and compared with the corresponding real address, and the number of entries in which a match is detected is given by a predetermined value n ( When n is not smaller than 2≤n≤m), the entire entry of the same column of the m memories is invalidated, and when smaller than n, the same color of the m memories is invalidated. Address conversion buffer controlling method characterized by matching only invalidate entries of the entries.