JPH0775414B2 - Disc playback demodulator - Google Patents

Description

TECHNICAL FIELD The present invention relates to a video disc reproducing apparatus for reproducing and demodulating a high-definition (high-definition television) band-compressed signal.

Conventional technology High-definition video signals that produce higher definition images than the current standard TV system
A band compression transmission method called MUSE that uses one channel of MHz bandwidth has been proposed (for example, Reference (1): Yuichi Ninomiya, "Transmission method of high-definition broadcasting using satellite MUSE", Nikkei Electronics, 1987 11
May 2, NO.433, P.189-P.212).

The transmission method shown here is for compressing and transmitting a high-definition signal originally having a band of 20 MHz or more to about 8 MHz by sub-Nyquist sampling, which is useful not only for satellite broadcasting but also for recording and reproducing. Applications to VTRs, video discs, etc. are being considered.

Especially with regard to video discs, high-definition, high-definition, wide and powerful images can be enjoyed easily even in ordinary households, and thus it can be expected to spread quickly. The major difference between this MUSE type video disc and that of the current television system is that the sync signal cannot be easily separated from the reproduced signal in amplitude because the sync signal is positive polarity synchronization. Therefore, disc rotation control with jitter and other time axis fluctuations, etc. That is, the synchronization signal cannot be easily separated and used. Therefore, it has been proposed that a pilot carrier signal is multiplexed with a television FM signal and recorded on a disc, and the pilot carrier signal is detected and used at the time of reproduction to control the rotation of the disc or the like (reference (2)). : Yuichi Ninomiya et al., "Home video disk by MUSE method", Technical Report of the Television Society of Japan, method circuit study group, TEBS99-4, September 20, 1984).

As described in Reference (2) above, since the MUSE method is a method that is realized by sub-Nyquist sampling, if the reproduced signal has time-axis fluctuations, that is, jitter, the resample phase shifts and the original signal is restored. Jitter correction is necessary because it cannot be done. From the viewpoint of reproduced signal quality, it is effective to use a digital time base collector (hereinafter abbreviated as TBC) for this jitter correction.

Problems to be Solved by the Invention Since a MUSE-type television signal has a band of 8 MHz or more, generally, in order to perform analog-digital conversion (hereinafter abbreviated as A / D conversion) without impairing the reproduction signal, At least 24M
A sampling clock of Hz or higher is required. However, at such a frequency, there is a problem that a normal TTL logic IC is almost near the performance limit, and a high-speed type IC consumes a large amount of power.

Therefore, MUSE sampling clock 16.2MHz
It is conceivable to resample at a frequency of, but in this case, in order to faithfully A / D convert an analog signal having a band of 8.1 MHz, it accurately follows the input video signal with jitter. , And the sampling clock of the optimum phase must be used. Therefore, the above-mentioned reference (2)
While making a resampling clock using the pilot carrier signal in the disc playback signal shown in,
Sampling phase detection and phase shift operation are required separately.

By the way, when recording a video disk MUSE signal and a pilot carrier signal synchronized with the video disk MUSE signal, the phase difference of the pilot carrier with respect to the MUSE synchronization signal is not specified and may differ depending on the disk. However, the phase difference between both signals recorded continuously is constant and does not change. Therefore, it is desirable that the phase control of the resampling clock be stabilized at a constant value after being quickly pulled to the optimum phase. However, in the conventional technique, there are unstable factors such as a temporary error in the phase control circuit caused by dropout or noise during the reproduction of the disc, and the clock phase always fluctuating even after the pulling in.

In view of the above point, the present invention has an object to provide a disk reproducing / demodulating device having a clock phase shift circuit capable of performing ideal resampling clock phase control.

Means for Solving the Problems In order to solve the above problems, the present invention provides a television FM
A disc reproducing device for reproducing a video disc on which a modulated signal, a pilot carrier and the like are recorded, a pilot carrier extracting circuit for extracting a pilot carrier from an output signal of the disc reproducing device, and a clock signal synchronized with the extracted pilot carrier For generating a phase-locked loop oscillator circuit, a transfer circuit for outputting a phase-shifted clock signal by switching the delay time of the clock signal by an address signal, and a reproduction FM from the output signal of the disk reproducing device. An FM-demodulation circuit that demodulates a signal, an analog-digital conversion circuit that converts the television signal demodulated by the FM demodulation circuit into a digital signal using the phase-shifted clock signal, and the analog-digital conversion circuit. Time axis of digital television signal A time base collector circuit that absorbs motion, a sync signal detection circuit that detects a sync signal in the analog-digital converted signal, and sampling of an analog-digital conversion circuit based on the sync signal detected by the sync signal detection circuit A phase error detection circuit that detects a phase shift, a comparison circuit that outputs an out-of-phase signal only when the absolute value of the output of the phase error detection circuit is larger than a set value, and a setting in which the out-of-phase signal is within a certain period A counter that outputs an enable signal when detected more than the number of times, and an address signal by an up-down counter that controls up-down by the sign of the output of the phase error detection circuit and enables the counting operation of the synchronization signal by the enable signal. And an address generation circuit for outputting

The disk reproducing and demodulating device according to the present invention is constituted by the above means.
The control signal of the up-down counter is generated by adapting to the advance or delay of the detected sampling phase and the degree of pull-in.
By switching a plurality of clocks of different phases by the selector controlled by the counter output and supplying the clocks to the A / D conversion circuit, the sampling is always performed stably at the optimum phase.

Embodiment Hereinafter, the configuration and operation of a specific embodiment of the present invention will be described with reference to the drawings.

In FIG. 1, 1 is a disc reproducing device for reproducing an FM signal or the like from a video disc by a pickup, 2 is an FM demodulation circuit for demodulating the reproduced FM signal into an original video signal, 3
Is an A / D conversion circuit that converts the demodulated analog video signal to a digital signal using the phase-shifted clock signal described below. 4 is a stable clock that writes the video signal with jitter to the memory using a clock synchronized with it. Get a TV signal without jitter by reading with TB
C and 5 are the television signals that are jitter-corrected, that is, MUSE
MUSE decoder that demodulates the signal to the original broadband HDTV signal, 6 is a pilot carrier extraction circuit that extracts the pilot carrier in the FM signal reproduced from the disc,
7 is a phase locked loop (PLL) oscillator circuit that generates a clock synchronized with the extracted pilot carrier,
8 is a sync signal detection circuit for detecting a vertical sync signal and a horizontal sync signal from the digitally converted MUSE signal, 9 is a resample phase of the A / D conversion circuit from the normal position using the detected horizontal sync signal Is a phase error detection circuit for calculating whether or not there is a shift, and 10 is a clock shifter for outputting a phase shift clock signal obtained by shifting the phase of the clock signal obtained by the PLL oscillation circuit 7 to the optimum position by the output signal of the phase error detection circuit. It is a phase circuit.

A clock with a jittered video signal and its time-axis fluctuation completely matched is obtained by the PLL oscillation circuit 7, but the clock phase shift circuit 10 absorbs the phase difference between the pilot carrier and the video signal determined when the disc was created. Then, the phase of the resampling clock in the A / D conversion circuit is moved to the optimum value.

Next, FIG. 2 shows the principle of detecting the resample phase from the horizontal synchronizing signal. For details, refer to the above-mentioned reference (1) and Japanese Patent Laid-Open No. Sho 59-221091 "Clock phase lock system".
Therefore, only the parts necessary for the present invention will be described here. In the figure, 11 is a part of the waveform of the horizontal synchronizing signal, and its polarity is actually inverted every scanning line. The circles on the horizontal sync signal indicate the regular resampling positions, of which the values 12, 13, and 14 are used for the actual calculation. Letting each sample value be D1, D2, D3, the lead / lag of the resample phase can be judged depending on whether the value calculated by (D1 + D3) / 2-D2 is positive or negative, and the amount of deviation can be determined by the absolute value. I understand. This is input to the clock phase circuit as phase error data.

Next, a concrete description of the clock phase circuit will be given with reference to FIG. In the figure, 15 is an input terminal for phase error data,
Reference numeral 16 is a code component of the phase error data, and 17 is an absolute value component of the phase error data. Reference numeral 18 denotes a comparison circuit for comparing the absolute value 17 with a preset allowable value, which discriminates whether or not the sampling phase is out of the allowable range, and outputs the out-of-phase signal 19. 20 is a counter that outputs an enable signal 21 that enables the up / down counter 22 described later only when the out-of-phase signal 19 is detected more than a set number of times within a certain period, and the out-of-phase signal 19 truly exceeds the allowable value. The up / down counter 22 to be described later is distinguished by distinguishing whether it is output due to out-of-phase or whether it is temporarily output due to incorrect phase error data due to an error in phase error detection due to dropout or noise. It has a role to control.

Reference numeral 22 denotes an up / down counter whose up / down is controlled by the code 16 of the phase error data and which is controlled by the enable signal 21 from the counter 18 to count or not the synchronization signal as the operation clock. Address signal 23. For example, if the sign of the phase error data is negative and the phase of the sampling clock in the A / D conversion circuit is delayed, the count of the clock phase is incremented or decremented.

When the circuit is actually constructed, the phase error data is calculated in the same cycle as the horizontal synchronizing signal. Therefore, the operating clocks of the counter 20 and the up / down counter 22 have an appropriate horizontal synchronizing frequency. As a period for monitoring the number of times, an integer multiple of the vertical synchronization cycle is suitable.

25 is the input terminal of the clock signal obtained by the PLL oscillator circuit, 2
A minute delay element (delay time t) 6 is connected in series by the number of stages necessary to obtain a plurality of clock phases.
For MUSE signal, the sampling clock frequency is 16.2MH
Therefore, if the precision of the controlled phase is set to 2 nsec or more and t is set to 1.93 nsec, all phases can be obtained in a 32-stage configuration, and the address signal becomes 5 bits. 24 is a selector, which receives the clock from each connection point of the delay elements 26 connected in series, selects one corresponding to the address signal 23 from among these various clocks, and resamples the A / D conversion. According to the disc reproducing / demodulating device of the present invention, the phase shift clock having the optimum phase is used to configure the digital TBC by A / D converting the transmission sampling clock of 16.2 MHz in the pilot carrier recording system MUSE video disc. , A / D conversion can always be performed with the optimum sampling phase even when playing a disc in which the phase difference between the video signal and the pilot carrier is not specified. Moreover, even if a temporary error occurs in the phase error detection due to a disturbance such as dropout or noise, the clock phase shift circuit does not perform the clock phase shift operation separately from the case where the sampling phase is actually shifted. It is possible to minimize the fluctuation of the generated clock. As a result, the synchronized reproduction becomes very stable, and there is an advantage that the resolution is temporarily reduced and the screen is not disturbed, and the quality of the reproduced image is greatly improved.

[Brief description of drawings]

FIG. 1 is a block diagram of a disc reproducing / demodulating device according to an embodiment of the present invention, FIG. 2 is a waveform diagram for explaining a horizontal synchronizing signal and a resample position of a MUSE signal, and FIG. 3 is a clock in the disc reproducing / demodulating device. It is a block diagram of a phase shift circuit. 1 ... Disk playback device, 3 ... A / D conversion circuit, 6 ...
Pilot carrier extraction circuit, 7 ... PLL oscillation circuit, 8
...... Synchronization signal detection circuit, 9 …… Phase error detection circuit, 10 ・ ・ ・
… Clock phase shift circuit, 18 …… Comparison circuit, 20 …… Counter, 22 …… Up / down counter, 24 …… Selector, 26
...... Minute delay element.

Claims (1)

[Claims] 1. A disc reproducing apparatus for reproducing a video disc on which a television FM modulation signal, a pilot carrier and the like are recorded, a pilot carrier extracting circuit for extracting a pilot carrier from an output signal of the disc reproducing apparatus, and the extracted circuit. A clock generation circuit configured by a phase locked loop oscillation circuit for generating a clock signal synchronized with the pilot carrier; a phase shift circuit for switching a delay time of the clock signal by an address signal to output a phase shift clock signal; An FM demodulation circuit for demodulating a reproduced FM signal from an output signal of the disc reproducing device;
Analog that converts the television signal demodulated by the FM demodulation circuit into a digital signal using the phase shift clock signal
A digital conversion circuit, a time base collector circuit that absorbs a time base fluctuation of the digital television signal converted by the analog-digital conversion circuit, and the analog-
A synchronization signal detection circuit for detecting a synchronization signal in the digitally converted signal; a phase error detection circuit for detecting a deviation of the sampling phase of the analog-digital conversion circuit from the synchronization signal detected by the synchronization signal detection circuit; A comparator circuit that outputs an out-of-phase signal only when the absolute value of the output of the phase error detection circuit is larger than a set value, and a counter that outputs an enable signal when the out-of-phase signal is detected for a set number of times within a certain period. An address generation circuit that outputs the address signal by an up / down counter that controls up / down by the sign of the output of the phase error detection circuit and enables the counting operation of the synchronization signal by the enable signal. And a disc playback demodulator.