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JPH077786B2 - Method for manufacturing semiconductor device - Google Patents
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JPH077786B2 - Method for manufacturing semiconductor device - Google Patents

Method for manufacturing semiconductor device

Info

Publication number
JPH077786B2
JPH077786B2 JP60088529A JP8852985A JPH077786B2 JP H077786 B2 JPH077786 B2 JP H077786B2 JP 60088529 A JP60088529 A JP 60088529A JP 8852985 A JP8852985 A JP 8852985A JP H077786 B2 JPH077786 B2 JP H077786B2
Authority
JP
Japan
Prior art keywords
substrate
substrates
capacitance
main surface
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60088529A
Other languages
Japanese (ja)
Other versions
JPS61248435A (en
Inventor
夏樹 横山
喜夫 本間
高 西田
助芳 恒川
浩 森崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP60088529A priority Critical patent/JPH077786B2/en
Publication of JPS61248435A publication Critical patent/JPS61248435A/en
Publication of JPH077786B2 publication Critical patent/JPH077786B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10PGENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P74/00Testing or measuring during manufacture or treatment of wafers, substrates or devices

Landscapes

  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の製造方法に係り、特に、所定の
配線または素子を備えた複数個の基板間の相対的位置を
定めるに好適な方法に関する。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and in particular, is suitable for determining a relative position between a plurality of substrates provided with predetermined wirings or elements. Regarding the method.

〔発明の背景〕[Background of the Invention]

半導体装置の集積密度の増大に対応し、その多機能化,
高性能化を図るためには、配線の多層化が必要であり、
将来的には、数十層の配線層形成が必要となるとさえ言
われている。このような多層配線を、素子を形成した基
板上に下層から順次形成する方法で作製することは、工
程数の増加に伴う良品率の低下と、いわゆるターン・ア
ラウンド時間の増加の点から極めて非能率的であり、コ
スト高につながる。このような工程数の増加に起因する
弊害は、ウエハ規模集積回路製造の妨げとなり、また、
3次元集積回路製造においても、多層配線集積回路製造
と同様にもたらされる。かかる従来法の欠点を取除くた
め、所定の配線または素子を備えた基板を複数個独立に
作製し、しかる後、該複数個の基板を接着一体化して半
導体装置を製造するという方法がある。この方法におい
て問題となるのは、複数個の基板間の相対的位置関係を
いかにして定めるかという点である。かかる相対的位置
関係を定める方法としては、従来の製造方法において実
施されている、露光マスクと基板との位置合せ法がある
が、この方法は、対象とする複数個の基板のいずれもが
光を透過する部分を有しない場合には適用できない。
In response to the increase in the integration density of semiconductor devices, its multifunctionalization,
In order to achieve high performance, it is necessary to have multiple layers of wiring,
It is said that it will be necessary to form several tens of wiring layers in the future. Fabrication of such a multilayer wiring by a method of sequentially forming from the lower layer on the substrate on which the element is formed is extremely non-defective in terms of a decrease in non-defective product rate due to an increase in the number of steps and an increase in so-called turn around time. Efficient and costly. The adverse effects resulting from such an increase in the number of steps hinder the manufacture of wafer-scale integrated circuits, and
The same applies to the manufacture of a three-dimensional integrated circuit as the manufacture of a multilayer wiring integrated circuit. In order to eliminate the drawbacks of the conventional method, there is a method of independently manufacturing a plurality of substrates provided with predetermined wirings or elements, and then bonding and integrating the plurality of substrates to manufacture a semiconductor device. The problem with this method is how to determine the relative positional relationship between a plurality of substrates. As a method of determining such a relative positional relationship, there is a method of aligning an exposure mask and a substrate, which is carried out in a conventional manufacturing method. In this method, all of a plurality of target substrates are exposed to light. This is not applicable when there is no part that transmits

〔発明の目的〕[Object of the Invention]

本発明の目的は、上記従来の問題を解決し、所定の配線
または素子を備えた複数個の基板間の相対的位置関係を
定めることのできる半導体装置の墳造方法を提供するこ
とにある。
SUMMARY OF THE INVENTION It is an object of the present invention to provide a method for manufacturing a semiconductor device, which can solve the above-mentioned conventional problems and can determine the relative positional relationship between a plurality of substrates provided with predetermined wirings or elements.

〔発明の概要〕[Outline of Invention]

上記目的を達成するため、本発明は、容量測定用電極
を、所定の配線または素子を備えた複数個の基板上に、
各々少なくとも1つずつ作製し、該電極のうち少なくと
も2つが相対するように該複数個の基板を配置し、該電
極間の容量または該電極間の相対的位置関係の変化によ
る容量変化を測定することにより、該基板間相互の相対
的位置関係の決定を可能とするものである。該複数個の
基板を配列(配列とは、いずれか1つの基板主表面に平
行な向きの複数個の基板間の相対的位置関係を固定した
状態を言う)させた後に、該複数個の基板間の距離を調
整することまたは該複数個の基板を重ね合わせることも
可能とした。
In order to achieve the above object, the present invention provides a capacitance measuring electrode on a plurality of substrates provided with predetermined wirings or elements,
At least one is prepared for each, the plurality of substrates are arranged so that at least two of the electrodes face each other, and the capacitance change due to the change in the capacitance between the electrodes or the relative positional relationship between the electrodes is measured. This makes it possible to determine the relative positional relationship between the substrates. After arranging the plurality of substrates (an array means a state in which a relative positional relationship between the plurality of substrates in a direction parallel to any one main surface of the substrates is fixed), the plurality of substrates is arranged. It is also possible to adjust the distance between them or stack the plurality of substrates.

〔発明の実施例〕Example of Invention

以下、本発明を、実施例を参照して詳細に説明する。 Hereinafter, the present invention will be described in detail with reference to examples.

実施例1 第1図を用いて説明する。第1図(a)は、本発明に用
いる容量測定用電極を備えた基板を示す。電極数はいく
つでもよいが、ここでは、40である。図において、記号
1は所定の配線または素子を備えた基板、2〜5は容量
測定用電極、6は複数個の基板を接着一体化し、電気的
導通をとるための接着用電極をそれぞれ表わす。容量測
定用電極2〜5の大きさは、各々、1μm×5cmであ
り、10個ずつが間隔1μmで並んでいる。形は、ここで
は長方形であるが、他の形でも構わないのは言うまでも
ない。基板1としては、所定の配線と素子を備えた半導
体基板と、所定の配線を備えた絶縁物基板を用い、容量
測定用電極2〜5は、両基板1を向い合わせたときに相
対するように、それぞれの上に配置されている。容量測
定用電極2〜5と、接着用電極6との間の、各々の基板
上での相対的位置関係は確定していて、2つの基板1上
の容量測定用電極2〜5の相対的位置関係を定めると、
2つの基板1上の接着用電極6相互間の位置関係も定ま
る。第1図(a)に示したような半導体基板1と絶縁物
基板1を1つずつ、第1図(b)の如く平行に向い合わ
せる。絶縁物基板21は固定されていて、半導体基板31は
可動台41上に設置されている。少なくともいずれか一方
の基板が可能であればよい。該両基板21,31間の距離
は、10μmである。容量測定用電極22と32,24と34によ
つてそれぞれ形成される蓄電器を並列に接続し、その総
合量を容量計42により測定する。可動台41を容量測定用
電極32の長辺に垂直な方向に移動しながら容量を測定し
た結果を第1図(c)に示す。横軸は容量最大の点から
のずれを示す。この移動方向と垂直な移動方法について
も、同様の方法により、同様の結果が得られた。用いた
容量計42の測定精度が0.3pFであることから決まる本実
施例における両基板21,31間の相対的位置関係の決定精
度は、±0.3μmであつた。なお、2組の蓄電器を並列
に接続することは必ずしも必要ではなく、また、3組以
上を接続してもよい。
Example 1 will be described with reference to FIG. FIG. 1 (a) shows a substrate provided with a capacitance measuring electrode used in the present invention. The number of electrodes is arbitrary, but here, it is 40. In the figure, reference numeral 1 represents a substrate provided with a predetermined wiring or element, 2 to 5 represent capacitance measuring electrodes, and 6 represents an adhesive electrode for adhesively integrating a plurality of substrates to establish electrical conduction. The capacitance measuring electrodes 2 to 5 each have a size of 1 μm × 5 cm, and 10 electrodes are arranged at intervals of 1 μm. The shape is rectangular here, but it goes without saying that other shapes may be used. As the substrate 1, a semiconductor substrate having predetermined wirings and elements and an insulating substrate having predetermined wirings are used, and the capacitance measuring electrodes 2 to 5 face each other when the both substrates 1 face each other. Are placed on top of each. The relative positional relationship between the capacitance measuring electrodes 2 to 5 and the bonding electrode 6 on each substrate is fixed, and the relative capacitance relationship between the capacitance measuring electrodes 2 to 5 on the two substrates 1 is determined. If you define the positional relationship,
The positional relationship between the bonding electrodes 6 on the two substrates 1 is also determined. One semiconductor substrate 1 and one insulator substrate 1 as shown in FIG. 1A are faced in parallel as shown in FIG. 1B. The insulator substrate 21 is fixed, and the semiconductor substrate 31 is installed on the movable base 41. It is sufficient that at least one of the substrates is possible. The distance between the two substrates 21 and 31 is 10 μm. Capacitors formed by the capacitance measuring electrodes 22 and 32 and 24 and 34 are connected in parallel, and the total amount thereof is measured by the capacitance meter 42. The result of measuring the capacitance while moving the movable table 41 in the direction perpendicular to the long side of the capacitance measuring electrode 32 is shown in FIG. The horizontal axis shows the deviation from the maximum capacity point. Similar results were obtained by the same method for the moving method perpendicular to the moving direction. The determination accuracy of the relative positional relationship between the two substrates 21 and 31 in the present embodiment determined by the measurement accuracy of the used capacitance meter 42 being 0.3 pF was ± 0.3 μm. It is not always necessary to connect two sets of capacitors in parallel, and three or more sets may be connected.

実施例2 第2図を用いて説明する。本実施例は、実施例1と同様
の工程の後、両基板21,31を重ね合わせた例を示す。実
施例2で用いた可動台41は、該両基板21,31を配列させ
た後に、該両基板21,31間の距離を調整するまたは該両
基板21,31を重ね合わせる機能を有する。実施例1の如
く、2つの基板21,31を配列させた後、可動台41を半導
体基板31の主表面に垂直な方向に移動し、該両基板21,3
1を重ね合わせた。可動台41を基板31の主表面に垂直な
方向に動かす際に、基板主表面方向に±0.2μmの誤差
が生じるため、本実施例における最終的な該基板21,31
間の相対的位置関係の決定精度は、±0.5μmであつ
た。かかる工程の後、該両基板21,31を加熱圧着する
と、接着用電極26と36とが接着され、該両基板21,31は
一体化した。なお、該両基板21,31の一体化の方法とし
ては、他に、テープキヤリア方式等用いることも可能で
ある。
Example 2 will be described with reference to FIG. The present embodiment shows an example in which both substrates 21 and 31 are superposed after the process similar to that of the first embodiment. The movable base 41 used in the second embodiment has a function of arranging the both substrates 21 and 31 and then adjusting a distance between the both substrates 21 and 31, or superposing the both substrates 21 and 31. After arranging the two substrates 21 and 31 as in the first embodiment, the movable table 41 is moved in a direction perpendicular to the main surface of the semiconductor substrate 31, and the two substrates 21 and 3 are moved.
Stacked 1 When the movable table 41 is moved in the direction perpendicular to the main surface of the substrate 31, an error of ± 0.2 μm occurs in the direction of the main surface of the substrate.
The accuracy of determination of the relative positional relationship between them was ± 0.5 μm. After this step, when the substrates 21 and 31 are heated and pressure-bonded, the bonding electrodes 26 and 36 are bonded and the substrates 21 and 31 are integrated. As a method of integrating the two substrates 21 and 31, it is also possible to use a tape carrier method or the like.

実施例3 第3図を用いて説明する。本実施例3は、実施例1と同
様の基板21,31を用い、第3図(a)に示す如く、容量
計42の出力に2次微分回路43を接続し、2つの基板21,3
1上の容量測定用電極22と24,32と34間の容量そのもので
はなく、可動台41の移動による容量変化のピーク検出を
行つて、該両基板21,31間の相対的位置関係の決定を行
つた実施例である。第3図(b)は2次微分回路43の出
力の一例を示す。横軸は、容量最大に対応するピークの
中心からのずれを表す。2次微分回路43を付与すること
によつて、本実施例における該両基板21,31間の相対的
位置の決定精度は、±0.15μmとなつた。
Example 3 will be described with reference to FIG. In the third embodiment, the same substrates 21 and 31 as in the first embodiment are used, and as shown in FIG. 3A, the output of the capacitance meter 42 is connected to the secondary differentiating circuit 43, and the two substrates 21 and 3 are connected.
Not the capacitance itself between the capacitance measuring electrodes 22 and 24, 32 and 34 on 1 but the peak of the capacitance change due to the movement of the movable base 41 is detected to determine the relative positional relationship between the two substrates 21 and 31. This is an example of the above. FIG. 3B shows an example of the output of the secondary differentiating circuit 43. The horizontal axis represents the deviation from the center of the peak corresponding to the maximum capacity. By providing the secondary differentiating circuit 43, the accuracy of determining the relative position between the substrates 21 and 31 in this embodiment is ± 0.15 μm.

実施例4 第1図を用いて説明する。本実施例は、実施例1と同様
の基板21,31を用い、実施例1と同様の容量計42を用い
て、該両基板21,31間の平行関係を精度よく定めた例で
ある。なお、本実施例においては、容量測定用電極22と
32,24と34の各組から成る蓄電器は並列接続せず、それ
ぞれ独立に容量を測定した。本実施例で用いた可動台41
は周辺部8ケ所にピツチの小さなねじから成る高さ調整
装置を具備していて、該両基板21,31の平行度を調整す
る機能を有する。各組の電極22と32,24と34から成る蓄
電器の容量が同どになるように可動台41を移動したとこ
ろ、該両基板21,31の相対する基板面の各位置における
該両基板21,31間の距離の差は、±0.4μmに収まつた。
Example 4 will be described with reference to FIG. This embodiment is an example in which the substrates 21 and 31 similar to those of the first embodiment are used, and the parallel relationship between the substrates 21 and 31 is accurately determined by using the same capacitance meter 42 as that of the first embodiment. In the present embodiment, the capacitance measuring electrode 22 and
The capacitors composed of each set of 32, 24 and 34 were not connected in parallel and the capacity was measured independently. Movable base 41 used in this embodiment
Is equipped with a height adjusting device composed of screws with small pitches at eight peripheral portions, and has a function of adjusting the parallelism between the two substrates 21 and 31. When the movable base 41 is moved so that the capacitors formed of the electrodes 22 and 32, 24 and 34 of each set have the same capacity, the two substrates 21 and 31 at the respective positions on the opposite substrate surfaces are opposed to each other. The difference in distance between the and 31 was within ± 0.4 μm.

〔発明の効果〕〔The invention's effect〕

本発明によれば、複数個の、配線または素子を備えた基
板間の相対的位置関係を精度よく定めることを可能とす
る効果がある。さらに、該複数個の基板間の距離を調整
すること、または、該複数個の基板を重ね合わせること
も可能となる。
According to the present invention, there is an effect that it is possible to accurately determine the relative positional relationship between a plurality of substrates provided with wirings or elements. Further, it becomes possible to adjust the distance between the plurality of substrates or to superpose the plurality of substrates.

【図面の簡単な説明】[Brief description of drawings]

第1図ないし第3図は、それぞれ本発明の異なる実施例
を説明するための図である。 1……所定の配線または素子を備えた基板、2〜5,22,2
4,32,34……容量測定用電極、6、26、36……接着用電
極、21……絶縁物基板、31……半導体基板、41……可動
台、42……容量計、43……2次微分回路。
1 to 3 are views for explaining different embodiments of the present invention. 1 ... Substrate with predetermined wiring or elements, 2-5,22,2
4,32,34 …… Capacity measuring electrodes, 6,26,36 …… Adhesive electrodes, 21 …… Insulator substrate, 31 …… Semiconductor substrate, 41 …… Movable platform, 42 …… Capacity meter, 43… … Second-order differentiation circuit.

───────────────────────────────────────────────────── フロントページの続き (72)発明者 恒川 助芳 東京都国分寺市東恋ヶ窪1丁目280番地 株式会社日立製作所中央研究所内 (72)発明者 森崎 浩 東京都国分寺市東恋ヶ窪1丁目280番地 株式会社日立製作所中央研究所内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Sukeyoshi Tsunekawa 1-280 Higashi Koigakubo, Kokubunji, Tokyo Inside Central Research Laboratory, Hitachi, Ltd. (72) Inventor Hiroshi Morisaki 1-280 Higashi Koigakubo, Kokubunji, Tokyo Hitachi Ltd. Central Research Laboratory

Claims (5)

【特許請求の範囲】[Claims] 【請求項1】それぞれの主表面に所定の配線または所定
の素子の少なくとも一方を備えた第1の基板と第2の基
板とを準備して、該第1の基板の主表面と該第2の基板
の主表面とを向い合わせた後、両者を接着一体化して半
導体装置を製造するに際して上記第1の基板と上記第2
の基板との間の相対的位置関係を測定するため、 上記第1の基板と上記第2の基板のそれぞれの主表面に
容量測定を可能とする電極を予め配置し、 該容量測定可能な電極の間の容量を測定することにより
上記相対的位置関係を測定することを特徴とする半導体
装置の製造方法。
1. A first substrate and a second substrate each having at least one of a predetermined wiring and a predetermined element on each main surface are prepared, and the main surface of the first substrate and the second substrate are prepared. After facing the main surface of the first substrate, the first substrate and the second substrate are bonded and integrated to manufacture a semiconductor device.
In order to measure the relative positional relationship between the first substrate and the second substrate, electrodes capable of measuring the capacitance are arranged in advance on the respective main surfaces of the first substrate and the second substrate, and the electrodes capable of measuring the capacitance are arranged. A method for manufacturing a semiconductor device, characterized in that the relative positional relationship is measured by measuring a capacitance between the two.
【請求項2】上記容量測定可能な電極の間の容量を測定
する容量測定手段の出力に従って上記第1の基板と上記
第2の基板との間の上記相対的位置関係を調整し、 しかる後、上記両者を接着一体化することを特徴とする
特許請求の範囲第1項に記載の半導体装置の製造方法。
2. The relative positional relationship between the first substrate and the second substrate is adjusted according to the output of a capacitance measuring means for measuring the capacitance between the capacitance-measurable electrodes, and thereafter, The method for manufacturing a semiconductor device according to claim 1, wherein the both are integrally bonded.
【請求項3】上記第1の基板と上記第2の基板のそれぞ
れの主表面に互いに対応する接続用電極が予め形成され
てなり、 上記両者を接着一体化するに際して、上記第1の基板の
主表面の該接続用電極と上記第2の基板の主表面の該接
続用電極とが互いに接続されることを特徴とする特許請
求の範囲第2項に記載の半導体装置の製造方法。
3. A connection electrode corresponding to each other is previously formed on the main surface of each of the first substrate and the second substrate. When the two are bonded and integrated, the first substrate The method for manufacturing a semiconductor device according to claim 2, wherein the connection electrode on the main surface and the connection electrode on the main surface of the second substrate are connected to each other.
【請求項4】上記両者を接着一体化するに際して、加熱
処理することにより上記第1の基板の主表面の上記接続
用電極と上記第2の基板の主表面の上記接続用電極とが
互いに接着されることを特徴とする特許請求の範囲第3
項に記載の半導体装置の製造方法。
4. The bonding electrode on the main surface of the first substrate and the connecting electrode on the main surface of the second substrate are bonded to each other by heat treatment when bonding and integrating both of them. Claim 3 characterized in that
A method of manufacturing a semiconductor device according to item.
【請求項5】上記第1の基板と上記第2の基板の一方は
半導体基板であることを特徴とする特許請求の範囲第1
項から第4項までのいずれかに記載の半導体装置の製造
方法。
5. The method according to claim 1, wherein one of the first substrate and the second substrate is a semiconductor substrate.
Item 5. A method for manufacturing a semiconductor device according to any one of items 4 to 4.
JP60088529A 1985-04-26 1985-04-26 Method for manufacturing semiconductor device Expired - Lifetime JPH077786B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP60088529A JPH077786B2 (en) 1985-04-26 1985-04-26 Method for manufacturing semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP60088529A JPH077786B2 (en) 1985-04-26 1985-04-26 Method for manufacturing semiconductor device

Publications (2)

Publication Number Publication Date
JPS61248435A JPS61248435A (en) 1986-11-05
JPH077786B2 true JPH077786B2 (en) 1995-01-30

Family

ID=13945362

Family Applications (1)

Application Number Title Priority Date Filing Date
JP60088529A Expired - Lifetime JPH077786B2 (en) 1985-04-26 1985-04-26 Method for manufacturing semiconductor device

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Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02278745A (en) * 1989-04-19 1990-11-15 Tokyo Electron Ltd Alignment device

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Publication number Publication date
JPS61248435A (en) 1986-11-05

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