JPH078044B2 - Digital convergence device - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital convergence correction device for a color television receiver.

2. Related Art FIG. 4 is a block diagram of a conventional example.

In FIG. 4, reference numeral 1 denotes a PLL circuit, which inputs a horizontal blanking signal to a terminal a and a vertical blanking signal to a terminal b from the deflection system of the display device. PLL circuit 1 above
Then, the blanking signal is phase-synchronized, and a reference clock that is multiplied by X in the horizontal direction and multiplied by Y in the vertical direction (X and Y are natural numbers) is output. The clock is input to the timing generation circuit 2 and outputs a crosshatch signal to the crosshatch generation circuit 3 and an address clock signal to the address generation circuit 4. The crosshatch generation circuit 3 outputs a crosshatch signal for displaying a crosshatch pattern as shown in FIG. 5 on the screen. The convergence correction point has an address on the screen as an intersection of this crosshatch pattern.

That is, the cross hatch pattern is divided into X equal parts in the horizontal direction and Y equal parts in the vertical direction. The address generation circuit 4 outputs the synchronous address to the terminal c of the address switching circuit 5. The synchronization address is synchronized with each horizontal and vertical blanking signal input to the PLL circuit 1. The address switching circuit 5 is composed of three terminals d and e in addition to the terminal c, and its switching operation is controlled by an address switching signal output from the control circuit 8. When the terminals c and e are currently ON as shown in FIG. 4, the synchronous address is guided to the frame memory 6. The digital correction data in the frame memory 6 respectively correspond to the correction points which are the intersections of the crosshatch shown in FIG. 5, and are sequentially read out as digital correction data in synchronization with the raster scan. The read digital correction data is input to the D / A conversion circuit 9, converted into an analog signal, smoothed by a low pass filter (hereinafter referred to as “LPE”) 10, and guided to the convergence correction coil as a convergence correction signal. , Convergence is corrected.

The control circuit 8 is a circuit using, for example, a microprocessor, and generates a control address signal to the terminal d of the address switching circuit 5 and the nonvolatile memory 7. At the same time, it has a bidirectional data bus for the frame memory 6 and the non-volatile memory 7. That is, when the address switching signal from the control circuit 8 turns on between the terminals d and e of the address switching circuit 5, the frame memory 6 is addressed by the control address signal, and the contents are changed through the data bus of the control circuit 8. As a result, proper convergence correction digital data can be obtained in the frame memory 6 through trial and error. If the address switching signal is changed at a timing such as a vertical blanking signal, the synchronous address and the control address signal are alternately switched to the frame memory 6, and the digital correction data is read from the frame memory 6 without being interrupted at the synchronous signal cycle. Will be done. When a series of operations for convergence correction is completed, when the terminals f and g of the write switch 11 connected to the control circuit 8 are turned on, the control circuit 8 sends an address switching signal again only during the vertical blanking period. The terminals d and e are output so as to be turned on, and the contents of the frame memory 6 are transferred and written to the nonvolatile memory 7 through the bidirectional data bus. By providing the nonvolatile memory 7 with a capacity N times as large as the data capacity of the frame memory 6, selective writing can be performed in N blocks using a memory selection signal from the control circuit 8. Conversely, when the power is turned off and then turned on again, the address switching signal turns on between the terminals d and e of the address switching circuit 5, and the control circuit 8 causes the nonvolatile memory 7 of the block selected by the memory selection signal. By transferring the contents to the frame memory 6 through the data bus, the digital correction data can be read again synchronously.

Although the red convergence correction 1 is performed as described above, the same operation is repeated for green and blue.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention In the write circuit of the conventional digital convergence correction device, the control circuit immediately recognizes the write operation by the operation of one write switch. Therefore, there is a drawback that if the write switch is mistakenly operated while the other switches are being operated, the write operation will be performed.

Means for Solving the Problems In order to solve the above problems, the present invention is provided with a writing switch and a writing auxiliary switch, and a writing means for writing a convergence correction amount to a memory by a logical product of the both switches. To

Therefore, in the present invention, the logical product of the two switches of the write switch and the write auxiliary switch, that is, the write operation of writing the convergence correction amount into the memory can be performed only when both of the two switches are simultaneously pressed.
This is to prevent an erroneous write operation.

Embodiment FIG. 1 is a block diagram of an embodiment of the present invention. The parts corresponding to those of the conventional example shown in FIG.

In FIG. 1, reference numeral 13 is a writing circuit of a digital convergence device which is an essential part of the present invention.
A write switch 11 provided with a g, a write auxiliary switch 12 provided with contacts h and i, and a logic circuit 14 that takes the logical product of the two switches 11 and 12, and the output of the logic circuit 14 is a control circuit as a write signal. Given to 8.

Therefore, when the write switch 11 and the write correction switch 12 of the write circuit 13 are both off, the input terminals j and k of the logic circuit 14 are both at the high level, and the output terminal 1 of the logic circuit 14 is set at the high level and becomes low. The active control circuit 8 does not perform the write operation. Write switch 11 of write circuit 13
Alternatively, if only one of the write auxiliary switches 12 is accidentally turned on, one input terminal of the logic circuit 14
The other input terminal becomes HIGH, the output terminal 1 of the logic circuit 14 becomes HIGH, and the control circuit 8 does not perform the write operation. When the write switch 11 and the write auxiliary switch 12 are simultaneously pressed and turned on, both input terminals k and j of the logic circuit 14 become LOW level, the output terminal 1 is set to LOW level, and the LOW active control circuit 8 writes. Will do the action.

A summary of the above operations is shown in FIG.

FIG. 3 shows the operation panel 15 for performing convergence correction.
The write switch 11 and the write auxiliary switch 12 are arranged at positions separated from each other so that they cannot be pressed by mistake at the same time. 16 is a cursor key that moves the cursor up and down, left and right to the point where you want to correct the convergence, 17 is a color switching key that selects convergence correction of red green blue, 18 is a mode switch that switches the mode such as cursor movement mode or convergence adjustment mode Is the key.

In the above embodiment, the logical product of the write switch 11 and the write auxiliary switch 12 is processed by hardware, but it can also be processed by software by the microprocessor used in the control circuit 8.

EFFECTS OF THE INVENTION Since the present invention has the above-described configuration, even if the write switch is pressed by mistake, the write operation for writing the incorrect convergence correction data in the nonvolatile memory is not performed. Can be shortened, convergence can be corrected in a short time, and the life of a nonvolatile memory having a finite number of writable times can be extended.

[Brief description of drawings]

1 is a block diagram of an embodiment of the present invention, FIG.
1 is an operation explanatory view of FIG. 1, FIG. 3 is a view showing an example of an operation panel used in the present invention, FIG. 4 is a block diagram of a conventional example, and FIG. 5 is a view showing a crosshatch pattern. 6 ... Frame memory, 7 ... Non-volatile memory, 8 ... Control circuit, 11 ... Write switch, 12 ... Write auxiliary switch, 14 ... Logic circuit.

Claims (1)

[Claims] 1. On a screen of a raster scan type color display device, intersections of mesh patterns that equally divide the horizontal direction into X and the vertical direction into Y are arranged two-dimensionally as digital convergence correction points, and the respective corrections are made. A frame memory that stores one plane of digital correction amount corresponding to a point and a non-volatile memory that stores several planes of digital correction amount are provided, and the digital correction amount of the frame memory is read in synchronization with the deflection timing of the color display device to obtain the analog correction amount. In the digital convergence correction device that corrects the convergence by converting to, a writing unit that increases or decreases each correction data in the frame memory and adjusts to an appropriate digital amount, and writes the contents of the entire frame memory to the non-volatile memory, Write for controlling start of write operation of the write means And switch, digital convergence apparatus according to claim a logical product of both said switch comprising a writing auxiliary switch that so as to start the writing operation of the writing means.