JPH0783072B2 - Container for semiconductor device - Google Patents
Container for semiconductor deviceInfo
- Publication number
- JPH0783072B2 JPH0783072B2 JP61221296A JP22129686A JPH0783072B2 JP H0783072 B2 JPH0783072 B2 JP H0783072B2 JP 61221296 A JP61221296 A JP 61221296A JP 22129686 A JP22129686 A JP 22129686A JP H0783072 B2 JPH0783072 B2 JP H0783072B2
- Authority
- JP
- Japan
- Prior art keywords
- conductor layer
- container
- semiconductor device
- insulating substrate
- transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 239000004065 semiconductor Substances 0.000 title claims description 15
- 239000004020 conductor Substances 0.000 claims description 38
- 239000000758 substrate Substances 0.000 claims description 15
- 239000012212 insulator Substances 0.000 claims description 11
- 239000003990 capacitor Substances 0.000 claims description 9
- 239000002184 metal Substances 0.000 description 10
- 239000000463 material Substances 0.000 description 3
- LTPBRCUWZOMYOC-UHFFFAOYSA-N Beryllium oxide Chemical compound O=[Be] LTPBRCUWZOMYOC-UHFFFAOYSA-N 0.000 description 2
- 238000005219 brazing Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000000149 penetrating effect Effects 0.000 description 1
Landscapes
- Microwave Amplifiers (AREA)
Description
【発明の詳細な説明】 〔産業上の利用分野〕 本発明は半導体装置用容器に関し、特に超高周波用トラ
ンジスタを搭載して収容するための半導体装置用容器に
関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device container, and more particularly to a semiconductor device container for mounting and accommodating an ultra-high frequency transistor.
従来の半導体装置用容器のうち、容器の内部に整合用コ
ンデンサ等を含んで超高周波用トランジスタを搭載する
ための容器は、第4図に例示するような構造のものが用
いられている。第4図は、超高周波電力用トランジスタ
と整合用コンデンサとを搭載して収容した半導体装置用
容器の斜視図である。Among the conventional semiconductor device containers, a container having a structure as illustrated in FIG. 4 is used as a container for mounting an ultra-high frequency transistor including a matching capacitor and the like inside the container. FIG. 4 is a perspective view of a semiconductor device container in which an ultra-high frequency power transistor and a matching capacitor are mounted and housed.
一般に超高周波トランジスタでは、外部線路(一般には
50Ω)との整合をとって使用するが、不整合による損失
を少なくするために、可能な限りトランジスタの近くで
整合をとることが必要であり、このため第4図に例示す
るように、同一の容器内に整合用コンデンサ8とトラン
ジスタ7とを搭載するような構成としている。また接地
インダクタンスを低減するため、トランジスタのエミッ
タの配線用金属19の細線は、同一エミッタ電極について
複数本を接続している。このため、ブリッジ用の金属ブ
リッジ10を容器内にろう付等の手段を用いて取付けてい
る。Generally, in an ultra high frequency transistor, an external line (generally,
50Ω) is used, but in order to reduce the loss due to mismatch, it is necessary to match as close to the transistor as possible. Therefore, as shown in FIG. The matching capacitor 8 and the transistor 7 are mounted in the container. Further, in order to reduce the ground inductance, a plurality of thin wires of the wiring metal 19 of the emitter of the transistor are connected to the same emitter electrode. Therefore, the metal bridge 10 for the bridge is mounted in the container by means such as brazing.
従来の超高周波トランジスタを搭載するための半導体装
置用容器は、上述のように金属ブリッジ10を絶縁基板11
にろう付等で固着しているため、信号導出用導体層1と
の間に空間を設けて絶縁する必要があり、このためある
程度の金属ブリッジ10の高さ(1mm程度)が必要であ
る。更に金属ブリッジ10の機械的強度を保つためにも、
その形状も大きくする必要がある。従って従来の半導体
装置用容器は、その形状が大きくなり、また製造コスト
も高くなるという欠点がある。A semiconductor device container for mounting a conventional ultra-high frequency transistor includes a metal bridge 10 and an insulating substrate 11 as described above.
Since they are fixed by brazing or the like, it is necessary to provide a space between them and the signal lead-out conductor layer 1 to insulate them. Therefore, the metal bridge 10 must have a certain height (about 1 mm). Furthermore, in order to maintain the mechanical strength of the metal bridge 10,
Its shape also needs to be large. Therefore, the conventional semiconductor device container has the drawbacks of large size and high manufacturing cost.
本発明の目的は、上述のような従来の半導体装置用容器
の欠点を除去して、形状が小さくまた製造コストを低減
できる半導体装置用容器を提供することにある。An object of the present invention is to provide a semiconductor device container having a small shape and a reduced manufacturing cost by eliminating the above-mentioned drawbacks of the conventional semiconductor device container.
本発明の半導体装置用容器は、信号導入用導体層と、前
記信号導入用導体層とは絶縁されていて半導体素子を搭
載するための信号導出用導体層と、前記信号導入用導体
層と前記信号導出用導体層との間に互いに絶縁されて設
けられていてコンデンサを搭載するための第一の接地導
体層とを上面に有し、第二の接地導体層を下面に有する
絶縁基板と、 前記絶縁基板上に搭載され上面に第三の接地導体層を有
する第二絶縁体とを備え、 前記第一および第二および第三接地導体層をスルーホー
ル導体または金属化層によって電気的に導通するように
接続したものである。The semiconductor device container of the present invention includes a signal introducing conductor layer, a signal introducing conductor layer for mounting a semiconductor element that is insulated from the signal introducing conductor layer, the signal introducing conductor layer, and the An insulating substrate having a first grounding conductor layer on the upper surface and a second grounding conductor layer on the lower surface, the first grounding conductor layer being mounted on the signal lead-out conductor layer so as to be insulated from each other and for mounting a capacitor, A second insulator mounted on the insulating substrate and having a third ground conductor layer on its upper surface, and electrically connecting the first, second and third ground conductor layers with a through-hole conductor or a metallized layer. Are connected to each other.
次に本発明の実施例について図面を参照して説明する。 Next, embodiments of the present invention will be described with reference to the drawings.
第1図(a)および(b)は本発明の第一の実施例の平
面図および側面図である。1 (a) and 1 (b) are a plan view and a side view of a first embodiment of the present invention.
第1図において参照符号1は絶縁基板、2は絶縁基板1
上に設けられている第二絶縁体であり、絶縁基板1の上
下面に設けられている接地導体層3a・3bと第二絶縁体2
の上面に設けられている接地導体層3cとは、絶縁基板1
と第二絶縁体2とを貫通するスルーホール4によって導
通されている。電力用トランジスタのように熱消費が大
きいトランジスタを搭載する場合は、絶縁基板1として
はベリリアのような熱伝導度の大きい材料が選ばれる
が、第二絶縁体2は、アルミナのような安価な材料でよ
い。絶縁基板1の上面には、接地用導体層3aと絶縁され
た信号導入用導体層5および信号導出用導体層6が設け
られている。信号導入用導体層5と信号導出用導体層6
も絶縁されている。In FIG. 1, reference numeral 1 is an insulating substrate, 2 is an insulating substrate 1.
The second insulator provided above and the ground conductor layers 3a and 3b and the second insulator 2 provided on the upper and lower surfaces of the insulating substrate 1.
The ground conductor layer 3c provided on the upper surface of the insulating substrate 1
And the second insulator 2 are electrically connected by a through hole 4 penetrating the second insulator 2. When a transistor that consumes a large amount of heat, such as a power transistor, is mounted, a material having a high thermal conductivity such as beryllia is selected as the insulating substrate 1, but the second insulator 2 is an inexpensive material such as alumina. The material is good. A signal introducing conductor layer 5 and a signal deriving conductor layer 6 which are insulated from the grounding conductor layer 3a are provided on the upper surface of the insulating substrate 1. Signal introduction conductor layer 5 and signal introduction conductor layer 6
Is also insulated.
第2図は第1図の実施例にトランジスタ7と、整合用コ
ンデンサ8とを搭載した状態を示す平面図である。FIG. 2 is a plan view showing a state in which the transistor 7 and the matching capacitor 8 are mounted on the embodiment shown in FIG.
トランジスタ7は信号導出用導体層6上に、整合用コン
デンサ8は接地用導体層3a上に搭載し、トランジスタ7
の接地用端子は配線用金属9によって接地導体層3cまた
は3aと接続する。これによって従来のように金属ブリッ
ジを使用せずに所望の接続を行うことができる。The transistor 7 is mounted on the signal deriving conductor layer 6 and the matching capacitor 8 is mounted on the grounding conductor layer 3a.
The grounding terminal is connected to the grounding conductor layer 3c or 3a by the wiring metal 9. This allows the desired connection to be made without the use of metal bridges as in the prior art.
第3図は本発明の第二の実施例を示す平面図である。FIG. 3 is a plan view showing a second embodiment of the present invention.
本実施例は絶縁基板21の上面または下面の接地導体層と
第二絶縁体22の上面の接地導体層との接続を、スルーホ
ールの代りにそれらの側面に被着させた金属化層23によ
って行ったものである。In this embodiment, the connection between the ground conductor layer on the upper surface or the lower surface of the insulating substrate 21 and the ground conductor layer on the upper surface of the second insulator 22 is made by a metallized layer 23 deposited on their side surfaces instead of through holes. I went there.
なお、上記の各実施例は、トランジスタや整合コンデン
サ等の電子部品搭載部が露出された構成の容器の場合の
例であるが、本発明は、キャップによって搭載した電子
部品を封止する構成の容器の場合にも適用できる。In addition, each of the above-described embodiments is an example of the case of a configuration in which the electronic component mounting portion such as a transistor and a matching capacitor is exposed, but the present invention is configured to seal the mounted electronic component with a cap. It can also be applied to containers.
以上説明したように、本発明は従来トランジスタの設置
のため用いていた金属ブリッジの代りに導体層を表面に
被着した第二絶縁体を用い、第二絶縁体を絶縁基板上に
直接搭載することによって小形で安価な半導体装置用容
器が得られるという効果がある。As described above, the present invention uses a second insulator having a conductor layer deposited on the surface thereof, instead of the metal bridge used for installing a transistor, and the second insulator is directly mounted on the insulating substrate. As a result, a small and inexpensive semiconductor device container can be obtained.
第1図(a)および(b)は本発明の第一の実施例の平
面図および側面図、第2図は第1図の実施例にトランジ
スタを搭載した状態を示す平面図、第3図は本発明の第
二の実施例を示す平面図、第4図は従来の半導体容器の
一例にトランジスタを搭載した状態を示す斜視図であ
る。 1、11、21……絶縁基板、2、22……第二絶縁体、3a・
3b……接地導体層、4……スルーホール、5・15……信
号導入用導体層、6・16……信号導出用導体層、7……
トランジスタ、8……整合用コンデンサ、9・19……配
線用金属、10……金属ブリッジ、11……絶縁基板。1 (a) and 1 (b) are a plan view and a side view of the first embodiment of the present invention, and FIG. 2 is a plan view showing a state in which a transistor is mounted on the embodiment of FIG. 1, and FIG. Is a plan view showing a second embodiment of the present invention, and FIG. 4 is a perspective view showing a state where a transistor is mounted on an example of a conventional semiconductor container. 1, 11, 21 ... Insulating substrate, 2, 22 ... Second insulator, 3a
3b …… Grounding conductor layer, 4 …… Through hole, 5 ・ 15 …… Signal introduction conductor layer, 6 ・ 16 …… Signal lead conductor layer, 7 ……
Transistor, 8 ... Matching capacitor, 9/19 ... Wiring metal, 10 ... Metal bridge, 11 ... Insulating substrate.
Claims (1)
とは絶縁されていて半導体素子を搭載するための信号導
出用導体層と前記信号導入用導体層と前記信号導出用導
体層との間に互いに絶縁されて設けられていてコンデン
サを搭載するための第一の接地導体層とを上面に有し、
第二の接地導体層を下面に有する絶縁基板と、 前記絶縁基板上に搭載され上面に第三の接地導体層を有
する第二絶縁体とを備え、 前記第一および第二および第三接地導体層をスルーホー
ル導体または金属化層によって電気的に導通するように
接続したことを特徴とする半導体装置用容器。1. A signal introducing conductor layer and the signal introducing conductor layer are insulated from each other, and a signal deriving conductor layer for mounting a semiconductor element, the signal introducing conductor layer, and the signal deriving conductor layer. Having a first ground conductor layer for mounting the capacitor, which is provided insulated from each other between
An insulating substrate having a second ground conductor layer on the lower surface; and a second insulator mounted on the insulating substrate and having a third ground conductor layer on the upper surface, the first, second, and third ground conductors A container for a semiconductor device, characterized in that the layers are electrically connected by a through-hole conductor or a metallized layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61221296A JPH0783072B2 (en) | 1986-09-18 | 1986-09-18 | Container for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61221296A JPH0783072B2 (en) | 1986-09-18 | 1986-09-18 | Container for semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6376355A JPS6376355A (en) | 1988-04-06 |
| JPH0783072B2 true JPH0783072B2 (en) | 1995-09-06 |
Family
ID=16764563
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61221296A Expired - Fee Related JPH0783072B2 (en) | 1986-09-18 | 1986-09-18 | Container for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0783072B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59126654A (en) * | 1983-01-10 | 1984-07-21 | Toshiba Corp | High frequency power amplifier |
-
1986
- 1986-09-18 JP JP61221296A patent/JPH0783072B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6376355A (en) | 1988-04-06 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
| LAPS | Cancellation because of no payment of annual fees |