JPH0787372B2 - Analog-digital conversion circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a mask layout of an analog / digital conversion circuit.

2. Description of the Related Art In recent years, video systems and audio systems using digital signal processing have become widespread, and analog-digital conversion circuits have become indispensable.

The mask layout of the reference signal level of the conventional analog-digital conversion circuit will be described below.

FIG. 2 is an example of a reference signal level mask layout of a conventional analog-to-digital conversion circuit, in which 1 is a pad for giving an input analog signal, 2 is a pad for giving the highest reference signal level, and 3 is a reference signal level. The pad 4 for giving the lowest level is a unit cell of a comparator for comparing the input analog signal and the reference signal level, 5 is a wiring for transmitting the input analog signal to the comparator unit cell 4, and 6 is a wiring for forming a standard reference level.

The operation of the analog-digital conversion circuit configured as described above will be described below.

First, the voltage corresponding to the highest reference level is applied to the pad 2 from the external fixed power supply, and the voltage corresponding to the lowest reference signal level is applied to the pad 3 from the outer peripheral fixed power supply.
As a result, through the wiring 6 to pads 2 to 3 (pad 2
And a potential difference between pad 3) / (wiring resistance of wiring 6). Now, the potential of pad 2 is V _RT , the potential of pad 3 is
If V _RB and the wiring resistance of the wiring 6 are R _ref , the wiring 6 has (V
The current of _RT− V _RB ) / R _erf flows from the pad 2 toward the pad 3. Since the current flowing into the comparator unit cell 4 which gives the reference signal level is smaller than the current flowing from the pad 2 to the pad 3 in the wiring 6, the reference signal level of the first comparator unit cell 4a is It becomes the same V _RT , and the reference signal level of the second comparator unit cell 4b is from the pad 2 to the second.
The voltage drops to the level corresponding to the wiring resistance up to the input of the comparator unit cell 4b. Furthermore, the reference signal level of the third comparator unit cell 4c becomes a level in which the voltage drops by the wiring resistance from the pad 2 to the input of the third comparator unit cell 4c. By applying a voltage from the external fixed power supply to the pads 2 and 3 in this way,
The reference signal level of each comparator unit cell 4 is fixed. Next, when an analog signal to be digitally converted is applied to the pad 1, it becomes an analog input of each comparator unit cell through the wiring 5, and in each comparator unit cell 4, the input analog signal and the reference signal level are compared and the result is digitalized. The conversion will be done.

It should be noted that the input analog signal entering each comparator unit cell 4 has a voltage flow to the comparator unit cell from the pad 2 to the pad 3 which is smaller than the current flowing through the wiring 6 and therefore causes a voltage drop during the wiring 5. Does not occur and they are all at the same potential.

DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention However, in the above-described conventional configuration, when the resistance value of the wiring 6 between the comparator unit cells 4 is made equal and the level of the reference signal is set, the wiring resistance of the portion where the wiring is folded back is reduced. Since width and length cannot be the same as other parts,
It was necessary to widen the width of the wiring resistance at the folded portion according to the length. However, when the line width is changed depending on the location, if the line width is uniformly thinned due to overetching in the wiring process, etc., the thin wire thinning ratio and the thick wire thinning ratio are different. However, there is a problem in that the level of the reference signal cannot be maintained at an ideal pitch at equal intervals, and the accuracy becomes poor at the time of digital conversion.

The present invention solves the above-mentioned conventional problems, and an object of the present invention is to provide an analog / digital conversion circuit capable of highly accurate digital processing.

Means for Solving the Problems In order to achieve this object, an analog-digital conversion circuit of the present invention has a basic wiring portion linearly extending on a semiconductor substrate and at the same time from a first pad (7). A first wiring (11) to which an input analog signal is applied and a wiring portion serving as a backbone are separated from the first wiring, and are folded and extended so as to surround the first wiring. 2,
A second wiring (12) having a third pad (8, 9) and to which a reference signal is applied, an input analog signal input from the first wiring, and an input from the second wiring A unit cell of a comparator circuit for comparing the input analog signal to a digital signal by arranging a plurality of the unit cells in a region between the first and second wirings. In the circuit device, the plurality of unit cells (10) have the same substantially isosceles triangular shape, and the bases of the plurality of unit cells are directed to the second wiring side and are linear along the first wiring. Arranged in a line,
At the folding points of the plurality of unit cells, the arrangement direction of the unit cells is gradually changed to be folded, and the second wiring is provided along the arrangement of the unit cells.

With this configuration, the second wiring is folded back in a circular arc shape in correspondence with the folded back portion B of the array of unit cells, so that the length of the second wiring per unit cell can be made substantially equal, It is possible to uniformly make the widths of the second wirings equal to each other, and to generate a reference voltage with an accurate pitch, in which the resistance value of the second wiring per unit cell does not change due to overetching in the wiring process. You can

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a mask layout of a reference signal level of an analog / digital conversion circuit according to an embodiment of the present invention. In FIG. 1, 7 is a pad for giving an input analog signal, 8 is a pad for giving the highest reference signal level, 9 is a pad for giving the lowest reference signal level, and 10 is a comparison between the input analog signal and the reference signal level. A comparator unit cell, 11 is a wiring for transmitting an input analog signal to the comparator unit cell 10, and 12 is a wiring for forming a reference signal level.

More specifically, the comparator unit cell
The element 10 is arranged so that the elements constituting the circuit of the comparator are housed within a substantially isosceles triangular shape. Then, the plurality of comparator unit cells (10a, 10b, ...) Of the same shape have the bottom portion of the unit cell directed to the wiring 12 (second wiring) side, and the wiring portion serving as the backbone is laid linearly. Wiring
11 (first wiring) are continuously arranged in a straight line, and the wiring as the backbone of the reference signal wiring 12 is provided along the outside of the unit cell row, and the linear portion A unit in FIG. 1 is provided. The cells and wirings 11 and 12 are laid out in a mask. In addition,
In the unit cells (10a, 10b, ...) Of each comparator, the wiring branched from the wiring portion which is the backbone of the wirings 11 and 12 is drawn into each unit cell and connected to each input terminal.

At the turn-back portion B in FIG. 1, the arrangement direction of the comparator unit cells 10 is gradually changed, and the unit cells are arranged so that the bottom portion draws an arc. In this way, if the wiring 12 is provided along the unit cell row, the length of the wiring 12 per unit cell can be made substantially the same at all locations, and the same line width can be made at all locations. It is possible to make the resistance value the same, thereby reducing the influence of etching accuracy in the wiring process.

First, the voltage corresponding to the highest reference signal level is applied to the pad 8 from the external fixed power supply, and the voltage corresponding to the lowest reference signal level is applied to the pad 9 from the external fixed power supply. As a result, through the wiring 12, the pad 8 to the pad 9
Current flows through. Now, assuming that the potential of the pad 8 is V ′ _RT and the potential of the pad 9 is V ′ _RB , and the wiring resistance of the wiring 12 is R ′ _ref , the wiring 12 has a current of (V ′ _RT −V ′ _RB ) / R ′ _ref . Will flow from the pad 8 toward the pad 9. Since the current flowing into the comparator unit cell 10 that gives the reference signal level is smaller than the current flowing from the pad 8 to the pad 9 in the wiring 12, the reference signal level of the first comparator unit cell 10a is the pad 7 the same V _'RT becomes a reference signal level of the second Kampa regulator unit cell 10b is formed of a pad 7 to a level that is by the voltage drop wiring resistance component to the input of the second comparator unit cell 10b. By thus applying the voltage from the external fixed power supply, the reference signal level of each comparator is fixed. At this time, in this embodiment, since the comparator unit cells are laid out along the arc at the folded portion, the wiring resistance between the comparator unit cells has the same width and the same length. The voltage level does not shift. Next, when an analog signal to be digitally converted is given to the pad 7, it becomes an analog input of each comparator unit cell 10 through the wiring 12, and in each comparator unit cell 10, the input analog signal is compared with the reference signal level,
As a result, digital conversion is performed.

As described above, the wiring between each comparator unit cell 12
By making the resistors of the same width and the same length, the reference voltage level with high accuracy can be created.

EFFECTS OF THE INVENTION As described above, according to the present invention, the unit cell row of the comparator circuit and the second wiring for the reference signal can be folded at substantially equal intervals, and the line width of the second wiring can be made uniform. Therefore, it is possible to realize an excellent analog-to-digital converter capable of performing digital conversion with a plurality of reference signals having a high pitch accuracy without affecting the etching accuracy of the wiring process.

[Brief description of drawings]

FIG. 1 is a plan view showing a mask layout of an analog-digital conversion circuit according to an embodiment of the present invention, and FIG. 2 is a plan view showing a mask layout of a reference voltage level of a conventional analog-digital conversion circuit. 1,2,3 …… Pad, 4 …… Comparator unit cell,
5,6 …… wiring, 7,8,9 …… pad, 11 …… comparator unit cell, 12,13 …… wiring.

Claims (1)

[Claims] 1. A first wiring to which an input analog signal is applied from a first pad, and a wiring portion to be a backbone are linearly extended on a semiconductor substrate. A second wiring that is spaced apart from the first wiring, extends back to surround the first wiring, has second and third pads at both ends, and to which a reference signal is applied; A unit cell of a comparator circuit for comparing an input analog signal inputted from the first wiring and a reference number inputted from the second wiring, wherein the unit cell of the comparator circuit is provided in a region between the first and second wirings. In a circuit device in which a plurality of unit cells are arranged and the input analog signal is converted into a digital signal, the plurality of unit cells have the same substantially isosceles triangular shape, and a bottom portion of the plurality of unit cells is the first base. For the wiring side of 2 Rutotomoni, along the first wire continuously linearly arranged, folded portions of the plurality of unit cells,
An analog-digital conversion circuit, characterized in that the arrangement direction of the unit cells is gradually changed and folded back, and a second wiring is provided along the arrangement of the unit cells.