JPH0793440B2 - Method of manufacturing thin film transistor - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor.

[0002]

2. Description of the Related Art Conventionally, a display panel using an active matrix has been attracting attention as a method capable of realizing a large-sized panel having a large number of dots because its matrix size can be made very large as compared with the dynamic method. In particular, a light-receiving element such as a liquid crystal has a limited drive duty in a dynamic system, and an active matrix application is considered for a television display and the like.

FIG. 1 shows one cell of a conventional active matrix. The address line X is input to the gate of the transistor 2, and the transistor is turned on to accumulate the signal on the data line Y in the holding capacitor 3 as electric charge. Until the data is written again, this capacitor 3
And the liquid crystal 4 is driven at the same time. VC here
Is a common electrode signal. Since the liquid crystal leaks very little, it is sufficient for holding charges for a short time. The manufacture of this transistor and capacitor 3 is exactly the same as the process of a normal IC.

FIG. 2 shows an example in which the cell of FIG. 1 is produced by a silicon gate process. Melting of 600C or more such as quartz
Transistor 10 and capacitor on transparent substrate with dots
12 are configured. The address line X and the upper electrode 11 of the capacitor are made of polycrystalline silicon (polysilicon) formed at a processing temperature of about 1000 ° C. , the data line Y and the liquid crystal drive electrode 13 are made of Al, and the contact holes 7 and 8 are formed. ，
9, the substrate and A1 are connected, and the polysilicon and A1 are connected.

[0005]

The matrix substrate according to the ordinary IC process has the following major drawbacks.

Since the manufacturing process of the matrix substrate is the same as that of IC , heat treatment at about 1000 ° C. is performed during the process.
These high temperature processes include device materials
And substrate materials are limited. Especially large display
If it does, use a metal material with low resistance for the gate material.
Or, it is essential to use inexpensive glass for the substrate,
Difficult with current high temperature processes.

[0007]

The present invention is formed on a substrate.
In the method of manufacturing a thin film transistor
Channel region and source of thin film silicon layer of transistor
.Laser beam or electron beam after forming the drain region
And a step of irradiating the laser beam or
Of the thin film transistor except the step of irradiating with an electron beam
The processing temperature in the manufacturing process should be 600 ° C or lower.
Characterize.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The structure of the present invention constitutes a thin film transistor having a silicon thin film as a channel, which will be described below with reference to specific examples.

[0009] FIG. 3 shows an example of a matrix cell to be used in the present invention, and FIG. 1, G including the capacitor 18
The difference is that ND wiring is newly provided,
Basic writing and holding of data are the same. The GND potential in this case means a constant bias voltage, and the bias level or the signal level does not matter. Also, as the capacitance for the data line Y to sample - hold the input of the display data, the capacitance 21 between the data line Y and the GND line, or the data line Y
And the parasitic capacitance 22 at the intersection of the address line X is used.

The capacitor 18 in the present invention is used to hold the display data of the cell portion for a certain period of time, and is about 16 msec for a television image, for example. If the leakage current of the silicon thin film transistor is 100 V or less at 10 V, the capacity of this holding capacitor is 0.5 PF.
~ 1PF is required.

If the liquid crystal material has a high relative dielectric constant, especially 10 or more, and the thickness of the liquid crystal material is 10 μm or less, the capacitance of the liquid crystal material as a dielectric becomes 0.5 PF or more, and the charge holding capacitor becomes No longer needed. Then, the GND line and the capacitor 18 in FIG. 3 can be omitted, the effective liquid crystal driving area is increased, the contrast can be improved, and extra elements are eliminated, leading to an improvement in yield. At this time, the sample-hold capacitance of the data line Y is mainly the parasitic capacitance 22 at the intersection of the data line and the address line.

Example 1 FIGS. 4A and 4B show the structure of a cell of Example 1 of the present invention . First silicon thin film 2 for forming source / drain / channel of transistor on transparent substrate 33
8 and a second silicon thin film forming a gate line to be a gate of a transistor or a wiring layer 26 and G equivalent thereto.
ND line 27, transparent low resistance material such as SnO ₂
As described above, the liquid crystal drive electrode 31 and the data line 25 made of a gold film or the like having a thickness of 100 Å or less, and the contact hole 29 for electrically connecting the layers are formed. Further, the overlapping portion of the GND line 27 and the liquid crystal drive electrode becomes a charge holding capacitor (FIG. 3-18). Source of transistor
The drain 34, 35 are present over the N ⁺ diffusion (P-channel if P ⁺⁾ is a gate insulating film 36 channels 30 in the lower gate electrode 38 made, also further insulation, such as oxide film around the gate electrode The film 37 is formed.

The feature of the first structure shown in FIG. 4 is as follows .
The gate insulating film of the transistor becomes a gate self-alignment by forming the first silicon thin film on the silicon thin film by oxidation or forming on the silicon thin film. It is possible to prevent the deterioration of the speed by reducing the parasitic capacitance by making the parasitic capacitance self-aligned.

The other is to hold a charge (see FIG. 3-1).
8) Capacitance for sample-hold of data line (Fig. 3-2
As the dielectric film of the capacitor for forming the first and the second), an oxide film of a second silicon thin film or an insulating film on the thin film is used.

In the conventional bulk silicon type, a bulk silicon thermal oxide film is used for the gate insulating film and the charge holding capacitor of the transistor, but the impurity doping is performed by the gate cell alignment shown in FIG. 5B. In the case of the method, since a high-concentration impurity does not enter under the second-layer silicon thin film that forms one electrode of the capacitance, it is difficult to use as it is because it is unstable as the capacitance. An extra step of doping a high concentration impurity only in the lower electrode of the capacitor is required. Therefore, as shown in Figure 4,
By forming the dielectric film forming the holding capacitor on the second-layer silicon thin film , the process can be simplified and the capacitor can be stabilized.

FIG. 5 shows a manufacturing process of the active matrix cell shown in FIG. In the low temperature process of the present invention, glass or a high melting point glass such as Pyrex or Corning is used as the transparent substrate, the process is performed at 600 ° C. or lower, and the substrate itself is inexpensive.

In the low temperature process, first, a silicon thin film is formed on the substrate 33 by CVA such as plasma CVD or low pressure CVD.
Method, sputtering method or the like, and photoetching into a required shape. Then, the surface is oxidized in an O ₂ plasma atmosphere. In practice, a CVD method may be used to deposit an equivalent insulating film. As a result, an oxide film 41 serving as a gate insulating film is formed on the silicon thin film 40 (FIG. 5A). After that, the second-layer silicon thin film is deposited in the same manner as the first-layer silicon thin film and photoetched.
The oxide film 41 is etched by using the silicon thin film 45 of the layer as a mask to form the gate insulating film 41 and at the same time a diffusion window is formed. When diffusion is performed by ion implantation, sources and drains 42 and 43 are formed. (Fig. 5
(B)).

After that, plasma treatment is again performed in an O ₂ atmosphere to form a plasma oxide film 46 on the surface, and the temperature is 400 ° C.
Annealing is performed at 600 ° C. (FIG. 5C).

The characteristic of this process is that the silicon thin film is directly oxidized by plasma treatment, and the mobility is improved as an oxide film of the CVD method as a gate insulating film of a transistor and a dielectric film for a capacitor. Also, the reliability is improved.

The steps after FIG. 5C are as follows .
A contact hole is opened to keep the contact between the wiring part and the first and second layers, and the material that also serves as the wiring and the transparent drive electrode, the NES film, the metal with a thickness of 100 Å or less is sputtered or evaporated. Attach and photoetch. If it is difficult to directly contact the silicon thin film such as the Nesa film, a contact exclusive material such as Au or Ni-Cr is added to the contact portion.

Since the transistor formed by the above method has low mobility only by the above-mentioned processing , the following measures are required.

FIG. 6A shows a first silicon thin film formed by a low pressure CVD apparatus while changing the deposition temperature.
Shows the mobility of the transistor at 10V. It was found by experiments that the mobility sharply improves when the deposition temperature becomes 600 ° C. or lower. Therefore,
First, as a first device , in order to improve the mobility and ensure the response, it is advisable to form the first silicon thin film at 600 ° C. or lower by a low pressure CVD apparatus.

FIG. 7 shows the O of the transistor at 10V.
The FF leakage current I _C is calculated as the film thickness t of the first silicon thin film.
It is plotted by changing _si . The inventor has experimentally found that a film thickness of 3700 Å or less results in a leakage current of 500 PA or less, which is not a problem for use.

Next, as a second point, it is possible to locally anneal the silicon thin film of the first layer at a high temperature so as not to affect the substrate by the laser or the electron beam.

FIG. 6B shows the mobility of a transistor obtained by illuminating a silicon thin film formed in the same manner as in the above-mentioned (A) with a laser beam with a Q switch of 0.12 mJ per pulse. , It can be seen that it has been further improved. From this, it is understood that the local annealing by the laser beam, the electron beam, etc. is particularly effective.

(Embodiment 2) FIG. 8 shows a cell structure according to a second embodiment of the present invention .
(A) is a plan view and the address line 51 is the data line 50.
Drain the source, drive electrode and capacitor electrode 52
It has become to the gate of the channel 54 of the transistor to be down. The GND line 53 is formed at the same time as the address line 51 and forms a capacitance with the electrode 52.

FIG. 8B shows a cross section taken along the line AB of FIG. 8A. An example of the manufacturing process will be described below.
A silicon layer is grown on the lath substrate 57 by about 3000 Å. However, in some cases, to improve adhesion, a thin S
In some cases , iO ₂ may be previously formed on the surface of the substrate . Further, by photo-etching, the gate 51 and the GND line 5
After forming 3 , the SiO ₂ film 55 of about 1500 Å is grown as the gate insulating film and the dielectric film of the capacitor. After that, a second silicon layer is formed, and a pattern is formed by photoetching. Then, P ions are implanted in a portion other than the channel portion 54 by a resist mask to form a liquid crystal which also serves as a source / drain electrode, a data line wiring portion, and a capacitor electrode. The drive electrode is formed.

The welding performance (threshold, conductance) of transistor in this state because there is insufficient, especially locally channel section 54, or uniformly throughout the substrate, the silicon layer is irradiated with a laser in a short time , Improve performance by solidifying and growing grains.
This is what is called laser annealing.

The feature of this structure is that, contrary to FIG. 4, the first gate silicon thin film is used for the transistor gate and the second gate silicon thin film is used for the channel. As a result, both silicon thin films are used. A high-concentration diffusion is possible, and a gate oxide film obtained by oxidizing the silicon thin film of the first layer or a gate insulating film on the silicon film of the first layer is used to form a charge holding capacitor. Dielectric film can be used,
The process of forming an oxide film is good in one process.

Another feature is that the first-layer silicon film serves as the address lines and the GND lines and the second-layer silicon film serves as the data-line wiring without newly providing a wiring material as shown in FIG. 4, the step of depositing the wiring material and photoetching can be omitted as compared with the configuration example of FIG. 4, and the step is further simplified. In addition, this method uses a silicon film as a transparent drive electrode of liquid crystal, and the silicon film also has a thickness of 3000 Å.
If it is below, it will be sufficiently transparent because it is almost transparent.

(Embodiment 3) FIG. 9 shows the structure of a cell according to a third embodiment of the present invention, in which the cell is formed on a normal glass substrate by a low temperature process.
Show things . A silicon film is formed on the glass substrate 70 by a low temperature film forming method such as sputtering or plasma CVD, and P ions or B ions are implanted on the entire surface. Next, the gate 73 and the capacitor electrode 72 are formed by photoetching. Further, the insulating film 74 is formed. Again, SiO ₂ or the like grown by low temperature is used. In addition, 2 to serve as the source and drain of the transistor, the capacitor and the drive electrode
The silicon film 75 of the layer is also formed at a low temperature. This polysilicon is not doped at all or is implanted with a sufficient amount of B ions to enhance the darkness. After that, the laser beam is locally or entirely irradiated and annealed.

A part of the laser beam is absorbed by the silicon of the first layer, but is transmitted through the glass substrate 70. Therefore 1
Activation of the impurity which is ion-implanted into the silicon layer th appropriate beam energy to a second layer of polysilicon grain growth (especially the channel unit 78) is performed
ー, appropriate time (pulse interval for pulsed laser, C
When the W laser treatment with dependent) on the scanning speed, the glass substrate can anneal range is almost no influence. The feature of this method is that laser annealing can reduce the influence of the conventional thermal annealing on the glass substrate, so that glass with low cost can be used. It is possible to grow the grain of the film and at the same time improve the characteristics of the transistor, especially the mobility.

After that, Al is applied and photoetching is performed to form source / drain electrodes 76 and 77. Since it is difficult to make contact with Al and silicon as they are, heat treatment may be carried out to some extent or a weak laser beam may be irradiated.

FIG. 10 shows an example of a liquid crystal display device using the matrix substrate of the present invention. Transparent drive electrode 6
A common electrode 69 composed of a transparent substrate 65 on which 7 is placed and a Nesa film
The liquid crystal body 68 is sandwiched between the glass 66 and the glass 66. Furthermore, after sandwiching with the polarizing plates 62 and 63, the reflecting plate 64 is attached to the lower side. In this way, most of the light incident from above passes through the electrode 67, is reflected by the reflector 64, and is sensed by the human eye.

The transistor constructed by the manufacturing method of the present invention is an external drive circuit for an active matrix,
That is, the shift register and the sample hold circuit can be built in the same substrate.

FIG. 11 shows the configuration of the manufacturing method of the present invention .
3 is an example of a drive circuit on the gate line side of a liquid crystal device using a transistor formed by using a transistor . The shift register cell 80 includes four transistors 81 to 84 and one bootstrap capacitor 8
It is composed of 5. The clock is a phase of φ ₁ and φ ₂ , and the “1” potential is sequentially transferred in synchronization with the clock by the input of the start pulse SP. Output D _{1 of} each shift register
.. D _m are input to the gate lines, and as a result, as shown in FIG. 12, each gate line is sequentially selected. The input transfer gate transistor 81 is used for the shift register input, and once stored in T ₁ to T _n , “1” is written to D ₁ to D _m by the bootstrap capacitance. If this transfer gate is not used, D ₁ , T ₂ , T _3, ...
… Shorted with bootstrap capacitance to gate line capacitance
There is much to be greater than C _G1, pattern is increased, thereby lowering the yield. Also it is only the written "1" to D ₁ ~ D _m for discharging 0 "connects the T ₃ to the transistor 84, but if the shift register is operated at a low frequency, the slight leakage On the other hand, the operation becomes defective, so that the potential fixing transistor 83 is added to improve the yield and stabilize the operation, and the voltage is refreshed to "0" level every half cycle of the clock.

FIG. 13 shows the configuration of the manufacturing method of the present invention .
2 is an example of a drive circuit on the data line side of a liquid crystal device using a transistor that is configured to operate . The shift register cell 86 includes a bootstrap capacitor 88 and transistors 89 and 9 necessary for operation.
1 and a reset transistor 90 for selecting a shift register, which will be described later, and an input gate 87 to the first stage.
A start pulse SP is applied via. The shift register outputs S ₁ to S _m are input to the sample and hold transistors H ₁ to H _m , and the capacitance C parasitic the data input to the video inputs V and S (video signal or data write signal) in synchronization with the scanning signal. _D1 to C _Dm are sample-held.

The data line side drive circuit is high in speed because it performs all the processing within one scanning line, and it is not necessary to consider the leak current so much. On the contrary, in order to ensure high speed operation and to achieve high speed. It is necessary to consider suppressing the increasing power consumption.

Since only 1 bit in the m bits is "1" in this shift register, power consumption other than the clock is small. In addition, the sample and hold transistor H ₁ ~
Although H _m requires considerably high-speed switching, it is applied to the gate input by a bootstrap operation with an amplitude nearly twice that of the clock signal as shown in FIG. is there.

FIG. 15 shows a case where these are actually arranged on the active matrix substrate. There are data-side shift registers 90 and 91, dummy cells 94 and 95 for forming the final stage feedback signal, and sample-hold transistors H ₁ to H _m, which are arranged in a vertically symmetrical manner. The gate-side shift registers 92 and 93 and the dummies 96 and 97 are arranged symmetrically. Originally, the peripheral circuit does not need to be symmetrical on both sides, and only one may be used, but a plurality of shift register arrays are prepared in consideration of the yield. Of course, it may be 4 columns or 8 columns, but here, an example of 2 columns is shown. The bootstrap capacitance 85 in the peripheral drive circuit of the present invention is basically an insulating film between a gate and a channel forming a transistor, unlike a capacitor for holding charges. In addition, the bootstrap capacitance needs to have a variable interelectrode capacitance depending on the gate voltage of the upper electrode, and therefore the lower electrode of the capacitance is a low-concentration or non-doped silicon film.

As described above, by using the silicon thin film on the insulating substrate, the cell portion of the active matrix and the peripheral driving circuit are formed.
If the paths are formed at the same time, the connection will be easier and the overall cost will be reduced. The peripheral driver circuit 11, Lane sucrose-less non-inverting as shown in FIG. 13 - and it has a shift register, considering such that the parasitic capacitance is much lower,
The overall power consumption can be reduced, and at the same time, the yield can be improved and the cost can be reduced.

[0042]

As described above, according to the present invention,
In the production how of the formed thin film transistor, the thin
The channel region of the silicon thin film layer of the film transistor and the
After forming the source / drain region, laser beam or electron beam
Laser beam irradiation, and the laser beam
Or the thin film transistor except the step of irradiating with an electron beam
The processing temperature in the manufacturing process is less than 600 ℃
There are advantages as described below .

A) It is possible to form a transistor having high mobility by a low temperature process of 600 ° C. or lower.

B) Since it is a low temperature process, a metal having a high mobility (a metal having low heat resistance such as Al and Ta) can be used as the gate electrode.

C) Since only a necessary portion can be selectively crystallized by irradiation with a laser beam or an electron beam, a thin film transistor made of amorphous silicon having a small off-current and polycrystalline silicon having a large on-current are used. Can be easily formed on the same substrate.

D) When manufacturing a self-aligned thin film transistor, the impurity doped in the silicon film can be activated using the gate electrode as a mask without exposing the entire substrate to high temperature as in the conventional case.

F) Since the activation of the impurities is not performed by the conventional annealing such that heat is applied to the entire substrate, it is easy to control the impurity diffusion region, and thus the size of the diffusion region can be accurately controlled. Therefore, the gate electrode and source
The parasitic capacitance with the drain region can be made extremely small.

[0048]

[Brief description of drawings]

FIG. 1 is a circuit diagram of a cell used in a conventional active matrix.

FIG. 2 is a plan view of a conventional cell.

FIG. 3 is a cell configuration diagram of the first embodiment of the present invention.

4A and 4B are a plan view and a sectional view thereof .

5 (a), (b) and (c) are manufacturing process diagrams thereof.

FIG. 6 is a diagram showing characteristics of a silicon thin film.

FIG. 7 is a diagram showing characteristics of a silicon thin film.

8A and 8B are cell structures of a second embodiment of the present invention .
Diagram .

FIG. 9 is a cell configuration diagram of a third embodiment of the present invention.

FIG. 10 is a sectional view of the active matrix panel of the present invention when assembled.

FIG. 11 is a diagram showing an example of a peripheral drive circuit used in the present invention.

FIG. 12 is an operation waveform diagram of the peripheral drive circuit of the present invention.

FIG. 13 is a diagram showing an example of a peripheral drive circuit used in the present invention.

FIG. 14 is an operation waveform diagram of the peripheral drive circuit of the present invention.

FIG. 15 is a diagram showing an example of a peripheral drive circuit used in the present invention.

[Explanation of symbols]

7, 8 and 9 Contact hole 10 Transistor 11 Upper electrode 13 of capacitor 3 Drive electrode 31 made of Al Transparent low resistance element 26, 45, 50, 52, 75 Silicon thin film of the second layer 28, 40, 51, 53, 72, 73 First-layer silicon thin film 30, 44, 54, 78 Channel 33, 57, 70 Substrate 36, 41, 55, 74, Gate insulating film 37, 46 Capacitive insulating film 62, 63 Polarizing plate 64 Reflecting plate 65, 66 Transparent substrate 67 Transparent drive electrode 68 Liquid crystal body 69 Nesa film 76, 77 Al 85, 88 Bootstrap capacitance 89 Transistor 90, 91, 92, 93 Shift register

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H01L 21/336

Claims (1)

[Claims] 1. A method of manufacturing a thin film transistor formed on a substrate, comprising: a silicon thin film of the thin film transistor.
After forming the channel region and source / drain regions of the layer
Laser beam or electron beam irradiation, or
The step of irradiating the laser beam or electron beam
Temperature in the manufacturing process of the thin film transistor excluding
Is 600 ° C. or less, a method for manufacturing a thin film transistor.