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JPH0795583B2 - Semiconductor device - Google Patents
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JPH0795583B2 - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH0795583B2
JPH0795583B2 JP63273434A JP27343488A JPH0795583B2 JP H0795583 B2 JPH0795583 B2 JP H0795583B2 JP 63273434 A JP63273434 A JP 63273434A JP 27343488 A JP27343488 A JP 27343488A JP H0795583 B2 JPH0795583 B2 JP H0795583B2
Authority
JP
Japan
Prior art keywords
layer
polycrystalline silicon
type impurity
conductivity type
impurity
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP63273434A
Other languages
Japanese (ja)
Other versions
JPH02119263A (en
Inventor
和彦 辻
昌三 岡田
和宏 小伏
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP63273434A priority Critical patent/JPH0795583B2/en
Publication of JPH02119263A publication Critical patent/JPH02119263A/en
Publication of JPH0795583B2 publication Critical patent/JPH0795583B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Semiconductor Integrated Circuits (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は半導体内にある形成された不純物の相互拡散を
防止した半導体装置およびその製造方法に関するもので
ある。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device in which impurities formed in a semiconductor are prevented from interdiffusion and a method for manufacturing the same.

従来の技術 従来の半導体装置においては、第4図に示すように半導
体基板21に形成した一導電型不純物層たとえばn型不純
物22を含有した半導体基板あるいは多結晶硅素膜24と、
前記と反対導電型不純物たとえばP型不純物23を含有し
た半導体基板あるいは多結晶硅素膜25とを電気的に接続
する場合PN接合の形成をさけるため一度アルミニウムな
どの金沿導電体層26を介して行っていた。
2. Description of the Related Art In a conventional semiconductor device, as shown in FIG. 4, one conductivity type impurity layer formed on a semiconductor substrate 21, for example, a semiconductor substrate containing an n-type impurity 22 or a polycrystalline silicon film 24,
When electrically connecting to a semiconductor substrate or a polycrystalline silicon film 25 containing an impurity of a conductivity type opposite to the above, for example, a P-type impurity 23, a gold-side conductor layer 26 of aluminum or the like is used once to prevent the formation of a PN junction. I was going.

また、低濃度不純物を含有する高抵抗半導体を抵抗体と
して用いた場合、高濃度不純物を含有する低抵抗半導体
と接続した場合、低抵抗半導体の不純物が高抵抗半導体
側へ拡散するため、前記高抵抗体の長さを長くしておく
必要があった。
When a high-resistance semiconductor containing a low-concentration impurity is used as a resistor, when connected to a low-resistance semiconductor containing a high-concentration impurity, the impurities of the low-resistance semiconductor diffuse to the high-resistance semiconductor side, It was necessary to lengthen the resistor.

発明が解決しようとする課題 従来例のように、異なる導電型を有する多結晶硅素膜の
接続を、金属導電体層を介して行った場合、金属導電体
膜とそれぞれの多結晶硅素膜の接続領域が必要であり高
密度化の妨げとなっていた。また、半導体基板に形成さ
れた不純物層に直接金属層を形成した場合、金属と半導
体との相互拡散、あるいは、金属として高融点金属を用
いた場合、不純物イオンと金属との相互拡散により、不
純物層の特性が劣化するという問題があった。
DISCLOSURE OF THE INVENTION Problems to be Solved by the Invention When a polycrystalline silicon film having a different conductivity type is connected through a metal conductor layer as in a conventional example, the metal conductor film is connected to each polycrystalline silicon film. A region is required, which hinders high density. Further, when a metal layer is directly formed on the impurity layer formed on the semiconductor substrate, the metal and the semiconductor are inter-diffused, or when a refractory metal is used as the metal, the impurity ions and the metal are inter-diffused. There is a problem that the characteristics of the layer deteriorate.

課題を解決するための手段 本発明は、上述の問題点を解決するため、異なる導電型
を有する半導体の接続領域に前記導電型不純物の拡散を
防止する不順物イオンを注入させるという構成を備えた
ものである。また、一導電型半導体基板と金属層の接続
領域に前記半導体および半導体中の導電型不純物と前記
金属の相互拡散を防止する不純物イオンを注入させると
いう構成を備えたものである。
Means for Solving the Problems In order to solve the above-mentioned problems, the present invention is provided with a configuration of implanting disordered ion for preventing diffusion of the conductivity type impurities into a connection region of a semiconductor having a different conductivity type. It is a thing. In addition, the semiconductor device is provided with a configuration in which impurity ions that prevent mutual diffusion of the semiconductor and conductive impurities in the semiconductor and the metal are implanted into a connection region between the one conductive semiconductor substrate and the metal layer.

作用 本発明は上述の構成によって、異なる導電型の接続領域
に注入した拡散防止不純物イオンが、半導体中の導電型
不純物イオンの拡散を防止するため、異なる導電型の半
導体を直接接続しても、不純物の相互拡散を生じない、
電気的に良好な接続を形成することが可能となる。ま
た、一導電型の半導体と金属の接続領域に注入した拡散
防止不純物イオンが前記と同様に、半導体中の不純物と
金属イオンの相互拡散を防止し、特性劣化のない、半導
体と金属層との接続を可能にする。
Action The present invention, by the above-mentioned configuration, the diffusion prevention impurity ions injected into the connection regions of different conductivity types prevent the diffusion of the conductivity type impurity ions in the semiconductor, so that the semiconductors of different conductivity types are directly connected, Does not cause mutual diffusion of impurities,
It is possible to form an electrically favorable connection. Further, the diffusion preventing impurity ions injected into the connection region of the one conductivity type semiconductor and the metal prevent the mutual diffusion of the impurity in the semiconductor and the metal ion in the same manner as described above and prevent the characteristics from deteriorating between the semiconductor and the metal layer. Allow connection.

実 施 例 第1図は本発明の一実施例による半導体装置の概略構成
を示すものであって、1は半導体基板、2および3は互
いに異なる導電型、たとえば2はn型、3はp型導電型
を示す不純物を導入した不純物導入領域である。4は絶
縁物膜、5はn型不純物を含む多結晶硅素膜、6はP型
不純物を含む多結晶硅素膜であり、7は窒素イオンをイ
オン注入法によりたとえば1.5KeVで4×1016イオン/cm2
注入したバリア領域である。8は低抵抗導電体層たとえ
ばチタン等の高融点金属あるいはチタンシリサイドなど
である。
Example 1 FIG. 1 shows a schematic structure of a semiconductor device according to an example of the present invention, in which 1 is a semiconductor substrate, 2 and 3 are different conductivity types, for example, 2 is n type and 3 is p type. This is an impurity introduction region into which an impurity exhibiting a conductivity type is introduced. Reference numeral 4 is an insulator film, 5 is a polycrystalline silicon film containing n-type impurities, 6 is a polycrystalline silicon film containing P-type impurities, and 7 is nitrogen ions by ion implantation, for example, 4 × 10 16 ions at 1.5 KeV. / cm 2
This is the implanted barrier region. Reference numeral 8 is a low resistance conductor layer such as a refractory metal such as titanium or titanium silicide.

上記構成における半導体装置において、多結晶半導体膜
中の不純物の相互拡散は、窒素イオン注入領域で阻止さ
れ、相互の電気的接続は高融点金属を介して行われる第
3図に多結晶硅素膜と高融点金属膜の接続抵抗と窒素イ
オン注入量の関係を示す。第3図より明らかなように、
中入量が5×1016イオン/cm2以下ではほとんど接続抵抗
が増加しない。また、不純物の拡散防止のためには、注
入量が多い程よい。したがって、不純物の拡散を防止
し、かつ良好な電気的接続を得るためにイオン注入量は
5×1016イオン/cm2以下で行った。
In the semiconductor device having the above structure, mutual diffusion of impurities in the polycrystalline semiconductor film is blocked in the nitrogen ion implantation region, and mutual electrical connection is made through the refractory metal. The relationship between the connection resistance of the refractory metal film and the nitrogen ion implantation amount is shown. As is clear from FIG.
When the penetration amount is 5 × 10 16 ions / cm 2 or less, the connection resistance hardly increases. Further, in order to prevent the diffusion of impurities, it is preferable that the implantation amount be large. Therefore, in order to prevent the diffusion of impurities and to obtain a good electrical connection, the ion implantation amount is 5 × 10 16 ions / cm 2 or less.

第2の実施例を第2図にもとづいて説明する。10は一導
電型半導体基板、11は絶縁物膜、12は高濃度に不純物を
含有する低抵抗多結晶硅素膜、13は低濃度の不純物を含
有する高抵抗多結晶硅素膜であり、14は不純物拡散防止
イオン注入層である。
A second embodiment will be described with reference to FIG. 10 is a one conductivity type semiconductor substrate, 11 is an insulator film, 12 is a low resistance polycrystalline silicon film containing impurities in a high concentration, 13 is a high resistance polycrystalline silicon film containing impurities in a low concentration, and 14 is It is an ion diffusion layer for preventing impurity diffusion.

本実施例は、低抵抗半導体領域の不純物が、低抵抗領域
に拡散するのを防止するのが目的である。上記目的を達
成するため、前記のように、高濃度不純物層と低濃度不
純物層の接続領域に窒素あるいは炭素などの拡散防止イ
オンをイオン注入法により注入形成すことにより、前記
異なる濃度の不純物層を電気的に接続するとともに低濃
度不純物層を抵抗層として利用するものである。上記構
成によれば従来例と異なり、抵抗層のパターンの長さを
大きくすることなく高抵抗層を高密度に形成することが
できる。
The purpose of this embodiment is to prevent impurities in the low resistance semiconductor region from diffusing into the low resistance region. In order to achieve the above object, as described above, diffusion preventing ions such as nitrogen or carbon are implanted by ion implantation into the connection region between the high concentration impurity layer and the low concentration impurity layer to form the impurity layers having different concentrations. Is electrically connected and the low-concentration impurity layer is used as a resistance layer. According to the above configuration, unlike the conventional example, the high resistance layer can be formed at a high density without increasing the length of the pattern of the resistance layer.

発明の効果 本発明の方法によれば、異なる不純物濃度を有する半導
体および異なる導電型を示す半導体を電気的直接接続す
ることができ、かつ、それぞれの不純物の相互拡散を防
止することができるため、それぞれの不純物濃度および
導電型に影響を与えることなく、高密度の半導体装置を
形成することができる。
EFFECTS OF THE INVENTION According to the method of the present invention, semiconductors having different impurity concentrations and semiconductors having different conductivity types can be electrically directly connected to each other, and mutual diffusion of respective impurities can be prevented. A high-density semiconductor device can be formed without affecting the respective impurity concentrations and conductivity types.

【図面の簡単な説明】[Brief description of drawings]

第1図は本発明の第1の実施例を説明するための構造断
面図、第2図は本発明の第2の実施例を説明するための
構造断面図、第3図は本発明の実施例の電気特性図、第
4図は従来例を説明するための構造断面図である 1……半導体基板、2……導電型不純物層、3……他の
導電型不純物層、7……ベリア領域。
FIG. 1 is a structural sectional view for explaining a first embodiment of the present invention, FIG. 2 is a structural sectional view for explaining a second embodiment of the present invention, and FIG. 3 is an embodiment of the present invention. FIG. 4 is an electrical characteristic diagram of an example, and FIG. 4 is a structural cross-sectional view for explaining a conventional example. 1 ... Semiconductor substrate, 2 ... Conductive impurity layer, 3 ... Other conductive impurity layer, 7 ... Belia region.

Claims (3)

【特許請求の範囲】[Claims] 【請求項1】半導体基板に形成された第1の導電型不純
物層及び第2の導電型不純物層と、非導電型不純物イオ
ンが注入されるとともに前記第1の導電型不純物層及び
前記第2の導電型不純物層に接続され、前記第1の導電
型不純物層及び前記第2の導電型不純物層間の相互拡散
を防止する低濃度の非導電型不純物イオン注入層と、前
記非導電型不純物イオン注入層上に形成された低抵抗導
体層とを有する半導体装置。
1. A first conductivity type impurity layer and a second conductivity type impurity layer formed on a semiconductor substrate, and non-conductivity type impurity ions are implanted and the first conductivity type impurity layer and the second layer are formed. A low-concentration non-conductivity type impurity ion implantation layer that is connected to the second conductivity-type impurity layer and prevents mutual diffusion between the first conductivity type impurity layer and the second conductivity type impurity layer; A semiconductor device having a low resistance conductor layer formed on an injection layer.
【請求項2】非導電型不純物イオンが窒素であり、その
注入量が5×1016イオン/cm2以下であることを特徴とす
る特許請求の範囲第1項に記載の半導体装置。
2. The semiconductor device according to claim 1, wherein the non-conductive type impurity ion is nitrogen and the implantation amount is 5 × 10 16 ions / cm 2 or less.
【請求項3】絶縁膜上に形成された低濃度の不純物を有
する第1の多結晶硅素層及び高濃度の不純物を有する第
2の多結晶硅素層と、非導電型不純物イオンが注入され
るとともに前記第1の多結晶硅素層と第2の多結晶硅素
層間に形成された不純物拡散防止層とを有し、前記不純
物拡散防止層に注入される不純物イオンが前記第1の多
結晶硅素層と前記第2の多結晶硅素層間の電気的接続が
とれる量の低濃度であること特徴とする半導体装置。
3. A first polycrystalline silicon layer having a low concentration of impurities and a second polycrystalline silicon layer having a high concentration of impurities formed on an insulating film, and non-conductive impurity ions are implanted. And an impurity diffusion prevention layer formed between the first polycrystalline silicon layer and a second polycrystalline silicon layer, and the impurity ions injected into the impurity diffusion prevention layer are the first polycrystalline silicon layer. And a semiconductor device having a low concentration such that electrical connection can be made between the second polycrystalline silicon layer and the second polycrystalline silicon layer.
JP63273434A 1988-10-28 1988-10-28 Semiconductor device Expired - Fee Related JPH0795583B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63273434A JPH0795583B2 (en) 1988-10-28 1988-10-28 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63273434A JPH0795583B2 (en) 1988-10-28 1988-10-28 Semiconductor device

Publications (2)

Publication Number Publication Date
JPH02119263A JPH02119263A (en) 1990-05-07
JPH0795583B2 true JPH0795583B2 (en) 1995-10-11

Family

ID=17527853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63273434A Expired - Fee Related JPH0795583B2 (en) 1988-10-28 1988-10-28 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH0795583B2 (en)

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5246798B2 (en) * 1974-03-05 1977-11-28
US3976511A (en) * 1975-06-30 1976-08-24 Ibm Corporation Method for fabricating integrated circuit structures with full dielectric isolation by ion bombardment

Also Published As

Publication number Publication date
JPH02119263A (en) 1990-05-07

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