JPH0795697B2 - Miute circuit - Google Patents

Description

The present invention relates to a mute circuit for a FSK receiver in a subcarrier modulation system.

[Conventional technology]

Conventionally, the FSK receiver has a built-in mute circuit for erasing the data signal sound of the data portion included in the received signal. At this time, the mute circuit is generally configured to operate when a bit synchronization signal in the data signal is detected. That is, the conventional FSK receiver has a block diagram as shown in FIG.
In addition to the first mute circuit including the noise squelch circuit 15 and the first mute switch (SW) 11 whose opening and closing are controlled by the noise squelch circuit 15, the decoder 1
6, MPU (microprocessor) 17 and second mute switch (SW) 12, and when the MPU 17 detects a bit synchronization signal in the digital signal supplied from the decoder 16, the second MPU 17
A second mute circuit for opening the mute switch 12 is provided.

By the way, the FSK receiver enters a voice call after receiving data, but a signal similar to the bit synchronization signal may be generated depending on the voice signal. Then, the MPU 17 erroneously detects a signal similar to the bit synchronization signal as the bit synchronization signal, the second mute circuit operates, and the telephone call is interrupted.

Therefore, in order to solve the above-mentioned inconvenience, a first frequency of selecting a frequency that does not cause a malfunction of voice as a subcarrier
And the second method of increasing the number of bits of the bit synchronization signal to be detected have been proposed.

[Problems to be solved by the invention]

However, in the case of the above-mentioned first method, the voice band of the land mobile station is 300 Hz to 3 kHz, and it is possible to reduce the voice malfunction depending on how to select the frequency of the subcarrier, but the frequency of the subcarrier is the voice band. It is inside and cannot be completely prevented. In addition, the second
In the case of method 2, since it takes time to enter the mute operation,
The time for which the data signal sound is generated becomes long, which is contrary to the original purpose of the mute circuit of erasing the data signal sound.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a mute circuit that prevents malfunction due to voice during a call.

[Means for solving problems]

In order to achieve the above-mentioned object, according to the present invention, as shown in FIG. 1, a mute circuit of a receiver for FSK, a switching means E for opening / closing a transmission path of an audio frequency signal, and a high frequency High frequency signal detecting means A for detecting a signal
A predetermined time setting means B for setting a predetermined time, a bit synchronization signal detection means C for detecting a bit synchronization signal, and a predetermined time setting means B from the time when the high frequency signal detection means A detects a high frequency signal. A mute circuit is provided which comprises a control means D for opening the switching means E when the bit synchronization signal detection means C detects a bit synchronization signal within the predetermined time.

[Work]

When the high frequency signal detecting means A detects the high frequency signal, that is, when the predetermined time set by the predetermined time setting means B is exceeded from the time when the radio wave arrives, even if the bit synchronizing signal detecting means C detects the bit synchronizing signal, the control is performed. The means D do not open the switching means E. This allows
Audio malfunction of the mute circuit is prevented.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of an FSK receiver to which the first embodiment of the mute circuit according to the present invention is applied. In the figure, reference numeral 10 denotes a demodulation circuit. This demodulation circuit 10 demodulates a high frequency signal into an audio frequency and uses the demodulated audio frequency signal as a demodulation signal d for a noise squelch circuit.
15, the decoder 16 and the first mute switch (SW) 11 are supplied. The noise squelch circuit 15 receives the demodulated signal d
The presence or absence of a high-frequency signal is detected from the noise inside, and when the arrival of the high-frequency signal is detected, the noise squelch control signal e of "L" level or "H" level when not detected is output to the first mute switch 11 and the delay circuit 18. Supply to. Then, the first mute switch 11 is opened when the "H" level noise squelch control signal e is supplied. The noise squelch circuit 15 corresponds to the high frequency signal detecting means A in FIG.

The decoder 16 converts the data signal in the subcarrier included in the demodulation signal d supplied from the demodulation circuit 10 into a digital signal and supplies the digital signal to the microprocessor (MPU) 17. MPU17
Processes the digital signal supplied from the decoder 16 and supplies a "H" level detection signal f to one input terminal of the AND circuit 19 for a predetermined time when a bit synchronization signal is detected in the digital signal. The decoder 16 and MPU 17 correspond to the bit synchronization signal detecting means C in FIG.

The delay circuit 18 supplies a delay signal g obtained by delaying the noise squelch control signal e supplied from the noise squelch circuit 15 by a predetermined time to the other input terminal of the AND circuit 19, and the delay circuit 18 It corresponds to the predetermined time setting means B in FIG.

When the AND circuit 19 is supplied with the "H" level detection signal f and the delay signal g at its input terminals, it outputs the "H" level mute control signal h to the second mute switch (SW) 12. Supply. The AND circuit 19 and the second mute switch 12 correspond to the control means D and the switching means E in FIG. 1, respectively.

Reference numeral 13 denotes an AF amplifier, and this AF amplifier 13 is provided from the demodulation circuit 10 to a first mute switch 11 and a second mute switch 12.
The audio frequency signal supplied via the speaker is amplified and output to the speaker 14 to cause the speaker Б to ring.

In FIG. 2, the part surrounded by the broken line is the mute circuit according to the present invention.

Next, the operation of the above configuration will be described with reference to the timing chart shown in FIG. In the figure, (A),
(B) and (C) do not show the waveforms of the high-frequency signal, the data signal, and the audio signal, but show the presence or absence of those signals.

First, when the receiver does not receive the high frequency signal, that is, when the demodulated signal d includes only noise as shown in the region I of (D), the noise squelch circuit.
Reference numeral 15 outputs a noise squelch control signal e (see (E)) of "H" level. As a result, the first mute switch 11 is opened and the mute operation is performed.

Next, when a high frequency signal arrives, the noise squelch circuit 15
Detects the arrival of a high-frequency signal from the demodulated signal d and sets the noise squelch control signal e output by the high-frequency signal to the “L” level (see (E)). As a result, the first mute switch 11 is closed.

By the way, the high frequency signal is composed of a data signal and a voice signal (see (A), (B), (C) and (D)), and the data signal (region II of (D)) is transmitted first. Come on. Then, the MPU 17, when detecting the bit synchronization signal forming a part of the data signal in the digital signal supplied from the decoder 16, a predetermined time, that is, the time required to detect the bit synchronization signal from the time required to transmit the data signal. "H" level detection signal f ((F))
Is supplied to one input terminal of the AND circuit 19.

A delay signal g is supplied from the delay circuit 18 to the other input terminal of the AND circuit 19, and the delay signal g has a predetermined time for the noise squelch control signal e, that is, the time required for transmitting the data signal in this embodiment. It was delayed only. Therefore, as shown in (G), the delayed signal g is at "H" level at least from the arrival of the high frequency signal to the end of the reception of the data signal, but after the end of the reception of the data signal, At least while the high frequency signal is being received, the delay signal g is at "L" level. As a result, MPU1
While 7 receives the data signal after detecting the bit sync signal, the mute control signal output from the AND circuit 19 becomes "H" level, and the second mute switch 12 is opened.
Mute operation is performed. As a result, the data signal sound is erased.

After receiving the data signal, the audio signal (area (D) II)
Since the noise squelch control signal e and the mute control signal h are both at the “L” level when shifting to the reception of I), the first mute switch 11 and the second mute switch 12 are both closed, and the mute operation is performed. Is released. As a result, a voice call becomes possible. Moreover, for example, time t ₁
Even if the MPU 17 erroneously detects the audio signal as a bit synchronization signal and outputs a detection signal of "H" level (see (F)), the delay signal g is at "L" level, so the mute control signal h is Since the second mute switch 12 continues to be in the closed state because it remains at the "L" level, the voice call is not interrupted.

An example of a concrete circuit of the delay circuit 18 is shown in FIG. The delay circuit shown in FIG. 4 is publicly known.

FIG. 5 is a block diagram of an FSK receiver to which the second embodiment of the present invention is applied. This second embodiment is the second
The delay circuit 18 and the AND circuit 19 of the first embodiment shown in the drawing
The operation of is processed by the program of MPU27. Throughout the drawings, the same or similar parts are designated by the same reference numerals. The part surrounded by the broken line is the mute circuit according to the present invention.

The mute operation of the MPU 27 used in the second embodiment shown in FIG. 5 will be described below with reference to the flowchart shown in FIG.

First, in step 601, it is determined whether or not a high frequency signal is sensed based on the noise squelch control signal supplied from the noise squelch circuit 15, and the determination result is affirmative (YE
In the case of S), that is, when a high frequency signal is detected, the process proceeds to step 602, and in the case of a negative (NO), the process returns.
stand by.

In step 602, the internal timer in the MPU 27 is set to t =
At the same time as resetting to 0, start timing.

Next, in step 603, it is determined whether or not a bit synchronization signal is detected in the digital signal supplied from the decoder 16. If the determination result is affirmative, that is, if the bit synchronization signal is detected, the process proceeds to step 604. On the other hand, if the result is negative, the process returns to step 601.

In step 604, it is determined whether or not the elapsed time t after the internal timer starts counting, in other words, the elapsed time t from the time when the bit synchronization signal is detected is less than the predetermined time t ₀ , and the determination result is affirmative. In this case, that is, when the elapsed time t is less than the predetermined time t ₀ , the routine proceeds to step 605, where the mute operation for outputting the “H” level control signal to the second mute switch 12 is executed. The predetermined time t ₀ is a time obtained by subtracting the time required for detecting the bit synchronization signal from the time required for transmitting the data signal, and is set in advance as described in the description of the first embodiment. Is possible.

Next, at step 606, the elapsed time t is the predetermined time t _0.
If the determination result is negative, that is, if the elapsed time t has not reached the predetermined time t ₀ , the process returns to step 605 to continue the mute operation. As a result, the data signal sound is erased. Then, when the elapsed time t reaches the predetermined time t ₀ (the determination result of step 606 is affirmative), the process proceeds to step 607 to cancel the mute operation.

Next, in step 608, it is determined whether or not there is a high frequency signal. If the determination result is affirmative, that is, if a high frequency signal is being received, it is determined that a voice call is in progress, and the process returns to step 607 to mute. Continue releasing the motion. As a result, the mute operation does not occur during the voice call. On the other hand, if the result of the determination in step 608 is negative, it is determined that the call has ended, and the process returns to step 601.

If the determination result of step 604 is negative, the process proceeds to step 607.

〔The invention's effect〕

As described above, according to the mute circuit of the present invention,
Since the mute operation is performed only for a predetermined time from the arrival of the high frequency signal, it is possible to prevent malfunction due to voice during a call.

[Brief description of drawings]

FIG. 1 is a block diagram of the principle of the present invention, FIG. 2 is a block configuration diagram of an FSK receiver to which the first embodiment of the present invention is applied, FIG. 3 is a timing chart, and FIG. 4 is a delay circuit. A specific circuit diagram, FIG. 5 is a block diagram of an FSK receiver to which the second embodiment of the present invention is applied, FIG. 6 is a flowchart, and FIG. 7 is a conventional mute circuit. It is a block configuration diagram of a receiver for FSK that is. 14 …… Speaker, 17,27 …… Microprocessor (MPU), 19 …… And circuit.

Claims (1)

[Claims] 1. A mute circuit for an FSK receiver, comprising switching means for opening and closing an audio frequency signal transmission path, high frequency signal detecting means for detecting high frequency signals, and predetermined time for setting a predetermined time. Setting means, bit period signal detecting means for detecting a bit synchronizing signal, and the bit synchronizing signal detecting means within a predetermined time set by the predetermined time setting means from the time when the high frequency signal detecting means detects the high frequency signal. A mute circuit comprising: a control unit that opens the switching unit when a bit synchronization signal is detected.