JPH0799809B2 - Signal conversion circuit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal conversion circuit for converting a digital signal into an analog signal, and particularly to a digital signal with a small number of bits for a digital signal subjected to differential processing and range companding processing. /
The present invention relates to a signal conversion circuit that converts an analog signal using an analog converter.

[Background Art and its Problems] For example, from a digital PCM signal obtained by sampling an analog audio signal or an analog video signal, that is, performing quantization and encoding, a sound source device of a digital electronic musical instrument, or the like. It is necessary to finally convert the generated digital PCM signal or the like into an analog signal by using a digital / analog converter (D / A converter). This D / A converter generally has a complicated structure, and the price thereof sharply rises when the number of bits of the input digital signal exceeds 12 bits. This is due to the fact that the clock becomes faster, that a highly accurate resistor is required, and that the circuit configuration becomes extremely complicated.

However, in order to reduce the quantization error and widen the dynamic range, it is necessary to increase the number of bits per word of the digital PCM signal, that is, the so-called word length. In the case of a signal having a large peak factor such as a digital musical tone signal, for example, a word length of about 20 bits is required.

By the way, in the digital PCM signal corresponding to the analog signal, by utilizing the fact that the statistical properties thereof are biased and there is a part of low importance in view of the audiovisual phenomenon,
It is known that the amount of information can be compressed, and that signal quality deterioration is extremely small even if, for example, difference / sum processing and range compression / expansion processing are performed.

[Object of the Invention] In view of the above situation, the present invention provides a multiplication D / A with a small number of bits for a digital signal subjected to difference processing and range compression.
By converting to an analog signal using a converter and analog integrator circuit, a virtually simple multi-bit D / A conversion is possible with a relatively simple and inexpensive circuit configuration without using an expensive multi-bit D / A converter. It is an object of the present invention to provide a signal conversion circuit capable of

[Summary of the Invention] That is, the features of the signal conversion circuit according to the present invention are that a digital signal subjected to difference processing and range processing is input, and mantissa data displayed in floating point by the range processing and this floating point display. A multiplication type digital / analog converter for obtaining an addition value of the signal obtained by analog conversion of the exponent part data as an analog signal, and an analog signal from the addition digital / analog converter are inputted,
And an analog integrating circuit having an integration characteristic corresponding to an inverse characteristic of the characteristic by the difference processing and having a characteristic of compensating each saturation characteristic on the low frequency side and the high frequency side in the difference processing. That is.

Therefore, the digital signal whose word length has been shortened is not D / A converted without deteriorating the signal quality by the difference processing and range processing, and the range restoration is performed at the time of this D / A conversion, and the difference is obtained by analog integration. Since the processing is restored, a digital signal with a long word length can be efficiently converted into an analog signal by using a D / A converter having a small number of bits. Further, the transfer characteristic in the analog integration can be a characteristic that compensates for the saturation characteristic on the low frequency side and the high frequency side, which is a highly accurate inverse characteristic to the transfer characteristic in the digital difference processing. It is possible to provide a signal conversion circuit having a good flatness as an overall frequency characteristic and obtain a high quality analog signal.

[Embodiment] Hereinafter, a preferred embodiment of the signal conversion circuit according to the present invention will be described with reference to the drawings.

FIG. 1 is a block circuit diagram showing a first embodiment of the present invention. In FIG. 1, the input terminal 1 is supplied with a digital signal having a sampling frequency, that is, a sampling frequency of f _s and one word of, for example, 20 bits. This digital signal is a sampling frequency of the analog audio signal or analog video signal as the original input signal.
It is a digital PCM signal obtained by sampling at f _s and further by performing quantization and sampling, or a digital PCM signal output from a sound source device of a digital electronic musical instrument, etc., and finally D / It is necessary to perform A conversion (digital / analog conversion) to restore the original analog signal. By the way, the number of bits per word of the sampling data of the digital PCM signal supplied to the input terminal 1 is as large as 20 bits.
Direct D / A conversion (digital / analog conversion) of the digital signal of the word 20 bit makes the circuit scale of the D / A converter extremely large, the yield in mass production is poor, and the price is extremely high. As described above, it becomes expensive.

Here, in the first embodiment of the present invention shown in FIG. 1, a digital signal of, for example, 1 word and 20 bits from the input terminal 1 is sent to the difference processing circuit 2, and the output from the difference processing circuit 2 is range compressed. , Especially to the range processing circuit 3 which performs instantaneous compression.

The difference processing circuit 2 has a circuit configuration for taking a primary difference as shown in FIG. 2, for example. In FIG. 2, the input data x _i (i is a word number according to the time sequence of the sampling data) is sent to the adder 21 and is multiplied by the coefficient k in the coefficient multiplier 22 and in the delay element 23. The data kx _i-1 delayed by one sample period is sent to the adder 21 as a subtraction input, so that the output data y _i from this adder 21 becomes y _i = x _i −kx _i−1 . The word length of the output data y _i subjected to this difference processing,
That is, the number of bits in one word is determined by what the maximum value is. This maximum value occurs when _one of the time-adjacent data x _i , x _i-1 of the input data string is positive and the other is negative, and is a value that is twice the maximum value of the input data. . Therefore, the word length of the input data,
For example, it is set to be 1 bit longer than 20 bits, for example, 21 bits. However, in general, when differential processing of sampling data of an analog signal is performed, most of data values, for example,
99% or more can be expressed with a sufficiently smaller number of bits than the input data, and effective bit reduction is performed.

Next, the range processing circuit 3 displays, for example, 21-bit data for one word, which has been subjected to the difference processing, by so-called floating point (floating point) display, for example, with 9 bits of mantissa and 4 bits of exponent, and the range processing is performed. The mantissa data as the input digital signal is input to the absolute value calculating circuit 4, and the exponent data as the range information is input to the D / A converter 5.
To each of them. The example in which the mantissa part is 9 bits is given here because it is assumed that an 8-bit D / A converter, which is widely used as a multiplication D / A converter 6 described later, is assumed. , When extracting the 9-bit mantissa part from the 21-bit input data, as described later, 4
The exponent part of the bit is required. Of course, the number of bits of these input data, the number of bits of the mantissa part, or the number of bits of the exponent part is not limited to the above example.

Here, a specific example of the range processing circuit 3 will be described with reference to FIG.

Fig. 3 shows 21-bit data represented in 2's complement as 9
A specific example in the case of representing the mantissa part D _m of bits and the exponent part D _{i of} 4 bits is shown. In the above two's complement display, the most significant bit (MSB) represents a positive or negative sign, and the MSB is "1".
Indicates a positive number, and "0" indicates a negative number.
In FIG. 3, each bit of 21 bits is sequentially set as b _{0 to} b ₂₀ from the least significant bit (LSB) side to the MSB side, and the bit represented by “x” in the figure is “1” or “1”. It indicates that any value of "0" may be used.

First, in FIG. 3A, when the input data of 1 word 21 bits is a positive number, in general, the decimal point is moved or shifted by k bits to the MSB side, and the 9-bit mantissa part is moved from the decimal point to the MSB side. An example of extracting from 21 bits is shown. That is, when the bit b ₂₀ of the MSB of 21-bit data of one word is a positive number that is “0”, the smaller the data value is, the greater the number of “0” consecutive from the MSB side to the LSB side becomes. The significant digits are the bits after "1" appearing. However, it is necessary to add a bit for representing the positive and negative signs to the most significant bit. Therefore, in FIG.
In this example, the bit b in _{k + 8} is "0", the bit b _{k + 7} and the first "1" appears from the MSB side to the mantissa 9 bits in this case from bit b _k to bits b _{k + 8} Take out as part D _m ,
As the exponent part D _i , a 4-bit binary number representing the bit shift amount k is taken out. FIG. 3 shows B, C, and D, and the case where the bit shift amount k is 0, 5, and 12, respectively. For example, if the bit in which "1" first appears from the MSB side of 21-bit data is bit b ₇ or less, that is,
When at least up to the bit b ₈ "0" continues from the MSB side, as shown in B of FIG. 3, the mantissa of the 9-bit bit shift amount bits b ₀ ~b ₈ from the LSB side as 0 , And a 4-bit binary number “0000” representing the bit shift amount is extracted as the exponent part. In the case of "1" appears data initially a bit b ₁₂ consecutive "0" from the MSB side, as shown in C of FIG. 3, the bit b ₅ ~b the bit shift amount of 5 The 9 bits of ₁₃ are taken out as the mantissa part, and the 4-bit binary number “0101” representing the bit shift amount is taken out as the exponent part. Further, when "1" appears in the bit b ₁₉ next to the MSB of the 21 bit data, as shown in D of FIG. 3, the bit shift amount as 12,
9 bits from bit b ₁₂ to MSB b ₂₀ are taken out as a mantissa part, and a 4-bit binary number “1100” representing a bit shift amount is taken out as an exponent part.

Further, E in FIG. 3 shows an example in which a 9-bit mantissa part is generally taken out by shifting by k bits when the MSB is a negative number which is "1". That is, in the case of a negative number, "1" continues from the MSB side to the LSB side of 21-bit data, and the significant digits are the bits after "0" appears first. However, since 1 bit of the sign bit is arranged at the beginning (upper order), 9 bits taken out as the mantissa part
b _k bit b _{k + 8} most significant of the ~b _{k + 8} is made to be "1" in the above-mentioned for the first time appear in the next bit b _{k + 7} "0" is arranged.

The range processing circuit 3 in FIG. 1 extracts the 9-bit mantissa part and the 4-bit exponent part as described above,
Specifically, for example, the MSB value of the input 21-bit data is detected to determine the positive / negative sign, the MSB to LSB is searched for a bit having a value different from this MSB value, and the difference The consecutive 9 bits such that the first bit is the second bit from the upper side, for example, b _{k to} b _{k + 8} are taken out as the mantissa part, and the least significant bit b _k of these 9 bits and the original 21
The shift amount k as a difference from the LSBb ₀ of the bit is expressed in binary as 4 bits and extracted as an exponent part.

In such a range processing circuit 3, the input 21
By representing the bit data by the 9-bit mantissa part and the 4-bit exponent part, even if the instantaneous dynamic range is equivalent to 9 bits, the 4-bit exponent part makes the lowest 9 bits of 21 bits. Since bits b _{0 to} b ₈ to the most significant 9 bits b _{12 to} b ₂₀ can be expressed, a dynamic range equivalent to 21 bits can be obtained as a whole.

Next, the absolute value calculation circuit 4 calculates the absolute value of, for example, 9-bit data including the positive and negative signs obtained from the range processing circuit 3, and outputs the absolute value data of, for example, 1 word and 8 beats. , To the multiplication type D / A converter 6. Multiplying D / A
The above-mentioned exponent data is input to the multiplication signal input terminal of the converter 6.
The multiplication signal converted into the analog signal as the exponential function value by the D / A converter 5 is input, and the multiplication type D / A converter 6
Converts the multiplication value of the data value from the absolute value calculation circuit 4 and the multiplication signal value into an analog signal and outputs the analog signal.

As such a multiplication type D / A converter 6, a resistance ladder type D
A / A conversion circuit, weighting resistance type D / A conversion circuit, integration type D / A conversion circuit, current addition type D / A conversion circuit, etc. can be used, and the reference current source and reference voltage source in these circuit configurations can be used. The terminal for adjusting or variably controlling is used as the multiplication signal input terminal.

Here, a specific example of the case where an integral type D / A conversion circuit is used as the multiplication type D / A converter 6 will be described with reference to FIG.

In FIG. 4, the integral type D / A converter 30 used as the multiplication type D / A converter 6 is the absolute value calculation circuit 4 described above.
, For example, 8 data input terminals 31A to 31H to which 8-bit absolute value data is input, an 8-bit binary counter for counting a constant frequency clock from the clock input terminal 32, a counter 33, and the data input terminal Digital comparator 34 for comparing 8-bit absolute value data from 31A to 31H with 8-bit count data from the counter 33
And a switch 36 which is connected to the reference voltage input terminal 35 through a resistor and is ON / OFF controlled according to the comparison output from the comparator 34, and the output from this switch 36 is supplied to the non-inverting input terminal. Comprising an editing amplifier (op amp) 37, an integrating capacitor 38 connected between the non-inverting input terminal and the output terminal of the operational amplifier 37, and an analog switch 39 connected in parallel to the integrating capacitor 38. From the output terminal 40 of the operational amplifier 37, the D / A converted analog signal is taken out. Further, a control signal as shown in FIG. 5A synchronized with the switching timing of the 8-bit absolute value data is supplied to the counter 33, the comparator 34 and the switch 39 via the terminal 41. At time t _{1 when} this control signal (FIG. 5A) changes from “L” (low level) to “H” (high level), the switch 39 is discharged, and the output voltage from the output terminal 40 is changed to FIG. 5C. It rapidly drops to 0V as shown in. Next, when the control signal (FIG. 5A) changes from “H” to “L” at time t ₂ , the switch
When 39 is turned off and the counter 33 starts counting and the comparator 34 starts operating, the output from the comparator 34 changes from “L” to “H” as shown in FIG. 5B. The switch 36 is turned on by this comparison output. While the switch 36 is ON, a constant current obtained from the reference voltage terminal 35 via the resistor via the switch 36 is integrated by the operational amplifier 37 and the integrating capacitor 38, and the output terminal
The output voltage from 40 appears to be proportional to the elapsed time as shown in FIG. 5C. In this case, the input data from the output data and the input terminal 31A~31H from the counter 33 are compared by the comparator 34, the comparator at time t ₃ when the count output data matches to the input data from the counter 33 The output from 34 is "H" as shown in Fig. 5B.
Changes to "L", the switch 36 is turned off, and the integration operation is stopped. Therefore, after time t ₃ ,
A voltage proportional to the numerical value of the input data to the input terminals 31A to 31H is obtained from the output terminal 40. A so-called down counter is used instead of the counter 33 and the comparator 34, and the input data from the input terminals 31A to 31H is down-converted as described above.
It may be preset in the counter and the clock may be counted until the count value becomes zero.

By the way, the output terminal 4 of such an integral D / A conversion circuit 30
The output voltage from 0 depends not only on the input data to the input terminals 31A to 31H but also on the input voltage to the reference voltage input terminal 35. That is, for example, in FIG. 4, the time during which the switch 36 is ON is determined by the output from the comparator 34 according to the value of the input data to the terminals 31A to 31H. The voltage supplied by
This is because it becomes the voltage from the reference voltage input terminal 35. The reference voltage input terminal 35 is supplied with an output from the D / A converter 5 which converts the exponent part data from the range processing circuit 3 into an analog signal as an exponential function value.

As the simplest D / A converter 5, a configuration as shown in FIG. 4 can be considered. In FIG. 4, the 4-bit exponent part data is transferred to four data input terminals 45A.
.About.45D to the decoder 46, and the decoder 46 obtains n outputs corresponding to the binary values of the exponent part data. This n can be up to 16 in the case of 4-bit input, but in the range processing circuit 3, 21-bit input data is converted into 9-bit mantissa data as described with reference to FIG. Therefore, 13 is enough.
This is the least significant bit b ₀ shown in B of FIG. 3 as a method of extracting 9 consecutive bits from 21 bits.
From the upper 9 bits b _{0 to} b ₈
From when the shift amount is 0, i.e. the exponent part data is "0000", bit shift taking out 9 bit b ₁₂ ~b ₂₀ from 13 bit b ₁₂ shown in D of FIG. 3 to the most significant bits b ₂₀ This is because there are 12 possible quantities, that is, 13 ways until the exponent data is "1100". That is, the decoder 46 may select any one of the 13 outputs according to the 4-bit input data. The D / A converter 5 is supplied with 8-bit data which is the absolute value of the 9-bit mantissa data. Further, the D / A converter 5 is provided with _n switches 47 ₁ , 47 ₂ , ..., 47 _n that are ON / OFF-controlled according to the n outputs from the decoder 46, respectively. these switches 47 _1, 47 _2, ..., 47 resistors in each one of _n R _1, R _2, ..., R _n are connected. A reference voltage V _REF is applied to the resistors R _{1 to} R _n via a terminal 48, and the other ends of the switches 47 _{1 to} 47 _n are commonly connected to each other, and the integration type D / It is connected to the reference voltage input terminal 35 of the A conversion circuit 30.

In addition, inside the multiplication type D / A converter 6, the D / A converter 5 of FIG.
The multiplication type D / A converter that outputs the analog signal according to the multiplication value of the 4-bit exponent part data and the 8-bit absolute value data may be obtained by including the above configuration. The configuration in this case is such that the D / A converter 5 in the configuration of FIG. 1 is omitted, and the 4-bit exponent part data from the range processing circuit 3 is directly sent to the multiplication type D / A converter 6. Will be things.

Next, the analog output from the multiplication D / A converter 6 is sent to an analog integration circuit 7 for performing a summing operation in contrast to the difference processing circuit 2. The analog integrating circuit 7 has a polarity control function according to positive and negative signs, and the simplest circuit configuration example is shown in FIG. In FIG. 6, an analog signal from the multiplication D / A converter 6 is supplied to the input terminal 51, and this analog signal is directly supplied to one selected terminal a of the analog conversion switch 52 and , The analog signal is supplied to the other selected terminal b through an amplifier having a gain of -1, that is, an analog inverter 35. Analog selector switch 52
Is switched and connected to either one of the selected terminals a and b in accordance with the positive or negative sign data from the polarity switching control terminal 54, and the output from the analog changeover switch 52 is supplied to the analog integration circuit main body 55. By doing so, an integrated output of either positive or negative polarity is obtained. The above terminal 54 at this time
Positive and negative sign data to the absolute value calculation circuit 4 of FIG.
It may be taken out from the input side of or the input side of the range processing circuit 3.

By the way, the integration characteristic of the analog integration circuit 7 is
It is desirable to approximate the inverse characteristic of the transfer characteristic by the digital difference processing in FIG. 2 and the difference processing circuit 2 as close as possible. Here, when the relationship between the input x and the output y in the difference processing circuit 2 is expressed by using z ⁻¹ ≡e ^−jωTs (where T _s is a sampling cycle), it becomes y = (1-kz ⁻¹ ) x. The transfer characteristic of the difference processing circuit 2 is y / x = 1-kz ^-1 . Here, the sampling frequency f _s, the input signal frequency is f, from expressed as ωT _s = 2πf / f _s, the transfer characteristic, y / x = 1-ke -j2πf / fs , and the seventh Figure A characteristic similar to the differential characteristic such as A is obtained. In A of FIG. 7, a virtual line indicates an ideal differential characteristic or an analog differential characteristic, and the actual characteristic curve of the difference processing circuit 2 is a coefficient k on the low frequency side as shown by the solid line of A of FIG. Due to the saturation, and the saturation due to digital processing occurs on the high frequency side.

That is, on the low frequency side, when f in the above formula is brought close to 0, y / x comes close to 1-k, and when k has a value smaller than 1, it does not converge to 0 but converges to a fixed value. Therefore, saturation occurs on the low frequency side.

Further, on the high frequency side, the higher the frequency of the input signal, the larger the error between the analog differential output and the digital differential output, and the maximum value of the digital differential output appears smaller than the maximum value of the analog differential output. On the high frequency side, the saturation of the digital differential characteristic occurs with respect to the analog differential characteristic.

The saturation on the high frequency side will be described with reference to FIG. Focusing on the sampling points x _i in FIG. 8, the analog differentiation outputs the tangent slope at the points x _i on the input signal waveform, whereas the digital differences sample points x _{i on the} input signal waveform. Since the difference from the point x _i-1 one sample before is output for, as shown in A and B of FIG.
The higher the frequency of the input signal, the larger the error between the analog differential output and the digital differential output, and the maximum value of the digital differential output appears smaller than the maximum value of the analog differential output. That is, in the case of the high-frequency signal shown in FIG. 8A, even if the gradient at the sample point x _i is steep and the differential value is large, the sampling interval is wide with respect to the change in the waveform, so the difference value is generally It becomes smaller than the differential value, and the error increases. Therefore, on the high frequency side, the digital differential value appears smaller than the analog differential value, and the error increases as the frequency increases, and saturation of the digital differential characteristic occurs with respect to the analog differential characteristic.

Therefore, the analog integrator circuit 7 is required to have an integration characteristic for the reverse processing including the saturation characteristics on the high frequency side and the low frequency side. This integral characteristic is as shown by the solid line of B in FIG. 7, which is obtained by reversing the curve of the digital difference characteristic F (f) shown by the solid line of A in FIG.
Saturation occurs on the low frequency side and high frequency side.

That is, a simple or ideal analog integration characteristic I as shown by a broken line in B of FIG. 7 is applied to a signal on which the difference processing of the characteristic F (f) shown by a solid line of A in FIG. 7 is performed.
When the integration process of (f) is performed, the original signal cannot be restored. Therefore, as shown by the solid line integral characteristic G (f) in FIG. 7B, a characteristic curve in which saturation occurs on the low frequency side and the high frequency side is used to determine the difference characteristic F (f) on the low frequency side. Also, it is necessary to compensate for saturation on the high frequency side. At this time, the cutoff frequency on the low frequency side of the characteristic G (f) is matched with the cutoff frequency on the low frequency side of the characteristic F (f), and the cutoff frequency on the high frequency side of the characteristic G (f) is Characteristic F (f)
It is necessary to match the cutoff frequency on the high frequency side of. The frequency of each change point in the saturated portion of the characteristic curve on the low frequency side and the high frequency side is called a cutoff frequency or turnover frequency. In FIG. 7, the cutoff frequency on the low frequency side is cut off. The frequency is f _c1 and the cutoff frequency on the high frequency side is f _c2 .

Here, qualitative operation based on the circuit configuration will be described first with respect to the point that the integrating circuit 55 shown in FIG. 6 obtains an integrating characteristic for compensating for the saturation on the low band side and the high band side.

Capacitor 55a (capacity C), resistor 55c (resistance value R in FIG. 6)
If the impedance of the parallel circuit of the series circuit of c) and the resistance 55b (resistance value Rb) is Z and the resistance value of the input resistance is Rin, the gain of the integrating circuit 55 is Z / Rin. As for the overall frequency characteristics, the higher the frequency, the more the capacitor 55a
Since the impedance of is decreased, the gain is decreased and the characteristic curve is downward-sloping.

Next, considering the characteristics on the low-frequency side and the high-frequency side, the impedance of the capacitor 55a becomes extremely large on the low-frequency side, so that the impedance Z of the parallel circuit is almost a resistance.
The resistance value of 55b becomes Rb, and the gain of the integrating circuit 55 approaches a constant that does not depend on the frequency of Rb / Rin, so that the frequency characteristic becomes flat. This corresponds to the saturation characteristic on the low frequency side. Further, on the high frequency side, the impedance of the capacitor 55a becomes extremely small, so the impedance of the series circuit of the capacitor 55a and the resistor 55c becomes substantially equal to the resistance value Rc of the resistor 55c, and the impedance Z of the parallel circuit is the resistor 55c.
And the resistance 55b become parallel impedance and the integration circuit 55
The gain of becomes a constant. This corresponds to the saturation characteristic on the high frequency side. Therefore, the cutoff frequency f _c1 on the low frequency side is determined by the resistance value Rb of the resistor 55b, and the cutoff frequency f _c on the high frequency side is
Strictly speaking, _c2 depends on the resistance value Rc of the resistor 55c
It will be determined by the parallel resistance value with 55b.

Next, the relationship between the cutoff frequencies on the low band side and the high band side, the coefficient k, and the sampling frequency f _s will be considered. First, Here, the cutoff frequency or turnover frequency, which is the change point of the frequency characteristic curve due to saturation on the low frequency side, is obtained. This cutoff frequency is defined as the frequency at the point where the linear part of the characteristic curve is extended by 3 dB, and 3 dB on the logarithmic axis is Considering that, for the above ideal fine powder characteristics, The frequency of | y / x | Since the ideal differential characteristic is equal to | y / x | in the case of k = 1 on the low frequency side, the following equation holds. That is, Is. in this case, However, f _c1 is the low cutoff frequency. If the coefficient k is determined by this, the difference processing circuit 2
A cutoff frequency f _c1 indicating saturation on the low frequency side of the characteristic curve of is determined, and the low frequency cutoff frequency of the analog integrator circuit 7 is set to this frequency f _c1 , so that the low frequency side of the differential processing characteristic The saturation can be compensated.

Next, the high cutoff frequency will be considered. First,
As the present inventor has described in the specification and drawings of Japanese Patent Application Sho 58-98687 previously proposed (see Japanese Patent Kokoku 5-74253), the frequency at which the gain of the differential characteristic becomes 1 f _s / 6 Therefore, the ideal analog differential characteristic D (f) at which the gain is equal to 1 at this frequency is D (f) = (6 / f _s ) · f. Here, in order to obtain the frequency of the digital differential characteristic | y / x |, which is 3 dB lower than the analog differential characteristic D (f), from the definition of the cutoff frequency, If you calculate it, Here, since θ = 2πf / f _s , it is set as f / f _s ≡g, and g ² = (1-cos2πθ) / 9 where 0 <g <1 g (= f / f the value of _s) of, as is apparent from the graph of FIG. 9, becomes 0.4692, the high frequency side cutoff frequency f _c2 of the analog integrator circuit 7, in accordance with the sampling frequency f _s, f _c2 = 0.4692f _s Becomes Here, FIG. 10 shows the digital difference characteristic (broken line) and the high-frequency side cutoff frequency f when f _s = 32 kHz.
The analog differential characteristic (solid line) is shown when _c2 is 0.4692 _fs , that is, approximately 15 kHz. The difference between these characteristic curves is within 0.5 dB at high frequencies, and they match with high accuracy.

When the analog integrating circuit configuration as shown in FIG. 6 is used, the low cutoff frequency f _c1 can be determined by the resistor 55b connected in parallel to the capacitor 55a of the integrating circuit body 55, and The high cutoff frequency f _c2 can be determined by the resistor 55c connected in series with the capacitor 55a.

The output from the analog integrating circuit 7 is taken out from the output terminal 9 via the de-emphasis circuit 8 in FIG. 1, for example. The de-emphasis circuit 8 may be provided as necessary when the digital signal supplied to the input terminal 1 is pre-emphasized.

According to the signal conversion circuit as the first embodiment of the present invention as described above, a 4-word D / A converter 5 and an 8-bit multiplication are applied to a digital PCM signal having a long word length of 20 bits per word. Type D / A converter 6 can be used to convert to an analog signal. These D / A converters 5 and 6 have a simpler structure than 20-bit D / A converters, and have high mass production efficiency and are inexpensive. The signal conversion circuit of FIG. 1 as a whole can be supplied at a significantly lower cost than the 20-bit D / A converter. Moreover, by the difference processing and range processing focusing on the characteristics of the digital PCM signal, an extremely high-quality analog signal that is substantially comparable to 20-bit D / A conversion can be obtained from the output terminal 9. Also, the analog integration circuit 7 is positive,
Since the negative polarity control function is provided, it is only necessary to perform D / A conversion on the signal of 8-bit word length, which is the absolute value of the digital signal of 9-bit word length from the range processing circuit 3, and the multiplication type D / Since the number of bits of the A converter 6 is small, the load is reduced. Further, since the integration characteristic of the analog integrator circuit 7 is provided with a characteristic for compensating for the low-frequency side saturation characteristic and the high-frequency side saturation characteristic of the difference characteristic of the difference processing circuit 2, the total frequency of the entire signal conversion circuit is increased. The flatness of the characteristic becomes good, and a high quality analog signal can be obtained.

By the way, when transmitting a digital signal using an encoder and a decoder, it is possible to perform difference processing and range compression processing on the encoder side and transmit the range-compressed digital signal and range compression information. Is the absolute value calculation circuit 4 or D / A in FIG.
Only the configuration after the converter 5 may be provided on the decoder side.

The digital signal transmission method of Japanese Patent Application No. 58-97687 (see Japanese Patent Publication No. 5-74253) or the Japanese Patent Application No. 58-97688 (Japanese Patent Publication No. 5-74252) previously proposed by the present inventor. In the digital signal transmission device of), the encoder side performs difference processing and range compression processing (adaptive processing). In this case, the difference processing is one of several processing modes selected according to the input signal. Has become one of. For example, when the differential PCM mode and the general PCM, that is, the straight PCM mode are switched and selected according to the input signal, the information of the selected mode is transmitted, and the mode switching process is performed on the decoder side according to this mode information. There is a need. Therefore, the structure of the decoder is, for example, as in the second embodiment of the present invention shown in FIG.

In FIG. 11, the digital signal from the encoder as described above is supplied to the input terminal 61, and this digital signal is separated into four types of words in the multiplexer 62. That is, in the encoder of the technology of the above-mentioned prior application, sampling data is divided into blocks for each constant n words, and the PCM mode is selected and range compression is performed for each block for digital transmission. For each, for example, a reference word of 1 word 16 bits and a 1-bit mode information word for selecting either the differential PCM mode or the general (straight) PCM mode
For example, one word and four bits of range information (adaptive information) words are arranged one by one, and further, the range-compressed data of, for example, one word and eight bits is arranged in the above-mentioned fixed number of words (n-1 words to be exact). Then transmitted. Then, the multiplexer 62 of the encoder shown in FIG.
For example, the data of the number of words for one block, each word being 8 bits, is sent to the range reverse processing circuit 63, and the range is expanded in block units according to the range information word. Data, and these data are sent to the mode switching processing circuit 64. The mode switching processing circuit 64 includes a multiplexer.
The reference word and the mode information word extracted from 62 are supplied, and when the differential PCM mode is selected on the encoder side, the sum processing is performed to output general (straight) PCM data, and When the general (straight) PCM mode is selected on the encoder side, the reference word and the input data are output as they are. Therefore, the mode switching processing circuit 64 outputs 16-bit straight PCM data of one word, and this digital data may be supplied to the difference processing circuit 2 of FIG. 1 (however, the number of processing bits is different). . That is, the circuit section at the subsequent stage from the difference processing circuit 2 in FIG. 11 may be configured in the same manner as in FIG.
Corresponding parts are designated by the same reference numerals and description thereof is omitted. However, in the configuration of FIG. 11, the range processing circuit 3
Need only range-compress the 1-word 17-bit data from the difference processing circuit 2 in block units according to the 1-word 4-bit range information from the multiplexer 62. This range information is converted into a D / A converter. 5 may be supplied.
The range compression / expansion processing in block units is also referred to as block unit adaptive processing or quasi-instantaneous compression / expansion processing.

Next, FIG. 12 shows a third embodiment of the present invention, which shows a signal conversion circuit for receiving a digital broadcasting signal or the like using broadcasting hygiene. In the third embodiment, the digital input signal is one block of 32 words of quasi-instantaneous compression data represented by a floating point by a 10-bit mantissa part and a 3-bit exponent part.
Then, the mantissa data is sent to the quasi-instantaneous expansion circuit 72 via the input terminal 71, and the quasi-instantaneous expansion circuit 72 responds to the exponent data from the input terminal 73 in units of 32 words per block. The mantissa data is subjected to quasi-instantaneous expansion, and straight PCM data of 14 bits per word is output. The output data from the quasi-instantaneous expansion circuit 72 is sent to the difference processing circuit 2 of the signal conversion circuit having the same configuration as that of the first embodiment of FIG. 1 but different in the number of processing bits. However, the range processing circuit 3 in the third embodiment of FIG. 12 performs the quasi-instantaneous compression process in block units using the 3-bit exponent part data as range information, and the D / A converter 5 The above index part data is also sent to.

The present invention is not limited to the above-mentioned embodiment, and for example, the word length of the digital PCM signal after the difference processing, the word length of the range information signal after the range processing and the word length of the output digital signal, etc. may be changed as necessary. It can be set arbitrarily.
Also, the multiplication type D / A converter 6 that can output both positive and negative polarity signals is used, the absolute value calculation circuit 4 is omitted, and the analog integration circuit 7 does not have a positive or negative polarity control function. May be used.

EFFECTS OF THE INVENTION According to the signal conversion circuit of the present invention, when a digital signal having a large number of bits (word length) of one word is converted into an analog signal, differential processing and range compression processing are performed, and the number of bits is small. By using a multiplication type D / A (digital / analog) converter and an analog integrator circuit, D / A conversion can be performed efficiently and inexpensive supply becomes possible. In addition, by using an analog integrator circuit that has the characteristics of compensating for the high-frequency side characteristics and low-frequency saturation characteristics of digital difference processing, the frequency characteristics of the output analog signal after D / A conversion with respect to the input digital signal are made flat. It becomes possible to do.

[Brief description of drawings]

FIG. 1 is a block diagram showing the first embodiment of the present invention, and FIG.
FIG. 4 is a block diagram showing a concrete example of the difference processing circuit of FIG. 1, FIG. 3 is a diagram showing a concrete example of extracting mantissa data and exponent data from input data, and FIG. 4 is a multiplication of FIG. FIG. 5 is a block circuit diagram for explaining a concrete example of the type D / A converter, FIG. 5 is a time chart for explaining the operation of the circuit of FIG. 4, and FIG. 6 is a diagram of the first analog integrator circuit. FIG. 7 is a circuit diagram showing a specific example, FIG. 7 is a graph showing the transfer characteristics of the difference processing circuit and the analog integrator circuit of FIG. 1, and FIG. 8 is a graph for explaining the saturation phenomenon of the digital difference characteristics on the high frequency side. 9 and 10 are graphs used to calculate the high-side cutoff frequency of the analog integrator circuit of FIG.
FIG. 10 is a graph showing a comparison between digital differential characteristics and analog differential characteristics, FIG. 11 is a block diagram showing a second embodiment of the present invention, and FIG. 12 is a block showing a third embodiment of the present invention. It is a figure. 1, 61, 71 ... Digital signal input terminal 2 ... Difference processing circuit 3 ... Range processing circuit 4 ... Absolute value calculation circuit 5 ... D / A converter 6 ... Multiplying D / A converter 7 ... … Analog integration circuit 8 …… De-emphasis circuit 9 …… Analog signal output terminal

Continuation of front page (56) References JP-A-58-218227 (JP, A) JP-A-57-123730 (JP, A) JP-A-58-121824 (JP, A)

Claims (1)

[Claims] 1. A differential-processed and range-processed digital signal is input, and multiplication of the floating-point-displayed mantissa part data by this range-processing and the analog-converted signal of the floating-point-displayed exponent part data is performed. A multiplication type digital / analog converter that obtains a value as an analog signal, and an analog signal from the multiplication type digital / analog converter are input, have integration characteristics corresponding to the inverse characteristics of the characteristics by the difference processing, and An analog integrator circuit having a characteristic for compensating for each saturation characteristic on the low frequency side and the high frequency side in the differential processing.