JPH0827736B2 - Redundant processor system - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a dual processor system having dual processors and a backboard mounting these dual processors, and more particularly, to a dual processor system. The present invention relates to a dual processor system capable of easily deciding which side of the processor is the main system.

(Prior Art) FIG. 3 is a conceptual diagram showing a configuration of a conventional duplex processor system. In the figure, PC1 and PC2 are duplicated processors, and BB is these duplicated processors PC.
1, PC2 is, for example, a backboard mounted via a connector. In this system, the processor that has become operable first becomes the main system and executes control, and the other processor becomes the slave system and enters the standby state.

That is, when each of the processors PC1 and PC2 becomes operable, it activates the ready signals RDY1 and RDY2, and at that time, the control permission signals (IOCE1 and IOCE2) transmitted from the other side via the lead wire on the backboard BB. ) Is inactive, gates (AG1, AG2), drivers (DR1, DR)
The control permission signal with itself as the main system is activated via 2).

As a result, if you activate the ready signal first, you can activate the control permission signal, and if you activate the ready signal later, the control permission signal from the other side is already active, so you can activate your own control permission. The signal cannot be activated and becomes a slave.

(Problems to be Solved by the Invention) In the conventional duplex processor system configured as described above, if there is a large delay in the path of the control permission signal transmitted via the lead wire on the backboard BB ( Propagation time between two processors simultaneously (due to propagation delay of gate, driver, capacitance of backboard) and closing driver that outputs control permission signal of other device at the same time. If you activate the ready signal within a much smaller time),
The control permission signals from the two processors become oscillated, causing a problem that the levels are not fixed.

Such an oscillating state naturally subsides after some time, but it takes time for one of the processors to reach a stable main system operation.

The present invention has been made in view of such problems,
The purpose is to realize a duplex processor system that determines the duplex control for deciding which side of the duplex processor is the main system in a short time even if two processors compete and realizes stable operation. To do.

(Means for Solving Problems) In the present invention for solving the above problems, a control permission signal (▲▲) to itself is provided according to a ready signal (RDY) of itself and a control permission signal from the other party. ▼ 、 ▲
) Is output, and the duplicated first and second processors equipped with (DR) and the duplicated first and second processors are mounted, one of which is the master system and the other of which is the slave system. And a backboard on which lead wires for transmitting a control permission signal to each other are arranged, wherein one end of the duplexed first and second processors is a driver output end. And a capacitor connected to the other end to indicate a mounting position of the processor from the backboard, one of which is common, and the other of which is provided with an open signal (▲ ▼, LOC2). A resistor is provided for pulling up each lead wire for transmitting a control permission signal for making one of the second processors a master system and the other a slave system to a voltage of a predetermined value. Constructed.

(Operation) When the ready signals are output from the two processors at the same time, the control enable signals IOCE1 and IOCE2 are once activated, but then on the backboard, the output end of the driver is connected to the common via the capacitor. The side where the capacitor is open rises gently with the time constant of CR, while the side where the other end of the capacitor is open rises immediately. This difference is used to eliminate the conflict when the ready signals are output at the same time.

Embodiments Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a configuration block diagram showing an embodiment of the present invention. In the figure, PC1 and PC2 are duplicated first and second processors, respectively, which send control permission signals to themselves according to their own ready signals RDY and control permission signals from the other side (▲ ▼, Equipped with drivers (DR1, DR2) that output ▲ ▼).

BB is a duplicated first and second processor PC
1 is a backboard in which PC2 is mounted, and lead wires L1 and L2 for transmitting control permission signals ▲ ▼ and ▲ ▼ for making one the main system and the other the slave system are arranged.

In the duplicated first and second processors PC1 and PC2, AG1 and AG2 are AND gates, which input their own ready signals (RDY1 and RDY2) and control permission signals (▲ ▼) from each other. , ▲
▼) is entered.

C1 and C2 are the duplicated first and second processors PC1 and P
In C2, one end is connected to the output ends of the drivers DR1 and DR2, and the other end is a capacitor to which a signal (▲ ▼, LOC2) indicating the mounting position of the processor is applied from the backboard BB. Here, one of the signals indicating the mounting position of the processor, IOC1, is a low-level signal connected to the common, and the other IOC2 is in the open state,
It is a high level signal.

In the backboard BB, R1 and R2 are the lead wires L1 and
One end is connected to L2 and is a resistor for pulling up the potential of the lead wire to a voltage of a predetermined value (for example, + 5V).

In the first and second processors, the output signal of each driver-DR becomes a control permission signal ▲ ▼, ▲ ▼ for determining whether or not the driver itself is the main system, and is applied to its own processor. , Is transmitted to the other processor side via the lead wire on the backboard BB.

The operation of the device configured as described above will be described below by dividing it into a normal state and a competitive operation.

(Normal operation; when ready signal RDY1 becomes active prior to RDY2) Ready signal RDY1 and ready signal RDY2 are both inactive initially, and output from AND gates AG1 and AG2 on each processor PC1 and PC2 side. Are both inactive.

For this reason, the output of each driver DR1, DR2 is initially ▲
Both ▼ and ▲ ▼ are inactive.

Here, when the ready signal RDY1 becomes active (high level) prior to RDY2, the output of the AND gate AG1 becomes high level, and the driver DR1 outputs the control enable signal ▲
Drive ▼ to active (low level).

After that, the ready signal RDY2 on the second processor PC2 side becomes active, but the AND gate AG2 on the second processor PC2 side is closed due to the control permission signal ▲ ▼ that has already been activated earlier. ,
Its output is not active and therefore the processor PC
2 is a subordinate system and is in a standby state.

(Normal operation; when ready signal RDY2 becomes active prior to RDY1) In this case, the same operation as described above is performed.

(Competitive operation; when ready signals RDY1 and RDY2 are activated almost at the same time) In this case, control enable signals ▲ ▼, ▲
When the ready signals RDY1 and RDY2 become active at the same time from the state where both ▼ are inactive, the two control permission signals ▲ ▼ and ▲ ▼ become active once.

FIG. 2 shows two control permission signals ▲ in this state.
FIG. 7 is a waveform chart showing the states of ▼ and ▲ ▼.

Two control permission signals once activated ▲
▼ and ▲ ▼ are backboard BB
Is applied to the AND gates AG1 and AG2 of the counterpart processor through the lead wires L1 and L2 provided in the and, and these AND gates are closed. By this, each driver DR
1 and DR2 open their outputs respectively.

Here, two control permission signals ▲ ▼, ▲
Among the ▼, the output end of the driver DR1 that outputs one of the control permission signals ▲ ▼ is connected to the common via the capacitor C1.
▼ indicates a resistor R1 and a capacitor C1 as shown in (a).
It gradually rises with the time constant determined by the value of. On the other hand, the other control permission signal ▲ ▼ quickly becomes high level by the pull-up resistor R2, as shown in (b).

Until the control enable signal ▲ ▼ rises and activates the output of the AND gate AG1 again, and the control enable signal ▲ ▼ becomes active, the control enable signal ▲ ▼ rises slowly and the threshold of the AND gate AG2. By selecting the values of the resistor and capacitor so that the level Vth is not exceeded, the AND gate AG2 remains closed and the control enable signal ▲
▼ will not be activated thereafter, and the conflict will be resolved.

By such an operation, when the ready signals RDY1 and RDY2 are activated almost at the same time, the first processor PC1 side becomes the main system in this case due to the difference in the level of the signal LOC indicating the mounting position of the processor. Operate.

In the above description, the case where the first processor PC1 is the main system has been described, but the second processor PC2
In the case of using as the main system, it can be easily changed by changing the level of the signal LOC indicating the mounting position.

(Effect of the Invention) As described in detail above, according to the present invention, a dual processor system having the following features can be realized with a simple configuration.

(A) It is possible to determine which processor is to operate as the main system in a short time.

(B) Each processor determines the level of the control permission signal to be input after outputting the ready signal, but the waiting time can be shortened.

(C) The duplicated processor performs an asymmetrical operation depending on its mounting position, but the operation can be set from the backboard, so two processors having the same configuration can be used.

[Brief description of drawings]

FIG. 1 is a configuration block diagram showing an embodiment of the present invention, and FIG.
FIG. 3 is an operation waveform diagram showing an example of the operation, and FIG. 3 is a conceptual diagram of the configuration of a conventional dual processor system. PC1 ... First processor PC2 ... Second processor BB ... Backboard AG1, AG2 ... AND gates DR1, DR2 ... Drivers C1, C2 ... Capacitors R1, R2 ... Resistors

Claims (1)

[Claims] 1. A duplicated first and second processor (driver) which outputs a control permission signal to itself according to a ready signal of itself and a control permission signal from the other side respectively. PC1 and PC2) and the duplicated first and second processors are mounted, and lead wires (L1, L2) for transmitting control permission signals to one another as a main system and the other as a slave system. ) Are arranged in a backboard (BB), wherein one end is connected to the output end of the driver and the other end is connected to the backboard (BB) from the backboard to the processor. Controls for providing one of the first and second processors as a main system and the other as a slave system on the backboard by providing capacitors (C1, C2) to which a signal indicating the mounting position of Transmit permission signal to each other By installing resistors (R1, R2) that pull up each lead wire to a specified voltage, connect the other end of one capacitor to common and open the other end of the other capacitor on the backboard. A dual processor system, wherein a signal indicating the mounting position is generated.