JPH0828830B2 - Horizontal deflection circuit - Google Patents

Description

The present invention relates to a horizontal deflection circuit of a television receiver,
In particular, it is suitable for application to a horizontal deflection circuit which controls an oscillation circuit based on a horizontal synchronizing signal and a flyback pulse.

B Outline of the Invention In a horizontal deflection circuit of a television receiver, a comparison signal is created based on a flyback pulse, and the slope and other parts of the comparison signal are weighted with different weighting amounts to perform weighting with the horizontal synchronization signal. Compare the signal to the
By controlling the oscillation frequency on the basis of the comparison signal, even if a noise component is mixed in the horizontal synchronizing signal, the synchronization cannot be lost.

C Conventional Technology Conventionally, in the horizontal deflection circuit of a television receiver, a device has been devised so that its deflection frequency is synchronized with the horizontal synchronization signal of the television signal as stably and reliably as possible. For example, in the horizontal deflection circuit 1 as shown in FIG. 8, the phase comparison circuit 3, the low pass filter 5,
AFC (autumn) consisting of VCO6, flyback transformer drive circuit 7, flyback transformer 8 and phase comparison wave forming circuit 4
omatic frequency control) loop is used.

The horizontal synchronizing signal HD (Fig. 9 (B)) included in the video signal S1 (Fig. 9 (A)) output from the video receiving circuit 9 is separated in the synchronizing signal separating circuit 2 to be subjected to the phase comparison circuit. 3 is output.

On the other hand, the flyback pulse FBP (FIG. 9 (C)) output from the flyback transformer 8 is input to the phase comparison wave forming circuit 4, and the flyback pulse is generated based on this.
The rising comparison signal S2 (FIG. 9 (D)) synchronized with FBP is output to the phase comparison circuit 3.

The phase comparison circuit 3 compares the phase of the comparison signal 2 and the horizontal synchronization signal HD, and the control signal S3 representing the voltage of the comparison signal S2 in the section of the logic "H" (FIG. 9B) of the horizontal synchronization signal HD.
(Fig. 9 (E)) is output to VCO6 via the low-pass filter 5, whereby the control signal S3 operates so as to be pulled into the center voltage V _O. Thus, the phase of the flyback pulse FBP is locked to the horizontal synchronizing signal HD.

As a result, for example, as shown in period T1 of FIG. 9, when the flyback pulse FBP is synchronized with the horizontal synchronization signal HD, the control signal S3 is almost the center voltage of the comparison signal S3.
It becomes V _O.

Further, as shown in the period T2, in the state where synchronization is lost in the fly-back pulse FBP with respect to the horizontal synchronizing signal HD, the control signal S3, the control made by the voltage of the comparison signal S ₂ in the pulse width period T _S of the horizontal synchronizing signal HD Outputs signal S3. At this time, the control signal S3 is controlled by controlling the oscillation frequency of VCO6.
Is pulled to the center voltage V _O.

D The problem to be solved by the invention is that, due to the influence of random noise such as city noise, a video signal S1 having a noise component lower than the synchronizing signal level V _HD as shown in period T3 of FIG. It may be output from the receiving circuit 9.

In this case, the synchronization signal HD output from the synchronization signal separation circuit 2 becomes a signal that sets the noise component section T _N and the synchronization component section T _S to logic “H”.

Therefore, during normal operation in which the horizontal deflection circuit 1 is operating in synchronization with the rising pulse of the horizontal synchronizing signal HD, the voltage of the control signal S3 fluctuates during the noise generation period T _N.

Therefore, the oscillation frequency of the VCO 6 fluctuates intermittently, which causes a problem that the display image as shown in FIG. 10 is distorted as shown in FIG. 11, for example.

The present invention has been made in consideration of the above points, and an object thereof is to propose a horizontal deflection circuit which is hardly affected by random noise such as city noise.

E Means for Solving the Problems In order to solve the problems, according to the present invention, in the horizontal deflection circuit 10 of the television receiver, based on the pulse FBP induced in the flyback transformer 8, the pulse FBP is generated. A comparison signal forming circuit 12 for forming a comparison signal S4 having a time width equal to or less than the pulse width of 4 and having an inclined portion synchronized with the pulse FBP; and an effective phase pulse S5 of a predetermined level synchronized with the inclined portion of the comparison signal 4. At the timing based on the effective phase pulse forming circuit 13 to be formed and the horizontal synchronizing signal HD, the slope portion of the comparison signal S4 is weighted SD sample and held by the first weighting amount according to the level of the effective phase pulse S5, and the comparison signal S4 is generated. The other part of the effective phase pulse
A weighting circuit 11 for weighting with a second weighting amount according to the level of S5 to sample and hold, and a weighting circuit
Control means 5 and 6 for controlling the oscillation frequency of the drive signal for driving the flyback transformer 8 based on the sample hold result S3 output from 11 are provided.

F action The comparison signal S4 is formed on the basis of the pulse FBP induced in the flyback transformer 8, and the inclined portion of the comparison signal S4 is changed to the effective phase pulse S5 at the timing based on the horizontal synchronizing signal HD.
Is sampled and held with a first weighting amount corresponding to the level of the effective phase pulse S5 and the other portion of the comparison signal S4 is sampled and held with a second weighting amount according to the level of the effective phase pulse S5. By controlling the oscillation frequency of the drive signal for driving the flyback transformer 8 based on the sample hold result S3, even if a noise component is mixed in the horizontal synchronizing signal HD, horizontal synchronization can be reliably achieved. A deflection circuit can be realized.

G Embodiment One embodiment of the present invention will be described in detail below with reference to the drawings.

In the horizontal deflection circuit 10 of FIG. 1 in which parts corresponding to those of FIG. 8 are designated by the same reference numerals, a weighting circuit 11 and a pulse forming circuit 12 are used instead of the conventional phase comparison circuit 3 and phase comparison wave formation circuit 4. The level adjusting circuit 13 and the pulse shaping circuit 14 are used.

The pulse shaping circuit 14 shapes the flyback pulse FBP and outputs a pulse SP having a substantially equal duty to the pulse forming circuit 12 in synchronization with the flyback pulse FBP.

The pulse forming circuit 12 is composed of a transistor Q1 and a transistor Q2, for example, as shown in FIG.

The voltage V1 is applied to the base of the transistor Q1 via the resistor 21.
The reference power source 22 is connected to the reference power source 24 of the voltage V2 (V2 <V1) through the switch circuit 23.
The switch circuit 23 is turned on when the pulse SP reaches the "L" level, and connects the reference power supply 24 to the base of the transistor Q1. Therefore, the base voltage of transistor Q1 is pulsed.
When SP rises to the “H” level, the voltage becomes V1 and “L”
When it falls to the level, it becomes the voltage V2.

The emitter of the transistor Q1 is connected to the output terminal W1, connected to the power supply line via the constant current source 25 for the current I1, and further connected to the ground via the capacitor 26. The collector of the transistor Q1 is connected to the ground via the resistor 27, and the collector of the transistor Q1 is connected to the output terminal W2.
Connected to the base of Q2.

In the configuration of FIG. 2, as shown in FIG.
When the pulse SP is in the “L” level period T4, the transistor
The base voltage of Q1 becomes V2, and its emitter voltage, and accordingly the output voltage S4, becomes V2 + V _BE , as shown in FIG. 3 (B). Here, since the current I1 flows through the resistor 27 and a potential difference is generated in the resistor 27, the transistor Q2 is turned on.

On the other hand, when the pulse SP rises to the “H” level, the base voltage of the transistor Q1 rises from V2 to V1, but the charging time constant of the capacitor 26 affects the transistor Q1.
It becomes impossible for the emitter voltage of 1 to follow the base voltage. Accordingly, the transistor Q1 is turned off, the capacitor 26 is charged by the current I1 of the constant current source 25, and the output voltage S4 gradually rises (period T5).

The terminal voltage of the capacitor 26, and therefore the output voltage S4 is V1 + V
_{At BE} , transistor Q1 turns on and output voltage S4
Holds a constant value V1 + V _BE (period T6).

Here, the potential difference between the current value I1 of the constant current source 25 and the reference power sources 22 and 24 is such that the emitter voltage of the transistor Q1 (hence the output voltage S4) is V1 at about the middle of the “H” level of the pulse SP.
It is set to be + V _BE .

 Therefore, the period T5 is almost the same as the period T6.

On the other hand, since the transistor Q1 is turned off in the period T5, the base voltage of the transistor Q2 becomes 0 [V] and the transistor Q2 is turned off. At this time, the output voltage SL of the output terminal W2 rises to "H" level as shown in FIG.

Eventually, in the period T6, the transistor Q1 is turned on, the transistor Q2 is turned on, and the output voltage SL becomes "L" level.

Then, when the pulse SP falls, the base voltage V _B1 of the transistor Q1 drops to V2, and the capacitor 26 is rapidly discharged through the transistor Q1 to output the output voltage S4.
Change to V2 + V _BE .

Thus, the output terminal W1 has a pulse SP (Fig. 3 (A)).
An output signal S4 (FIG. 3 (B)) synchronized with the output signal S4 (FIG. 3 (C)) is output from the output terminal W2 (FIG. 3 (C)).
Is at the "H" level during the period corresponding to the sloped portion of, and is at the "L" level during the other periods.

The level adjusting circuit 13 receives the output voltage SL of the pulse forming circuit 12 and, in accordance with the level, becomes the predetermined voltage V _O1 at the “H” level and becomes the predetermined voltage V _O2 at the “L” level. Output pulse S5.

Further, the weighting circuit 11 is composed of a sample and hold circuit, and for example, a structure as shown in FIG. 4 can be applied. That is, the transistor Q5 constitutes a buffer circuit which receives the effective phase pulse S5 at the base via the input terminal W3, and the emitter thereof is connected to the ground via the resistors 31 and 33 and the diode 32.

The transistor Q6 constitutes a differential amplifier circuit which constitutes a current mirror circuit including an emitter resistor 34, a diode 32 and a resistor 33 connected to the base.
It operates as a current source on the emitter side of Q7 and Q8. Therefore, the sum current I _O flowing through the transistors Q7 and Q8 is
It changes according to the level of the effective phase pulse S5 input to Q5.

The collector of the transistor Q7 is connected to the power supply line V _CC, and the inverted signal ▲ ▼ of the horizontal synchronizing signal HD is given to the base via the input terminal W4.

On the other hand, the base of the transistor Q8 is supplied with a voltage V3 which is substantially equal to the center voltage of the inverted signal {circle around (1)} from the reference power source 35 and operates as an emitter side current source of the transistors Q9 and Q10 of the differential amplifier circuit configuration.

Therefore, when the base voltage of the transistor Q7 is V _B7 > V3 (when the inverted signal ▲ ▼ is at the "L" level), the transistor Q8 is turned on, and the sum current of the transistors Q9 and Q10 is the collector current I _O of the transistor Q6, that is, , It depends on the level of the effective phase pulse S5.

On the other hand, when the base voltage of the transistor Q7 is V _B7 <V3 (that is, when the inverted signal ▲ ▼ is at "H" level),
Transistor Q8 is turned off and transistor Q9 and
Q10 collector current stops flowing.

On the other hand, the output signal S4 of the pulse forming circuit 12 is given to the base of the transistor Q9 via the input terminal W5, and the collector is connected to the base of the transistor Q12 that constitutes the current mirror circuit together with the resistors 36 and 41 and the diode 37. .

The collector of transistor Q10 has collectors 38, 40
Also, the base is led to the output terminal W6 while being connected to the base of the transistor Q11 that forms the current mirror circuit together with the diode 39.

Further, the collector of the transistor Q11 is connected to the base of the transistor Q13 which forms a current mirror circuit together with the resistors 43 and 44 and the diode 42.

The collectors of the transistors Q12 and Q13 are connected to the output terminal W6 together with the sample-hold capacitor 45.

In the configuration of FIG. 4, when the transistor Q8 is in the ON state and the signal S4 rises and the base voltage V _B9 of the transistor Q9 rises, the collector current of the transistor Q9 increases and the collector current of the transistor Q10 decreases. To do. Therefore, the collector current of the transistor Q12 increases,
The collector currents of the transistors Q11 and Q13 decrease.

Therefore, a difference occurs in the collector currents of the transistors Q12 and Q13, and the capacitor 45 is charged by the difference current, and as a result, the base voltage of the transistor Q10 rises.

Eventually, the base voltage of transistor Q10 will be transistor Q.
When it matches the base voltage of 9, their collector currents are equal to each other, which also equalizes the collector currents of transistors Q12 and Q13.

Thus, the charging of the capacitor 45 is stopped and the voltage of the output terminal W6 becomes equal to the base voltage V _B9 of the transistor Q9.

Here, the sum of the collector currents of the transistors Q9 and Q10 is determined based on the collector current I _O of the transistor Q6, that is, the effective phase pulse S5 of the input terminal W3, and therefore corresponds to the increase or decrease in the input level of the effective phase pulse S5. The difference current between the collector currents of the transistors Q9 and Q10 (that is, the charging current of the capacitor 45) increases or decreases. Thus, when the effective phase pulse S5 is at "H" level, the charging time of the capacitor 45 is short, and conversely, when it is at "L" level, it is long.

On the other hand, while the capacitor 45 is charging, the transistor Q8
Is turned off (that is, when the inverted signal ▲ ▼ becomes "H" level), the transistors Q9 and Q10 are turned off, and at this time, the transistors Q12, Q11, and Q13 are also turned off.

Therefore, the charging operation of the capacitor 45 is completely stopped, and the terminal voltage of the capacitor 45 holds the voltage immediately before the transistor Q8 turns off, that is, the charging voltage immediately before the inverted signal ▲ ▼ becomes "H" level. To do.

On the other hand, when the base voltage V _B9 of the transistor Q9 drops while the transistor Q8 is on, the collector current of the transistor Q9 decreases and the transistor Q10
The collector current of Q12 increases, which causes transistor Q12
Collector current of transistor Q13 decreases and collector current of transistor Q13 increases. At this time, the capacitor 45 is discharged by the difference current between the collector currents of the transistors Q12 and Q13, so that the base voltage V _B10 of the transistor Q10 decreases.

This discharge current is also determined based on the sum current of the collector currents of the transistors Q9 and Q10, that is, the level of the effective phase pulse S5. When the effective phase pulse S5 is at the "H" level, the discharge time of the capacitor 45 is shortened, and conversely it is effective. Phase pulse
When S5 is at "L" level, the discharge time of the capacitor 45 becomes longer.

When the base voltage V _{B10 of the} transistor Q10 matches the base voltage of the transistor Q9, the capacitor 45 stops discharging.

Here, as in the charging operation of the capacitor 45, the transistor Q8 is in the OFF state (that is, the inverted signal ▲ ▼ is "H").
Capacitor 45, the inverted signal of capacitor 45
The voltage in the discharge process immediately before the ▼ becomes “H” level is held.

For example, as shown in FIG. 5, the signal SP (FIG. 5 (C)) obtained by shaping the flyback pulse FBP (FIG. 5 (B)) is synchronized with the inverted signal ▲ ▼ (FIG. 5 (A)). The signal S4 (Fig. 5 (D)) and the effective phase pulse S5 (Fig. 5 (E)) are input in synchronism with the timing of the inversion signal ▲ ▼.

Here, for example, in an ordinary television receiver, the pulse width of the horizontal synchronizing signal HD is about 4 to 5 [μsec],
Flyback pulse FBP pulse width is about 10 to 13 [μsec]
It is a degree. Therefore, the "L" level period T ₁₄ of the inverted signal ▲ ▼ is the "H" level period T of the effective phase pulse S5.
Almost identical to _11, coincides with the period T ₁₂ + T ₁₃ of the "L" level of the opposite "H" level period T ₁₅ effective phase pulse S5.

The collector current I _O of transistor Q6 is the effective phase pulse
It changes in synchronization with S5 and becomes I _O1 in the period T ₁₁ . On the contrary, in the period T ₁₂ , it changes to I _O2 (αI _O1 = I _O2 , 0 <α <1) (FIG. 5 (F)).

The transistor Q8 is turned on in the period T ₁₄ (≈T ₁₁ ), and the sum current I ₉ + I ₁₀ of the transistors Q9 and Q10 is I
It becomes _O1 . Further, the transistor Q8 has a period T ₁₅ (≈ T ₁₂ +
At T ₁₃ ), it is turned off and the current becomes zero. Therefore, the capacitor 45 quickly follows the voltage of the signal S4 in the period T ₁₁ , and the transistor 45 in the period T ₁₄ (≈T ₁₁ ).
Charging (or discharging) based on the sum current I ₉ + I ₁₀ (= I _O1 ) of Q9 and Q10. The capacitor 45 is a retaining the mesenchyme discharge voltage period T ₁₅ (the center voltage of approximately signal S4) (FIG. 5 (H)).

Further, as shown in FIG. 6, in the state where the pulse SP (FIG. 6 (C)) is out of synchronization with the inverted signal ▲ ▼ (FIG. 6 (A)), the signal S4 (FIG. 6 (D) )) And the effective phase pulse S5 (Fig. 6 (E)) are input in synchronization with the signal SP (Fig. 6 (C)), and the "L" level of the inverted signal ▲ ▼ (Fig. 6 (A)). period T ₂₄ is not equal to the term T ₂₁ of the "H" level of the active phase pulse S5 in.

The collector current I _O of transistor Q6 is the effective phase pulse
“L” level period T ₂₂ + T ₂₃ of S5 (Fig. 6 (E)) is I
_O2 , and conversely, during the period T ₂₁ , I _O1 (αI _O1 = I _O2 , 0 <α <
1) (Fig. 6 (F)).

On the other hand, the sum current I ₉ + I ₁₀ becomes I _O2 in the period T ₂₃ of the “L” level of the inversion signal (), and becomes 0 when it is at the “H” level (FIG. 6 (G)). Therefore condenser 45
It is to follow the signal S4 in the period T _24, the charging or discharging based on the lower sum current than during synchronization _{I 9 + I 10 (= I} O2).

As for the voltage of the capacitor 45, the charging / discharging current is α times (0 <α <
1), it follows the voltage of the signal S4 with a delay,
It is held before reaching the voltage of the signal S4. The voltage of the capacitor 45 is held for the period T ₂₅ (FIG. 6 (H)).

Further, as shown in FIG. 7, a period T ₃₅ of "H" level of the inverted signal ▲ ▼ is mixed with a period T ₃₆ of "L" level of the noise component (FIG. 7 (A)), and the inverted signal ▲
When the pulse SP (Fig. 7 (C)) operates in synchronization with ▼, the signal S4 and the effective phase pulse S5 are input in synchronization with the signal SP as in the case of Fig. 5. (FIG. 7 (C), (D), (E)).

Therefore, the "L" level period T of the inverted signal ▲ ▼
₃₄ substantially coincides with the "H" level period T ₃₁ of the effective phase pulse S5.

The current I _{O of the} transistor Q6 becomes I _O1 in the period T ₃₁ and becomes I _O2 (αI _O1 = I _O2 ) in the period T ₃₂ + T ₃₃ (FIG. 7 (F)).

While transistor Q8 is, since the on-state to the inverted signal ▲ ▼ "L" level period T ₃₄ and T _36, the sum current I ₉ + I ₁₀ of transistors Q9 and Q10 are next I _O1 is in a period T _34, It becomes I _{O2 in the} period T ₃₆ (FIG. 7 (G)).

Therefore, the capacitor 45 follows the voltage in the period T ₃₁ of the signal S4 in the period T ₃₆ and is charged or discharged based on the current I _O1 .

Then, until the period T ₃₆ , the voltage (almost signal S
The central voltage of 4) is maintained, and charging or discharging is performed again in the period T ₃₆ (FIG. 7 (H)).

In the period T ₃₆ , the sum current I ₉ + I ₁₀ becomes α times (0 <α <1) in the period T ₃₄ , and the capacitor 45 follows the signal S4 with a delay according to the sum current I ₉ + I _10. And discharge or charge.

Therefore, the voltage of the capacitor 45 is held at the voltage in the process of following the voltage of the signal S4, and the capacitor 45 is held for the period T _36.
After the lapse of time, the voltage is held until the next inversion signal ▲ ▼ becomes “L” level (FIG. 7 (H)).

In this way, the weighting circuit 11 of FIG. 4 samples the voltage of the signal S4 during the "H" level period of the inversion signal ▲ ▼, and samples the voltage based on the voltage of the effective apparent pulse during that period. Voltage V _H
Is output.

In the above configuration, when the pulse SP, which is shaped the flyback pulse FBP, is input to the pulse forming circuit 12 (Fig. 2), the output terminal W1 of the pulse forming circuit 12 outputs an output signal synchronized with the flyback pulse FBP. S4 is output (3rd
(B)).

On the other hand, the output terminal W2 is at "H" level during the period T5 of the output signal S4, and is at "L" level during the other periods (Fig. 3 (C)).

The level adjusting circuit 13 outputs the effective phase pulse S5 corresponding to the level of the output terminal W2.

Now, when the horizontal deflection circuit 10 is operating in synchronization with the horizontal synchronizing signal HD, the shaping pulse (FIG. 5 (C)) and the effective phase synchronized with the flyback pulse FBP (FIG. 5 (B)). The timing of the pulse S5 (FIG. 5 (E)) and the timing of the inversion signal () of the horizontal synchronizing signal HD coincide (FIGS. 5 (A) and (D)).

Therefore, the weighting circuit 11 outputs the inverted signal ▲ ▼ of the signal S4.
The voltage of the H-level period T ₁₄ is sampled (FIG. 5 (C)), and the voltage V _H1 weighted based on the voltage V _O1 of the H-level period T ₁₁ of the effective phase pulse S5 is obtained. It is output as a control signal S3 (FIG. 5 (H)).

The control signal S3 maintains the oscillation frequency of the VCO 6 via the low-pass filter 5, and the flyback transformer drive circuit 7 drives the flyback transformer 8 in synchronization with the horizontal synchronizing signal HD based on this frequency.

The flyback pulse FBP obtained from the flyback transformer 8 is input to the pulse shaping circuit 14, and the pulse SP is output to the pulse forming circuit 12.

Thus, the AFC loop is formed, and the horizontal deflection circuit 10 continues to operate in synchronization with the horizontal synchronization signal HD.

However, when the synchronization of the horizontal deflection circuit 10 is out, the period T ₂₁ in the "H" level of the active phase pulse S5, the inverted signal ▲ ▼ will not match.

Accordingly, the weighting circuit 11 samples the voltage of the signal S4 during the period T ₂₄ (FIG. 6 (D)) and controls the weighted voltage V _H2 based on the voltage V _O2 of the effective phase pulse S5 during the period T _21. It is output as a signal S3 (Fig. 6 (H)).

Thus, the voltage V _H2 is weighted approximately α times (α = I _O2 / I _O1 , FIG. 6 (F)) with respect to the voltage V _{S4 of the} signal S4. The VCO6 is controlled by the control voltage of this α times to change the oscillation frequency.

When the oscillation frequency changes and the period T ₂₆ overlaps a part of the sloped portion of the signal S4, the voltage of the signal S4 represents the weighting coefficient 1 in the overlapped portion. Thus, the control signal S3 changes abruptly, and the oscillation frequency of VCO6 changes to the synchronization signal HD.
Is drawn to.

Since the weighting of the change is a coefficient of "1", the change becomes a synchronization operation to the horizontal synchronization signal HD similar to the conventional horizontal deflection circuit 1.

On the other hand, if the noise component of the inverted signal ▲ ▼ is mixed in in a synchronized state, the weighting circuit 11 corresponds to the noise period T ₃₆ (Fig. 7 (A)) and the voltage V of the signal S4 during the period T ₂₁ .
_The voltage V _H3 obtained by weighting _S4 with the coefficient α is output during the period T ₃₇ (FIG. 6 (H)).

However, because of the synchronization, the weighting circuit 11 outputs the voltage V _H1 having the weighting coefficient 1 during the period other than this.

Thus, VCO 6 is repeated voltage V _H1 and V _H3 control signal
Controlled based on S3. Since the voltage V _H3 is weighted by the coefficient α and has a value close to V _H1 , the voltage output through the low-pass filter of the control signal S1 is almost V _H3 .

Thus, the horizontal deflection circuit 10 continues to operate in a synchronized state even when a noise component is mixed.

According to the above configuration, by appropriately selecting the weighting amount, even if a noise component is mixed in the synchronization signal HD, the synchronization state is maintained, and even when the synchronization is lost, the same level as the conventional circuit is obtained. It is possible to obtain a horizontal deflection circuit capable of pulling the oscillation frequency into the horizontal synchronization signal HD.

In the above-described embodiment, the signals S4 and S5 are generated using the pulse SP that is the waveform of the flyback pulse FBP, but the flyback pulse FBP may be used directly.

Further, as the weighting method and the comparison method with the horizontal synchronizing signal HD, the case where the sample hold circuit is used is described, but the present invention is not limited to this, and, for example, a method using a conventional phase comparison circuit by separately providing a weighting circuit. Etc. can be widely applied.

As a weighting method, one coefficient is set to 1,
Although the other coefficient is α (0 <α <1), the present invention is not limited to this, and one coefficient may be α (α> 1) and the other coefficient may be 1.

H As described above, according to the present invention, in the horizontal deflection circuit of the television receiver, based on the pulse induced in the flyback transformer, the time width is less than or equal to the pulse width of the pulse, and Forming a comparison signal having an inclined portion synchronized with the pulse, forming an effective phase pulse of a predetermined level in synchronization with the inclination portion of the comparison signal, and inclining and other portions of the comparison signal at a timing based on the horizontal synchronization signal Are sampled and held by weighting each with a first or second weighting amount according to the level of the effective phase pulse,
By controlling the oscillation frequency of the drive signal that drives the flyback transformer based on the sample and hold result, the displayed image will not be disturbed even if noise is mixed into the horizontal sync signal due to the effects of city noise, etc. A horizontal deflection circuit that can be effectively avoided can be realized.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the horizontal deflection circuit of the present invention, FIG. 2 is a circuit diagram of its pulse forming circuit, FIG. 3 is a signal waveform diagram for explaining its operation, and FIG. 4 is weighting. Circuit diagrams of the circuit, FIGS. 5 to 7 are signal waveform diagrams used for explaining the embodiment of the present invention, FIG. 8 is a block diagram of a conventional horizontal deflection circuit, and FIG. 9 is a signal waveform diagram used for the explanation. , Tenth
FIG. 11 and FIG. 11 are schematic diagrams of the display image. 1, 10 ... Horizontal deflection circuit, 2 ... Sync signal separation circuit, 3
...... Phase comparison circuit, 5 …… Low-pass filter, 6 …… VC
O, 8 ... Flyback transformer, 11 ... Weighting circuit, 12 ... Pulse forming circuit, 13 ... Level adjusting circuit, 14
...... Pulse shaping circuit.

Claims (1)

[Claims] 1. In a horizontal deflection circuit of a television receiver, based on a pulse induced in a flyback transformer,
A comparison signal forming circuit for forming a comparison signal having a time width equal to or less than the pulse width of the pulse and having an inclined portion synchronized with the pulse, and an effective phase pulse of a predetermined level synchronized with the inclined portion of the comparison signal. An effective phase pulse forming circuit for forming the first phase, and a first portion corresponding to the level of the effective phase pulse for the inclined portion of the comparison signal at a timing based on the horizontal synchronizing signal.
A weighting circuit for weighting and holding the other portion of the comparison signal with a second weighting amount according to the level of the effective phase pulse, and sample-holding the other portion of the comparison signal; and an output from the weighting circuit. And a control means for controlling the oscillation frequency of the drive signal for driving the flyback transformer based on the sample and hold result.