JPH0831591B2 - High-speed semiconductor device - Google Patents

Description

The present invention relates to a high speed semiconductor device, and more particularly to a resonant tunneling device.
Regarding hot carrier transistors.

(Prior Art) Resonance tunnel effect is extremely promising for application to ultra-high-speed and new-function devices because the delay time required for the passage of electrons is remarkably short and the differential negative resistance characteristic is remarkable. Development has become active.

FIG. 10 and FIG. 11 are an energy band diagram showing a cross-sectional structure diagram and operation of a conventional resonant tunneling hot electron transistor (RHET), for example, Yokoyama et al., Japanese Journal of Applied Physics. (Jpn.J.Appl.Phys.),
Vol. 24, No. 11, L853, reported in 1985. The cross-sectional view of this resonant tunneling hot electron transistor (hereinafter referred to as RHET) is the axis of symmetry YY '.
As shown in FIG. 10, only one side surface of the n-type GaAs emitter layer 1 formed on the semi-insulating GaAs substrate 9 and the non-doped AlGaAs quantum well layer forming the superlattice layer are shown. N of the sandwich layer of 2a and the non-doped AlGaAs potential barrier layer 2b, the n-type GaAs base layer 3, and the non-doped AlGaAs collector-side potential barrier layer 4
And a GaAs collector layer 5. Where 10, 11 and 12
Are emitter, base and collector electrodes, respectively. In this RHET, electrons injected by the resonance tunnel effect travel as hot electrons in the base layer 3 and thus have a remarkable differential negative resistance (NDR). Can be configured.

FIG. 12 shows a connection circuit diagram of a flip-flop configured by using the above-mentioned conventional resonant tunneling hot electron transistor (RHET). The collector electrode 12 of the emitter-grounded RHET is connected via a resistor R. Voltage source Vcc
Driven by the input voltage applied to the base electrode 11 from the input terminal S through the resistor Rs. In this circuit, the potential of the contact point between the collector electrode 12 of RHET and the resistor R is taken out from the output terminal Q, but by applying a bias potential to the input terminal S, the potential of the output terminal Q has two stable states. Therefore, by inputting either one of the positive and negative signal pulses with respect to the bias potential to the input terminal S, it becomes possible to switch between these two states. Thus, using this RHET, a simple flip-flop circuit can be obtained with one active element.

(Problems to be Solved by the Invention) By the way, when a counter, a shift register, or the like is formed by using a flip-flop, it is required that the output Q and its inverse output be obtained at the same time.
A one-output flip-flop as shown in Figure 12 is difficult to use. That is, in order to form a 2-output flip-flop by using such a 1-output flip-flop, it is necessary to use an inverter circuit at the same time. At this time, an increase in wiring delay time and output (Q,) Therefore, a high-speed operation becomes difficult due to the phase delay.

In view of the above problems, an object of the present invention is to provide a high-speed semiconductor device having a resonant tunnel effect capable of realizing a 2-output flip-flop operation with a simple circuit configuration.

(Means for Solving the Problems) According to the present invention, a high-speed semiconductor device includes a compound semiconductor substrate and a superlattice layer, a base layer, and a collector layer that share one emitter layer on the compound semiconductor substrate. The pair of resonant tunneling hot carrier transistors, which are arranged one after another in a vertically symmetrical arrangement, have electrons of different energy levels in the quantum well layer forming the superlattice layer. Alternatively, each of the sub-bands of holes is generated and formed.

(Operation) According to the present invention, a pair of resonant tunneling hot carrier transistors are independently formed on a single substrate, each of which is provided with a superlattice layer for generating subbands of electrons or holes having different energy levels. To be done. Therefore, each transistor can behave independently as a differential negative resistance element with respect to one input signal applied to the base layer, and it can operate as a 2-output flip-flop, exclusive OR / NOR.
Other logical operation operations can be performed by only one element.

(Example) Hereinafter, the present invention will be described in detail with reference to the drawings.

1 and 2 are a sectional structural view and a conduction band profile diagram corresponding thereto showing an embodiment of the high speed semiconductor device of the present invention, respectively. According to the present embodiment, the sectional view shows only one side surface of the symmetry axis Y-Y 'as in the conventional example, and the n-type GaAs common emitter 1 is sandwiched on the semi-insulating GaAs substrate 9 to form a pair of vertically symmetrical pairs. The first and second non-doped GaAs quantum well layers 2a ₁ and 2a ₂ and the first and second non-doped Al _0.3 Ga _0.7 As potential barrier layers 2b ₁ having different thicknesses formed so as to arrange the RHET. , 2b ₂ and a pair of first and second superlattice layers each consisting of a sandwich layer, and a pair of first and second n-type GaAs base layers
3a, 3b and a pair of first and second undoped Al _0.15 Ga
_0.85 As collector-side potential barrier layers 4a, 4b and a pair of first and second n-type GaAs collector layers 5a, 5b. Here, reference numerals 10 , 11a, 11b and 12a, 12b respectively denote a common emitter electrode and first and second base electrodes and collector electrodes, respectively.

According to this embodiment, electron sub-bands En (n = 1, 2, ...) Are generated in the quantum well layer 2a ₁ , and the quantum well layer 2a is formed.
The in ₂ electron subbands E'N (n = 1,2, ...) are generated, respectively. As is generally known, when the width of the quantum well layer is L and the effective mass of electrons is m, the energy level of the subband of the quantum well layer is approximately It is represented by. However, Is the Planck constant, and п is the pi. Therefore, by appropriately setting the film thicknesses of the quantum well layers 2a ₁ and 2a ₂ , it becomes possible to make the energy levels En and E′n of the subbands in the two quantum well layers different. In this embodiment, the quantum well layer 2a ₁ is thicker than the film thickness of 2a ₂ , and the energy level of each subband is E ₁ <E ′ as shown in the profile of FIG. The order is ₁ <E ₂ .

The high-speed semiconductor device having such a structure operates as follows.

3 (a), (b) and (c) show conduction band profile diagrams for explaining the basic operation of the high speed semiconductor device of the present invention. Here, consider a case where the two base electrodes 11a and 11b are short-circuited and signal pulses of different levels are applied thereto. For the sake of simplicity, the common emitter layer 1 will be referred to as E, the base layers 3a and 3b as B, the collector layer 5a as C, and the collector layer 5b as C '.

Now, when the base-emitter voltage V _BE is about 2E ₁ / q (where q is the electron charge amount), as shown in FIG. 3 (a), the subband ground level of the quantum well 2a ₁ The electrons injected into the base due to the resonance tunnel effect at E ₁ become hot electrons and reach the collector layer 5a, so that the current Ic flows through the collector C. On the other hand, since the injection energy of electrons in the base layer 3a is as low as the height of the first collector-side barrier layer 4a, a part of the electrons injected into the base layer 3a flows into the base B and the base current I _B
Make At this time, no current flows through the collector C '. Here, when V _BE becomes about 2E ′ ₁ / q, a resonant tunnel occurs in the subband ground level E ′ ₁ of the quantum well 2a ₂ as shown in FIG. 3B, and the current I _C flows to the collector C ′. ′ Flows. At this time, since the injection energy of electrons in the base layer 3b is sufficiently higher than the height of the second collector-side barrier 4b, most of the electrons flow into the collector C'and no base current flows. At this time, no current flows in one collector C. Further, when V _BE becomes about 2E ₂ / q, a resonance tunnel occurs in the energy level at E ₂ , and a current flows in one collector C and no current flows in the other collector C ′ (the third state). See FIG. (C)). As described above, the high-speed semiconductor device of the present invention in which the emitter layer 1 is shared to form the pair of RHETs has a differential negative resistance when the collector current I _C and the base current I _{B of} one RHET are V _BE = 2E ₁ / q. (NDR),
In the other RHET, the collector current I _C ′ is V _BE = 2
E ₁ / q also causes differential negative resistance (NDR). That is, since the collector current and the base current respectively exhibit differential negative resistance in response to different base-emitter voltages (V _BE ), it is possible to easily form a two-output flip-flop with a single element.

4 and 5 are a connection circuit diagram of a flip-flop using the high-speed semiconductor device of the present invention and an operating current-voltage characteristic diagram thereof, respectively.

The flip-flop based on the high-speed semiconductor device of the present invention is
Two collector electrodes 12a and 12b of the high-speed semiconductor device T of the present invention having a grounded emitter are connected to a voltage source V _CC via resistors R ₁ and R ₂ , respectively, and input to two commonly connected base terminals 11a and 11b. When an input voltage is applied from the terminal S via the resistor Rs, a flip-flop operation is performed, and the potentials of the connecting contact between the collector electrode 12a and the resistor R _{1 and} the connecting contact between the collector electrode 12b and the resistor R ₂ are output terminals.
Retrieved from Q. At this time, by applying the bias potential V _B to the input terminal S, the two stable states due to the differential negative resistance (NDR) in the base current I _B are changed to the low base-emitter voltage V _BE (V _{BE). 0} ) and high state (V ₁ ) respectively. The value of the low state (V ₀ ) and the high state (V ₁ ) of this base-emitter voltage V _BE can be adjusted by adjusting the resistance Rs to obtain V ₀ ≈ 2E ₁ / q V ₁ ≈ 2E ′
Can be set to ₁ / q respectively. Therefore, V _BE is V ₀
Then, according to FIG. 3 (a), the collector C of one RHET becomes conductive and the collector electrode I _C flows, and no current flows to the collector C'of the other RHET. Therefore, the output Q is in the low voltage state, that is, "L", and the output is in the high voltage state, that is, "H". If V _BE is V ₁ , according to FIG. 3 (b), no current flows through the collector C of one RHET and only the collector C ′ of the other RHET conducts, so that the output Q is “H”, The output goes to the “L” state.

By the way, when V _BE = V ₀ , when a positive pulse is input to the input terminal S with respect to the bias voltage V _B , V _BE becomes V ₀
Changes from V ₁ to V ₁ and is inverted from the output Q, but V _BE
Is V ₀ , even if a negative pulse is input, V _BE
Remains at V ₀ , so the output is held. Similarly, V _BE
There the state made V _1, by inputting a negative pulse with respect to the bias potential V _B to the input terminal S, it is possible to transition the V _BE from V ₁ becomes state V ₀ becomes state. When the positive input is represented by S ₀ and the negative input is represented by R ₀ , the truth table of input and output of the circuit of FIG. 4 is as shown in Table 1, and from now on, it is a 2-output flip-flop operation. Can be confirmed.

Further, according to the present invention, it is possible to simultaneously perform a plurality of logical operations such as exclusive OR and exclusive NOR.

FIG. 6 and FIG. 7 are a connection circuit diagram of an exclusive OR / NOR circuit constituted by the high speed semiconductor device of the present invention and a current-voltage characteristic diagram for explaining its logical operation function.

In the exclusive OR / NOR circuit according to the high-speed semiconductor device of the present invention, the two collector electrodes 12a and 12b of the high-speed semiconductor device T of the present invention with the emitter grounded are connected to the voltage source V _CC via the resistors R ₁ and R ₂ , respectively. Are connected to the two commonly connected base voltage sources V _CC , and the two commonly connected base terminals 11a and 11b are respectively connected to the resistors from the two input terminals A and B.
It operates by applying two different input voltages via R _a and resistor R _b , and the potential of the contact between collector electrode 12a and resistor R ₁ and the potential between the contact between collector electrode 12b and resistor R ₂ are output terminals. Retrieved from X and Y respectively. According to this circuit, by appropriately setting the resistors R _a and R _b , it is possible to prevent the bistable state at the base current I _B as shown in FIG. 5 from occurring. Therefore, the low (V ₀ ) and high (V ₁ , V ₂ ) states of the base-emitter voltage V _BE are V ₀ ≈ 2E ₁ / q, V ₁ ≈ 2E ′ ₁ / q, V ₂ ≈ 2E, respectively. ₂ / q and voltage V ₀ /
2 "0" _{level, (V 1 -V 0/2} ) the "1" and set to the level input terminal A, when it is assumed that give either the B, input A, none of B is " When it is 0 "or both are" 1 ", the base-emitter voltage V _BE
Are respectively V ₀ or almost V ₂ . Therefore, as is clear from the current-voltage characteristics of FIG. 7, in either case, the collector C of one RHET becomes conductive and the collector current I _C flows,
It becomes the other state that does not have _C flows 'current I' collector C of the RHET. That is, the output of the output terminal X becomes "L" and the output of the output terminal Y becomes "H". Similarly, when the inputs A and B are different from each other, V _BE = V ₁ , so that the output is “H” for X and “L” for Y. The truth table shows this as in Table 2, where X is the exclusive OR of A and B, and Y is the exclusive NOR of A and B.
It can be confirmed that

FIG. 8 and FIG. 9 are a sectional structural view and a conduction band profile diagram corresponding thereto, respectively, showing another embodiment of the high speed semiconductor device of the present invention. According to the present embodiment, the sectional view shows only one side surface of the axis of symmetry YY 'as in the previous embodiment, and is vertically symmetrical with the n-type GaAs common emitter layer 1 sandwiched on the N ⁺ GaAs substrate 9'. A non-doped In _0.1 Ga _0.9 As quantum well layer 2a ′ ₁ and a non-doped AlAs potential barrier layer 2b ′ ₁ , and a non-doped GaAs quantum well layer 2a ′ ₂ and a non-doped AlAs potential barrier, which are respectively formed by disposing a pair of RHETs. the pair of each layer 2b _'2 consisting sandwich layer 1 and the second superlattice layer, a pair of first and second n-type GaAs base layer 3a, 3b and a pair of first and second Dononpu Al _0.2 Ga _0.8 As collector-side potential barrier layers 4a, 4b and a pair of first and second n-type GaAs
Includes collector layers 5a and 5b. Here, 10 is a common emitter electrode, 11a and 11b are the first and second base electrodes, respectively.
Reference numerals 2a and 12b denote first and second collector electrodes, respectively. According to this embodiment, an electron sub-band En (n = 1, 2, ...) Is generated in the quantum well layer 2a ′ ₁ and an electron sub-band En (n = 1, 2, ...) Is generated in the quantum well layer 2a ′ ₂ . n = 1, 2, ...) Is generated. Although AlAs and InGaAs have different lattice constants, InGaAs
By setting the thickness of the quantum well layer 2a ′ ₁ to around 30Å and the critical thickness film (about 100Å) at which misfit dislocations are formed, elastic strain becomes a strained lattice layer that relaxes lattice misalignment, and a good interface is formed. To be done. Since InGaAs has a narrower band-jap than GaAs, the lower energy level of the conduction band is lower than that of the emitter layer 1 and the base layer 3a located on both sides by the conduction band offset (about 100 meV) in In _0.1 Ga _0.9 As / GaAs. Become. Therefore, a conduction band profile like the band shown in FIG. 9 is obtained, and E ₁ <E ₁ ′ <E ₂ even if the quantum well layers 2a ′ ₁ and 2a ′ ₂ are not different in film thickness as in the previous embodiment.
Thus, the high speed semiconductor device according to the present invention can be realized. In the above explanation, GaAs / AlGaAs was used as the material system.
However, the high speed semiconductor device according to the present invention is not limited to this material system and can be realized by other combinations. Furthermore, although the n-type semiconductor is used in the above embodiments, a p-type semiconductor may be used.

(Effects of the Invention) As is clear from the above detailed description, according to the present invention, a flip-flop with two outputs is provided by an extremely simple circuit configuration.
Since it is possible to realize a high-speed semiconductor device that enables a flop operation and also has a logical operation function, it will greatly contribute to future communication and information technology.

[Brief description of drawings]

1 and 2 are cross-sectional structural views showing an embodiment of the high speed semiconductor device of the present invention and a conduction band profile diagram corresponding thereto, and FIGS. 3 (a), (b) and (c) are the high speed semiconductor devices of the present invention. A conduction band profile diagram for explaining the basic operation of the semiconductor device, FIGS. 4 and 5 are a connection circuit diagram of a flip-flop using the high speed semiconductor device of the present invention and its operation current-voltage characteristic diagram, FIG. 6 and FIG. FIG. 7 is a connection circuit diagram of an exclusive OR / NOR circuit composed of the high-speed semiconductor device of the present invention and a current-voltage characteristic diagram for explaining its logical operation function,
8 and 9 are cross-sectional structural views showing another embodiment of the high-speed semiconductor device of the present invention and their corresponding conduction band profile diagrams, and FIGS. 10 and 11 are resonance tunnel hot electrons according to the prior art. A cross-sectional structure diagram of the transistor (RHET) and its energy band diagram, and FIG. 12 is a connection circuit diagram of a flip-flop configured using the conventional resonant tunneling hot electron transistor (RHET). 1 n-type GaAs common emitter layer, 2a ₁ , 2a ₂ , 2a ' ₂ ... non-doped GaAs quantum well layer, 2b ₁ , 2b ₂ ... non-doped AlGaA
s potential barrier layer, 2b ′ ₁ , 2b ′ ₂ ...... non-doped AlAs potential barrier layer, 3a, 3b …… n-type GaAs base layer, 4a, 4b …… non-doped AlGaAs collector-side barrier layer, 5a, 5b …… n-type GaAs collector layer, 9 ... Semi-insulating GaA
s substrate, 10 ... common emitter electrode, 11a, 11b ... base electrode, 12a, 12b ... collector electrode, 2a ' ₁ ... undoped I
nGaAs quantum well layer, 9 '... N ⁺ GaAs substrate layer, E ₁ , E ₂ , E ₁ ',
E ₂ ′ ... Sub-band level, T ... High-speed semiconductor device, R _S , R
₁ , R ₂ , R _a , R _b ... resistance, V _CC ... voltage source.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI technical display location H03K 17/56 19/08 Z

Claims (1)

[Claims] 1. A compound semiconductor substrate and a pair of resonant tunneling hot carriers in which one emitter layer is shared on the compound semiconductor substrate and a superlattice layer, a base layer and a collector layer are arranged in this order vertically symmetrically. · A pair of resonant tunnels, hot carriers
A high-speed semiconductor device, wherein the transistor is formed by generating subbands of electrons or holes having different energy levels in the quantum well layer forming the superlattice layer.