JPH0831472B2 - High-speed semiconductor device - Google Patents

Description

The present invention relates to a high-speed semiconductor device, and more particularly to a resonance tunnel
Regarding bipolar transistors.

[Prior art] Resonance tunnel effect is extremely promising for application to ultra-high-speed and new-function devices because the delay time required for the passage of electrons is remarkably short and the differential negative resistance characteristic is remarkable. Development has become active.

FIG. 10 and FIG. 11 are cross-sectional structural views of a conventional resonant tunneling bipolar transistor (RBT) and energy band diagrams showing the operation thereof, for example, Japanese Journal of Applied Physics by Niki et al. (Jpn.J.Appl.Phys.), Volume 26, L
131 pages, reported in 1987. This resonant tunneling bipolar transistor (hereinafter called RBT)
Although only one side surface of the axis of symmetry YY ′ is shown in the sectional view of FIG. 10, as shown in FIG. 10, the n-type AlGaAs emitter layer 1 formed on the N ⁺ GaAs substrate 9 and the superlattice are formed. The layer is composed of a sandwich layer of a non-doped GaAs quantum well layer 2a and a non-doped AlGaAs potential barrier layer 2b, a p-type GaAs base layer 3 and an n-type GaAs collector layer 5. here,
Reference numerals 10, 11 and 12 denote emitter, base and collector electrodes, respectively. In this RBT, electrons injected due to the resonance tunnel effect travel as hot electrons in the base layer 3, so that a remarkable differential negative resistance (ND
R), and can be configured as a flip-flop that operates at high speed.

FIG. 12 shows a connection circuit diagram of a flip-flop configured by using the conventional resonant tunneling bipolar transistor (RBT) described above.
Collector electrode 12 is driven by a voltage source V _CC through a resistor R, and the base electrode 11 is connected to a resistor R _S from an input terminal _S.
It operates by applying an input voltage via.
At this time, the potential of the contact point between the collector electrode 12 of the RBT and the resistor R is taken out from the output terminal Q, but by applying a bias potential to the input terminal S, the potential of the output terminal Q has two stable states. By inputting either one of positive and negative pulses to this bias potential to the input terminal S, it becomes possible to switch between these two states. Thus, by using this RBT, a simple flip-flop circuit can be obtained with one active element.

[Problems to be Solved by the Invention]

By the way, when a counter, a shift register, or the like is formed using flip-flops, it is required to obtain the output Q and its inverse output at the same time.
A one-output flip-flop as shown is difficult to use.
That is, in order to form a 2-output flip-flop by using such a 1-output flip-flop, it is necessary to use an inverter circuit at the same time. At this time, an increase in wiring delay time and output (Q,) Therefore, the high speed operation becomes difficult.

In view of such problems, an object of the present invention is to provide a high speed semiconductor device of a resonance tunnel effect bipolar transistor capable of realizing a two-output flip-flop operation with a simple circuit configuration.

[Means for solving the problem]

According to the present invention, a high-speed semiconductor device includes a compound semiconductor substrate and a superlattice layer, an opposite conductivity type base layer, and a one conductivity type collector layer that share one emitter layer of one conductivity type on the compound semiconductor substrate. The pair of identical-conductivity-type resonant tunneling bipolar transistors, which are arranged one after another in a vertically symmetrical manner, have different energies in the quantum well layers forming the superlattice layer. It is included that a level electron sub-band and a hole sub-band are generated respectively.

[Action]

According to the present invention, a pair of resonant tunneling bipolar transistors of the same conductivity type are independently formed on a single substrate, each of which is provided with a superlattice layer for generating subbands of electrons and holes having different energy levels. To be done. Therefore, each transistor can behave as a differential negative resistance element independently with respect to the input signal applied to the base layer, and the two-output flip-flop, exclusive OR
/ NOR and other logical operations can be performed by only one element.

〔Example〕

 Hereinafter, the present invention will be described in detail with reference to the drawings.

1 and 2 are a sectional structural view and a conduction band profile diagram corresponding thereto showing an embodiment of the high speed semiconductor device of the present invention, respectively. According to the present embodiment, the sectional view shows only one side surface of the axis of symmetry YY 'as in the conventional example, and the n-type AlGaAs common emitter layer 1 is sandwiched on the N ⁺ GaAs substrate 9 to form a pair of vertically symmetrical pairs. First and second non-doped layers having different thicknesses formed so as to dispose the RBT.
GaAs quantum well layers 2a ₁ and 2a ₂ and first and second non-doped A
l.5Ga.5As potential barrier layers 2b ₁ and 2b ₂ each having a pair of first and second superlattice layers and a pair of first and second P-type GasAs base layers 3a and 3b.
And a pair of first and second n-type GaAs collector layers 5a, 5b
And n ⁺ GaAs collector contact layer 6. Here, 10 , 11a, 11b and 12a, 12b are a common emitter electrode, a first and a second base electrode and a collector electrode, respectively. According to this embodiment, the electron and hole subbands En, Enh (n = 1, 2, ...) Are generated in the quantum well layer 2a _1, and the electron and hole subbands are generated in the quantum well layer 2a ₂ . Subbands E'n, E'nh (n = 1, 2, ...) Are generated respectively. As is generally known, when the width of the quantum well layer is L and the effective mass of carriers is m, the energy level of the subband is It is represented by. However, Is the Planck constant and π is the circular constant. Therefore, by appropriately setting the film thicknesses of the quantum well layers 2a ₁ and 2a ₂ , it becomes possible to make the energy levels En and E′n of the subbands in the two quantum well layers different from each other. In the present embodiment, the quantum well layer 2a ₁ is made thicker than the film thickness of 2a ₂ and the energy level of each subband is E1 <E′1 <E2 as shown in the profile of FIG. It is set to be in the order of.

The high-speed semiconductor device having such a structure operates as follows.

3 (a), (b) and (c) are conduction band profile diagrams for explaining the basic operation of the high speed semiconductor device of the present invention. Here, consider a case where the two base electrodes 11a and 11b are short-circuited and a signal pulse of a different level is applied thereto. In the following, in order to simplify the explanation, the common emitter layer 1 is defined as E, the base layer.
3a and 3b are called B, the collector layer 5a is called C, and the collector layer 5b is called C '.

Now, when the base-emitter voltage V _BE is about 2E1 / q (where q is the electron charge amount), as shown in FIG. 3 (a), the subband ground level E1 of the quantum well 2a ₁ is The electrons injected into the base due to the resonance tunnel effect in the above become hot electrons and reach the collector layer 5a, so that the current I _C flows through the collector C. On the other hand, light holes from the base layer 3a form the base current I _B injected into the emitter 1 by the resonance tunnel effect. At this time, no current flows through the collector C '. Here, when V _BE becomes about 2E′1 / q, a resonant tunnel occurs at the ground level E′1 in the quantum well 2a ₂ shown in FIG. 3B, and a current I _C ′ flows through the collector C ′. . At this time, the potential barrier layer
Since the barrier height in the valence band of 2b ₁ and 2b ₂ is low,
Since the double barrier structure is deformed and the resonance tunnel does not occur, the base current does not flow on the other RBT side. At this time, no current flows in the collector C on one RBT side. Further, when V _BE becomes about 2E2 / q, the energy level
A resonant tunnel occurs at E2, causing one collector C '
No current will flow through it. (See FIG. 3 (c)). In this way, one emitter layer 1 is shared and a pair of
In the high-speed semiconductor device of the present invention which constitutes the RBT, the collector I _C and the base current I _B of one RBT produce a differential negative resistance (NDR) at V _BE = 2E1 / q, and the other RBT has a collector. The current I _C ′ produces a differential negative resistance (NDR) at V _BE = 2E′1 / q. That is, since the collector current and the base current respectively exhibit differential negative resistance in response to different base-emitter voltages V _BE , it is possible to easily form a 2-output flip-flop or the like with a single element.

4 and 5 are a connection circuit diagram of a flip-flop using the high-speed semiconductor device of the present invention and an operating current-voltage characteristic diagram thereof, respectively.

The flip-flop based on the high-speed semiconductor device of the present invention is
The collector electrodes 12a and 12b are connected to the voltage source V _CC via resistors R1 and R2, respectively, to two high-speed semiconductor devices T of the present invention whose emitters are grounded, and the resistor R is connected to two commonly connected base terminals 11a and 11b. Flip-flop operation is performed by applying the input voltage via _S , and the collector electrode
The potentials of the contact between the resistor 12a and the resistor R1 and the contact between the collector electrode 12b and the resistor R2 are taken from the output terminals Q, Q, respectively. At this time, by applying the bias potential V _B to the input terminal S, the two stable states due to the differential negative resistance NDR in the base current I _B are changed to the base-emitter voltage V
It is formed in a low _BE state (V ₀ ) and a high _BE state (V ₁ ), respectively. The values of the low state (V ₀ ) and high state (V ₁ ) of the base-emitter voltage V _BE can be adjusted to V ₀ ≈ 2E1 / q, V ₁ ≈ 2E1 ′ / q by adjusting the resistance R _S. Can be set. Therefore, if V _BE is V ₀ , the collector C of one RBT becomes conductive and the collector current I _C flows according to FIG. 3 (a), and no current flows to the collector C ′ of the other RBT. , The output Q is in a low voltage state, that is, "L", and the output is in a high voltage state, that is, "H". If V _BE = V ₁ , then one R
No current flows through the collector C of the BT, and only the collector C'of the other RBT conducts, so the output Q is "H" and the output is "L".
It becomes a state.

By the way, when V _BE = V ₀ , when a positive pulse is input to the input terminal S with respect to the bias potential V _B , V _BE becomes V ₀
Changes from V ₁ to V ₁ and is inverted from the output Q, but V _BE
Is V ₀ , even if a negative pulse is input, V _BE
Remains at V ₀ , so the output is held. Similarly, V _BE
There the state made V _1, by inputting a negative pulse with respect to the bias potential V _B to the input terminal S, it is possible to transition the V _BE from V ₁ becomes state V ₀ becomes state. If the positive input is represented by S ₀ and the negative input is represented by R ₀ , the truth table of the input / output of the circuit of FIG. 4 becomes as shown in Table 1, and from now on, it should be the 2-output flip-flop operation. Is confirmed.

Further, according to the present invention, it is possible to simultaneously perform a plurality of logical operations such as exclusive OR and non-exclusive NOR.

FIG. 6 and FIG. 7 are a connection circuit diagram of an exclusive OR / NOR constituted by the high-speed semiconductor device of the present invention and a current-voltage characteristic diagram for explaining its logical operation function.

In the exclusive OR / NOR circuit according to the high speed semiconductor device of the present invention, the two collector electrodes 12a and 12b of the high speed semiconductor device T of the present invention whose emitter is grounded are connected to the voltage source V _CC via the resistors R ₁ and R ₂ , respectively. , Two input terminals A and B connected to two commonly connected base terminals 11a and 11b, and resistors Ra and R, respectively.
It operates when two different input voltages are applied via b, and the potentials of the contact between the collector electrode 12a and the resistor R _{1 and} the contact between the collector electrode 12b and the resistor R ₂ are respectively from the output terminals X and Y. Taken out. According to this circuit, the resistor Ra, by appropriately setting the Rb, it is possible to make 2 stable state does not occur in the base current I _B as Figure 5. Therefore, when the base-emitter voltage is low (V ₀ ) and high (V ₁ , V ₂ ), V ₀ ≈ 2
E1 / q and V ₁ ≈ 2E1 ′ / q, V ₂ ≈ 2E2 / q, and voltage V ₀ /
2 "0" level, V ₁ -V _0/2 "1" level in each set to the input terminal A, when it is assumed that give either the B, input A, also B are both at "0" If either of them is “1”, the base-emitter voltage V _BE becomes V ₀ or approximately V ₂ , respectively. Therefore, as is clear from the current-voltage characteristics of FIG. On the other hand, the collector C of one RBT becomes conductive, the collector current I _C flows, and the current I ′ _C does not flow in the collector C ′ of the other RBT. That is, the output of the output terminal X becomes "L" and the output of the output terminal Y becomes "H". Similarly, when inputs A and B are different from each other, V _BE
= V ₁ , the output X becomes "H" and the output Y becomes "L". The truth table shows this as shown in Table 2. It can be confirmed that X is the exclusive OR of A and B, and Y is the exclusive NOR of A and B.

8 and 9 are a cross-sectional structural view and a conduction band profile diagram corresponding thereto showing an embodiment of the high speed semiconductor device of the present invention, respectively. According to the present embodiment, the cross-sectional view thereof shows only one side surface of the axis of symmetry YY 'as in the previous embodiment, and the n-type AlGaAs common emitter layer 1 is sandwiched on the N ⁺ GaAs substrate 9 to form a vertically symmetrical pair. Non-doped In.1Ga.9As quantum well layer 2a ₁ ′ and non-doped AlAs potential barrier layer 2b ₁ ′ and non-doped GaAs quantum well layer 2a ₂ ′ and non-doped AlAs potential barrier layer 2b, respectively _A pair of first and second superlattice layers having a sandwich structure of ₂ ', a pair of first and second P-type GaAs base layers 3a and 3b, and a pair of first and second n-type GaAs. It includes collector layers 5a and 5b and an n ⁺ GaAs collector / contact layer 6. Here, 10 is a common emitter electrode, 11 _a and 11 _b are first and second base electrodes, respectively.
_2a and _12b are the first and second collector electrodes, respectively. According to the present embodiment, electron and hole subbands En, Enh (n = 1, 2, ...) Are generated in the quantum well layer 2a ₁ ′, respectively, and the quantum well layer 2a ₂ ′ is also generated. Generates electron and hole subbands E'n and E'nh, respectively. AlA
Although s and InGaAs have different lattice constants, InGaAs quantum well layer 2
By setting the thickness of a ₁ ′ to about 30 A and below the critical film thickness (about 100 A) at which misfit dislocations are formed, elastic strain becomes a strained lattice layer that relaxes lattice misalignment, and a good interface is formed. Since InGaAs has a narrower band gap than GaAs, the lower energy level of the conduction band is lower than that of the emitter layer 1 and the base 3a located on both sides by the conduction band offset (about 100 meV) in In.1Ga.9As / GaAs. Therefore, a conduction band profile such as the band shown in FIG. 9 is obtained, and E1 <E1 ′ <E2 is achieved even if the quantum well layers 2a ₁ ′ and 2a ₂ ′ are not made different in thickness as in the previous embodiment. A high speed semiconductor device according to the present invention can be realized. Although GaAs / AlGaAs is taken as an example of the material system in the above description, the high speed semiconductor device according to the present invention is not limited to this material system, and can be realized by other combinations.

〔The invention's effect〕

As will be apparent from the above detailed description, according to the present invention, a flip-flop having two outputs can be formed with an extremely simple circuit configuration.
Since it is possible to realize a high-speed semiconductor device that enables a flop operation and also has a logical operation function, it will greatly contribute to future communication and information technology.

[Brief description of drawings]

1 and 2 are cross-sectional structural views showing an embodiment of the high speed semiconductor device of the present invention and a conduction band profile diagram corresponding thereto, and FIGS. 3 (a), (b) and (c) are the high speed semiconductor devices of the present invention. A conduction band profile diagram for explaining the basic operation of the semiconductor device, FIGS. 4 and 5 are a connection circuit diagram of a flip-flop using the high speed semiconductor device of the present invention and its operation current-voltage characteristic diagram, FIG. 6 and FIG. FIG. 7 is a connection circuit diagram of exclusive OR / NOR constituted by the high speed semiconductor device of the present invention and a current-voltage characteristic diagram for explaining its logical operation function. FIGS. 8 and 9 are high speed semiconductor devices of the present invention, respectively. FIG. 10 is a cross-sectional structural view showing another embodiment of the present invention and its corresponding conduction band profile diagram, and FIG. 10 and FIG. 11 are resonance tunnel bipolar transistors (RB
FIG. 12 is a connection circuit diagram of a flip-flop formed by using the conventional resonant tunneling bipolar transistor described above, and FIG. 12 is a sectional structural view of T) and an energy band diagram showing its operation. 1 ... n-type AlGaAs common emitter layer, 2a, 2a ₂ , 2a ₂ '... non-doped GaAs quantum well layer forming superlattice layer, 2b ₁ , 2b ₂
...... Non-doped AlGaAs potential barrier layer forming superlattice layer, 2b ₁ ′, 2b ₂ ′ …… Non-doped AlAs potential barrier layer forming superlattice layer, 3a, 3b …… p-type GaA
s base layer, 5a, 5b ... n-type GaAs collector layer, 6 ... n ⁺ Ga
As collector layer, 9 ... n ⁺ GaAs substrate, 10 ... Common emitter electrode, 11a, 11b ... Base electrode, 12a, 12b ... Collector electrode, 2a ₁ '... Non-doped InGaAs quantum well layer, En, En' , E
nh, E'nh ... Subband level, T ... High-speed semiconductor device,
Rs, R1, R2, Ra, Rb, R …… Resistor, V _CC …… Voltage source.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical indication location H01L 29/201 29/73 29/88 H03K 3/313 H01L 27/06 101 B 29/88 S

Claims (1)

[Claims] 1. A compound semiconductor substrate and a superconducting layer, an anticonductivity type base layer and a one conductivity type collector layer which are formed on the compound semiconductor substrate so as to be shared by each other and are arranged symmetrically in the vertical direction. A pair of identical conductivity type resonant tunneling bipolar transistors, wherein the pair of identical conductivity type resonant tunneling bipolar transistors are arranged in the quantum well layer forming the superlattice layer. A high-speed semiconductor device characterized by being formed by forming sub-bands of holes respectively.