JPH0833554B2 - Semiconductor for image display device and manufacturing method thereof - Google Patents

Description

TECHNICAL FIELD The present invention relates to an image display device, and more particularly to a matrix type image display device.

2. Description of the Related Art In recent years, television images have been provided on a commercial basis using liquid crystal panels, although the size is as small as 2 to 6 inches due to the use of fine processing technology and liquid crystal materials and high-density packaging technology. .

Coloring of the display image is easily achieved by forming R, G, B colored layers on one glass substrate, and high contrast is achieved in the so-called active type in which a switching element is built in for each picture element. Guaranteed.

Such a liquid crystal panel typically has 120 to 240 scanning lines and 240 to 720 signal lines. As shown in FIG. 3, the scanning lines formed on one substrate 1 constituting the liquid crystal panel. Also, for example, a connection film 5 having a large number of gold-plated copper foils formed on a base of a polyimide resin thin film is pressed onto the terminal groups 3 and 4 of the signal lines, or the semiconductor integrated circuit chip 6 is directly attached. A means (implementation) for supplying an electric signal to the image display unit is provided. The wiring material that connects the electrode terminal group and the image display unit necessary for mounting does not have to be the same material, and is appropriately selected depending on the mounting method.

In addition, 2 is another glass plate having a common counter electrode made of a transparent conductive layer, the glass plate 1 and the glass plate 2 are formed with an appropriate distance, and the gap between the two glass plates is a sealing material. The closed space is sealed with a sealing agent, and the closed space is filled with liquid crystal. In a small to medium size liquid crystal panel, a color filter having a coloring layer on the closed space side of the glass plate 2 is generally used. When a TN type liquid crystal is used, for example, polarizing plates are attached on the upper surface of the glass plate 2 and the lower surface of the glass plate 1 to function as a liquid crystal panel.

FIG. 4 is an equivalent circuit of an active type liquid crystal panel. For example, a switch element 7 of an insulated gate transistor and a liquid crystal cell 8 are arranged at each intersection of the scanning line 3 and the signal line 4. Although the storage capacitor 9 is not necessarily an essential component, it reduces the utilization efficiency of video signals and image unevenness caused by the presence of parasitic capacitance between the gate and the source, or the switch element 7 and the liquid crystal cell. Flicker associated with leakage current in the holding state of 8 and uneven brightness at the top and bottom of the screen (brightness gradient)
It is extremely effective in suppressing. 10 is a counter electrode composed of a transparent conductive layer common to all the liquid crystal cells 8 described above,
11 is a common line for the storage capacitor 9, and generally 10
11 is connected and driven at the same potential.

Although there are considerable degrees of freedom in the structure and manufacturing method of the insulated gate transistor 7 and the storage capacitor 9, it is difficult to say that they have been established as a standard. However, here, a design example based mainly on the inventor's invention is used. Let's take it as an example.

FIG. 5 is a plan layout view of the unit picture elements, and FIG. 6 is a sectional view taken along the line AA ′ during the process. First, as shown in FIG. 6 (a), an ITO thin film having a film thickness of about 1000 Å is deposited on an insulating substrate 1, for example, a glass plate by sputtering or the like, and a pattern 11 is selectively left. This pattern forms a common line for all storage capacitors as described above, and measures for eliminating image unevenness at the time of writing of the storage capacitors due to the resistance value are disclosed in JP-A-61-17179. As I did. Note that firing at 300 to 500 ° C. in an atmosphere containing oxygen to increase the chemical stability of the ITO film is also preferably carried out at an appropriate stage in this step. Next, as shown in FIG. 6 (b), a CVD SiO ₂ layer 12 is deposited on the entire surface with a film thickness of, for example, 4000Å, and then a pixel electrode 13 made of an ITO film is selectively formed on the SiO ₂ film 12 again. To be deposited. With the SiO ₂ layer 12 as a dielectric,
It can be seen that a transparent storage capacitor having the ITO films 11 and 13 as electrodes is formed. Then, as shown in FIG. 6 (c), CV
After depositing the D SiO ₂ layer 14 on the entire surface with a film thickness of about 1000 Å,
An opening 15 is formed on the picture element electrode 13 to partially expose the picture element electrode 13. Although not shown, an opening is also formed in the common line 11 at an appropriate location outside the image display portion at this time, and the common line 11 is partially exposed. Further, as shown in FIG. 6 (d), a conductive layer that also serves as the scanning line and the gate of the insulated gate transistor.
16 is selectively deposited by, for example, stacking a 1000 Å Cr thin film and a 500 Å MoSi ₂ thin film. In addition, the above-mentioned opening
At the same time, 15 is also covered with the conductive layer 17, and the ITO film exposed on the glass plate 1 disappears at this point. Picture element electrode 1
The reason why the SiO ₂ layer 14 is required on the 3 is to prevent abnormal growth of the Si ₃ N ₄ film during the subsequent plasma CVD deposition as disclosed in Japanese Patent Laid-Open No. 59-9962, and the opening 15 conductive layer
The necessity of covering with 17 is to secure the contact resistance of the transparent conductive layer 13 as disclosed in Japanese Patent Laid-Open No. 58-199383, and the conductive layers 16 and 17 are formed by stacking metal and silicide. As described in JP-A-60-9167 and JP-A-61-44468, it is necessary to avoid increasing the resistance value of the scanning line, and to prevent the generation of a passive state on the surface of the conductive layer. Is. Reference is also made to the means for solving the problem that the conductive layers are laminated to increase the film thickness, which is also shown in the above-mentioned prior application.

After this, an active element, which is an essential element for becoming an active type, is formed, and as shown in FIG. 6 (e), the first silicon nitride layer 18 having a film thickness of, for example, 4000Å, 500Å, 1000Å is formed. (Si ₃ N ₄ ), the first containing almost no impurities
Of amorphous silicon layer 19 and then again a second Si ₃ N ₄ layer 20 are deposited, preferably continuously. Each of these thin films is produced by plasma CVD, which decomposes and synthesizes a source gas containing silane (SiH ₄ ) gas as a main component at a temperature of around 300 ° C by high frequency glow discharge. Gate the top Si ₃ N ₄ layer to gate 16
After a leave 20 'selectively only on, PH ₃ to SiH ₄ gas
Deposited the second amorphous silicon layer 21 containing a 500Å about the thickness of the impurity on the entire surface by a plasma discharge with the addition of gas, leaving the FIG. 6 (f) as shown in island Si ₃ N Expose ₄ 18 Continuing, as shown in Fig. 6 (g), Si ₃ N ₄
Openings 22 are formed in layer 18 to expose conductive layer 17. Since this opening formation process is an etching of Si ₃ N ₄ single layer, it is not necessary to apply dry etching with low productivity, and batch processing can be easily performed by batch processing with a hydrofluoric acid-based etching liquid. Is. At this time, although not shown, formation of an opening for connection to the gate 16 and the common line 11 and exposure of the mounting electrode made of ITO formed in the same step as the picture element electrode 13 for protection also protect the SiO ₂ layer 14 It is done at the same time by overeating enough to dissolve.
In the final step, as shown in FIG. 6 (h), a barrier layer 23 made of MoSi _{2 having} a film thickness of about 1000Å and Al having a film thickness of about 6000 to 10000Å are deposited by sputtering or the like, and the signal line 24 (source Wiring) or connection 25 between the pixel electrode 13 and the insulated gate transistor via the conductive layer 17 (drain wiring) and other wiring paths are formed by first leaving Al selectively and then by using Al as a mask. A semiconductor device for an image display device is completed by removing the unnecessary barrier layer 23 and the second amorphous silicon layer 21 'between the paths.

As disclosed in Japanese Unexamined Patent Publication No. 58-212177, the amorphous silicon layer 19 'that constitutes the channel of the insulated gate transistor and contains almost no impurities is a Si ₃ N ₄ layer 2 which is a protective film.
Since it is shielded from the outside air immediately after formation by 0 ', it is not only strong against external contamination, but also has the characteristic that its thickness and film quality are not affected except by the film forming process. The inclusion of the amorphous silicon layer 21 ensures good ohmic contact between the channel portion and the source / drain wiring. Introduction of heat resistant barrier layer
As disclosed in Japanese Patent Laid-Open No. 59-68975, this is a measure for improving the thermal stability of an insulated gate transistor, and a silicide compound is effective as a barrier layer.
No. 60-12770.

However, the above-described conventional example requires a large number of film forming steps, and inevitably requires as many as eight photomask steps, resulting in a long manufacturing step and a cost problem.

The present invention provides a semiconductor device for an image display device, which is based on the above-mentioned prior art and has a process that is as easy as an integrated circuit without any special or complicated process.

Means for Solving the Problems The rationalized device according to the present invention has a structure in which the pixel electrode and the gate electrode are first formed in a single photomask step. Next, there is a configuration that eliminates the storage capacitance. A device that has a storage capacitance and is rationalized is that the configuration of the storage capacitance is changed and one electrode is formed of the same member as the signal line, and the gate insulation film is used as an insulation film. It is obtained by utilizing. These streamlined devices naturally lead to a shortened manufacturing process, leading to improved productivity and yield.

The rationalization of the manufacturing process is achieved by introducing dry etching in the etching process for forming the opening and etching the multilayer film at once.

In implementing the above rationalized device and process, it was devised that stable ohmic contact can be obtained by exposing the transparent conductive layer by removing the metal layer in the opening for connection to the scanning line (gate line), The effects of the present invention are fully exhibited.

As described above, in the present invention, the transparent conductive layer and the metal layer constituting the gate are continuously deposited to selectively form the transparent conductive layer covered with the gate metal, and the exposed portion of the transparent conductive layer is formed. Since it is a pixel electrode, the rationalization of simultaneously forming the gate wiring and the pixel electrode can be achieved.

Further, according to the present invention, the pixel electrode and the gate insulating film are used instead of the storage capacitor and the two transparent electrodes and the dedicated insulating layer as in the conventional case, and the other electrode is formed simultaneously with the formation of the signal line. The rationalization eliminates the deposition of transparent electrodes, the deposition of insulating layers, and the cleaning steps associated with those steps. In the etching process, as will be described later, a through hole is formed all at once by dry etching in a multilayer film including an amorphous silicon layer containing impurities and an amorphous silicon layer containing no impurities, and a Si ₃ N ₄ layer and a SiO ₂ layer. By doing so, compared with the conventional manufacturing process, the photo-etching and etching processes of forming the opening in the SiO ₂ layer and islanding the amorphous silicon layer are rationalized and eliminated.

Embodiment FIG. 1 is a plan layout view of a unit pixel of a semiconductor device for an image display device according to an embodiment of the present invention.
2 (a) to 2 (e) are sectional views taken along the line A-A ', and FIGS. 2 (f) and 2 (f) are sectional views taken along the lines B-B' and C-C '.
(G). For the sake of convenience, parts having the same function will be assigned the same numbers as in the conventional example.

First, as shown in FIG.
ITO layer 26 with a thickness of about 00Å and Cr layer 27 as the first metal layer
Are laminated and attached. Next, the gate 16, which also serves as a scanning line,
A laminated pattern of the pixel electrodes 28 and the storage electrodes 28 and the connection portion 29 for the multilayer wiring is selectively formed. In order to mitigate the increase in film thickness due to lamination, the photosensitive resin used for pattern formation is a negative type, first Cr is slightly overetched, then the photosensitive resin is thermoplastically deformed by heat treatment. The ITO may be etched after the pattern width is widened by, and this method is exactly the same as the conventional laminated pattern formation of Cr and MoSi ₂ . Thereafter, as shown in FIG. 2B, a SiO ₂ layer 14 of about 1000 Å is deposited on the entire surface as a plasma protective layer. Then, as shown in FIG. 2 (c), the first
The Si ₃ N ₄ layer 18, a first amorphous silicon layer 19 containing no impurity, a second Si ₃ after N sequential depositing a _fourth layer 20, second only on the gate 16 Si ₃ N ₄ The layer is selectively left to be 20 '. Then, a second amorphous silicon layer 21 containing impurities is deposited on the entire surface, and then the laminated portion 28 is formed as shown in FIG. 2 (d).
Openings 31 and 32 are selectively formed in the opening, and an opening 33 is selectively formed in the laminated portion 29. It is necessary to form this opening for three different kinds of film quality such as the second and first amorphous silicon layers 21 and 19, the first Si ₃ N ₄ layer 18, and the protective SiO ₂ layer 14. Since the eaves is generated on the cross section and the chemical resistance of the photosensitive resin pattern 30 becomes a problem in the wet processing, it is possible to obtain a desirable result by penetrating with the Freon reactive dry etching (RIE method) at a stretch. Also, when this etching is completed, the side etch proceeds only after the Cr in the laminated layer is exposed, so that sufficient over-etching is sufficient for the unevenness of the film thickness and film quality of the Si ₃ N ₄ layer 18. The problem that the opening becomes abnormally large due to insufficient adhesion of the photosensitive resin, such as when over-etching with conventional hydrofluoric acid-based etching, is created. Does not occur.

An approach to reduce the mask process by stacking a transparent conductive layer and a gate metal is also disclosed in JP-A-61-134070, which can be regarded as an improvement in JP-A-58-199383. Only effective by heating the photosensitive resin and a protective SiO ₂ layer.

After removing the first and second amorphous silicon layers and the first and second insulating layers in the openings 31, 32 and 33, the Cr on the surface of the laminated portion exposed in the openings is removed to be transparent. Exposing the conductive layer.

It will be understood that the large opening 32 formed in the laminated portion 28 that also serves as the pixel electrode and one of the storage capacitor electrodes functions as the pixel electrode 34 when Cr is removed. The final step is the barrier layer as shown in FIGS. 2 (e) to (g).
After depositing MoSi ₂ as 23 and Al as a wiring layer, first, Al
Then, the unnecessary barrier layer 23 and the second amorphous silicon layer 21 are removed by using Al as a mask to form the necessary wiring paths such as the source / drain wirings 24 and 25 to display an image according to the present invention. The device semiconductor device is completed.

If you want to incorporate a storage capacitor, place a second
1, second insulating layers 14 and 18 and first and second amorphous silicon layers 19,
21 is left and the electrode 35 is formed when the source / drain wiring is formed.
Should be formed. However, when the electrode 35 is arranged orthogonally to the signal line 24, as shown in FIG.
It is necessary to perform multilayer wiring by using the opening 33.

When the storage capacitor is not required, it is not necessary to form the storage capacitor electrode 35, and as a matter of course, the opening 34 of the pixel electrode becomes large and a bright image can be obtained. In this case, the lower electrode 29 of the multilayer wiring is not necessarily an essential constituent factor, and from the viewpoint of the resistance value, the reliability of the connection, the generation of unnecessary steps, etc., the adoption is stopped and the source wiring 24 (signal line) is replaced. It is desirable to extend it as it is to obtain the desired result.

EFFECTS OF THE INVENTION As described above, by eliminating or rationalizing the storage capacity, the number of film formations is reduced, and accordingly, the cleaning process, the photo-etching process and the etching process are all reduced, and the manufacturing process is shortened. Needless to say that it was possible to contribute to cost reduction by reducing the number of production facilities, and because the manufacturing process is short, the chances of dust adhesion are reduced and the yield can be improved.

Further, in the present invention, the number of photomasks is halved to four, and
Since Cr is a metal that easily forms a passive state, there was a great risk of contact failure, but contact failure occurs by removing Cr in all openings and exposing the transparent conductive layer after forming the openings. You can obtain a remarkable effect such as no longer. In the present invention, since there is always a metal layer around the picture element electrode, if the unit picture element is small, that is, if high density is required, there is a drawback that the aperture ratio decreases, but some of them are about 1 mm or less. In the case of resolving power, the reduction of the aperture ratio is compensated for, and there are some merits. The same applies to the rationalization of storage capacity.

[Brief description of drawings]

FIG. 1 is a plan layout view of a unit pixel of a semiconductor device for an image display device according to an embodiment of the present invention, FIG. 2 is a sectional view of an essential part of the device, and FIG. 3 is a perspective view of a matrix type liquid crystal panel. Fourth
FIG. 5 is the same active type equivalent circuit diagram, and FIG.
FIG. 6 is a cross-sectional view of the main part manufacturing process of the device. 1 ... glass substrate, 14 ... first insulating layer (SiO ₂ ), 16 ...
… Gate (scan line), 18 …… Second insulating layer (Si ₃ N ₄ ), 1
9 ... First amorphous silicon layer containing no impurities, 20 ...
... third insulating layer (Si ₃ N _4), the second amorphous silicon layer containing 21 ...... impurities, 23 ...... barrier layer, 24 ...... source wiring (signal line), 25 ...... drain wiring, 26: transparent conductive layer,
27 …… First metal layer, 28,29 …… Laminate part, 31,32,33 ……
Aperture, 34 …… Pixel electrode, 35 ……-Storage capacitor negative electrode.

Claims (4)

[Claims] 1. A gate is a laminate of a transparent conductive layer selectively deposited on an insulating transparent substrate in the same photo process and a first metal layer, and is partially formed on the first metal layer. A first amorphous silicon layer containing almost no impurities on the gate stack through the first insulating layer and the second insulating layer serving as the gate insulating layer, with the transparent conductive layer stacked as a pixel electrode A third insulating layer is selectively formed on the first amorphous silicon layer on the gate stack, and the first amorphous silicon including a part of the third insulating layer. A second amorphous silicon layer containing impurities is formed on the layer, and a second metal layer selectively deposited on the second amorphous silicon layer via a barrier layer is used as a source. Insulated gate transistors used as drain wiring are arranged in a two-dimensional matrix, The first metal layer partially on pixel electrode and the first and second insulating layers are formed for an image display device wherein a. 2. A step of selectively depositing and forming a laminated pattern of a transparent conductive layer and a first metal layer on an insulating transparent substrate, and a step of depositing the first insulating layer on the entire surface and then a gate insulating layer. A second insulating layer, a first amorphous silicon layer containing almost no impurities, and a third insulating layer are sequentially deposited,
A second amorphous silicon layer containing impurities is exposed on the entire surface of the first amorphous silicon layer by partially leaving the third insulating layer formed on the laminated pattern to be a gate. A step of depositing, a step of selectively forming openings penetrating the first and second amorphous silicon layers and the first and second insulating layers on the laminated pattern, and a step of forming a first opening in the opening. The step of removing the first metal layer, and after depositing the barrier layer and the second metal layer on the entire surface, the second metal layer including a part of the third insulating layer and a part of the opening is formed. An image display device comprising a step of selectively leaving source / drain wirings and the like, and a step of selectively removing the barrier layer and the first and second amorphous silicon layers by using the wirings and the like as a mask. Manufacturing method of semiconductor device. 3. A laminate of a transparent conductive layer selectively deposited and formed on an insulating transparent substrate in the same photo step and a first metal layer is used as a gate and a connection wiring, and part of the first and second wiring layers is formed. The transparent conductive layer in which the metal layer of
A first amorphous silicon layer containing almost no impurities is formed on the gate stack through a first insulating layer and a second insulating layer serving as a gate insulating layer, and a first non-silicon layer on the gate stack is formed. A third insulating layer is selectively formed on the crystalline silicon layer, and second amorphous silicon containing a part of the third insulating layer and containing impurities on the first amorphous silicon layer. A second metal layer selectively deposited on the second amorphous silicon layer via a barrier layer.
Insulated gate transistors serving as drain wirings are arranged in a two-dimensional matrix, and first metal layers and first and second insulating layers are partially formed on the picture element electrodes, and the connection is made. A line connected to the source line as a lower line of the multi-layered line and intersecting the lower line via the first and second insulating layers, the first and second amorphous silicon layers, and the barrier layer. Is formed simultaneously with the source / drain wiring. 4. A step of selectively depositing and forming a laminated pattern and a connection pattern comprising a transparent conductive layer and a first metal layer on an insulative transparent substrate, and after depositing the first insulating layer on the entire surface,
A step of sequentially depositing a second insulating layer to be a gate insulating layer, a first amorphous silicon layer containing almost no impurities, and a third insulating layer; and a step of forming a second insulating layer to be a gate on the laminated pattern. The third insulating layer is partially left to selectively remove the first
Exposing the amorphous silicon layer and depositing a second amorphous silicon layer containing impurities on the entire surface, and the first and second amorphous silicon layers and the first and second amorphous silicon layers on the stacking pattern and the connection pattern. The step of selectively forming an opening penetrating the first and second insulating layers, the step of removing the first metal layer in the opening, and the step of depositing the barrier layer and the second metal layer on the entire surface. , A part of the third insulating layer, an opening on the connection pattern and a part of the laminated pattern to selectively leave the second metal layer as a source / drain wiring, and the connection. A method of manufacturing a semiconductor device for an image display device, which comprises a step of selectively removing a barrier layer and first and second amorphous silicon layers by using a wiring crossing a pattern as a storage capacitance line and using the wiring group as a mask. .