JP2692282B2 - Digital transmission equipment - Google Patents

Description

TECHNICAL FIELD The present invention relates to the configuration of a digital transmission device in a PCM transmission system, and more particularly to gigabits / second (Gb / sec).
s) The present invention relates to improvement of the feasibility of a timing extraction circuit and a discrimination circuit in a digital transmission device that transmits information.

[Conventional technology]

With the progress of optical transmission technology, studies on ultra-high-speed optical transmission technology using long-wavelength optical devices / single-mode fibers have been promoted as a possibility for large-capacity / long-distance transmission systems, especially for images, data, and voice. In order to realize a wideband information communication network that provides a wide variety of services, it is expected that the speed and stability of optical transmission equipment will be put into practical use. The transmission capacity of the backbone transmission system in such a broadband information communication network reaches, for example, several gigabits per second in a time division multiplex transmission system, and the optical transmitter / receiver is required to have a wide band / high speed.

Usually, the basic functions of a PCM regenerator are roughly classified into three types: (1) shaping by equalization amplification (reshaping), (2) retiming, and (3) identification regeneration. . The general structure is as shown in FIG. 2, a circuit that performs three basic functions, that is, an amplifier circuit 201,
It usually has a timing extraction circuit 202 and an identification circuit 203 (Reference: Publication "Basics and New Technologies of PCM Communication")
Industry report).

As in the conventional example of FIG. 2, a timing extraction circuit 202 having a role of giving a time point at the center of the eye in order to correctly identify the waveform equalized by the amplification circuit 201 is provided, and is generally used in a PCM transmission system. In this case, a timing extraction circuit that extracts a timing component from the transmitted code sequence itself is used.

FIG. 3 is a block diagram of a conventional timing extraction circuit. The code format of the input signal is assumed to be NRZ code. NRZ
Since a code or a bipolar code does not have a timing component in itself, a timing signal is generally extracted by a non-linear timing extraction method to generate a clock signal.

In FIG. 3, the NRZ code input to the input terminal is subjected to code change point detection by the differentiating circuit 301, and the double-wave rectifying circuit 302
At, the double wave rectification is performed to extract the f ₀ component.
The output signal of the both-wave rectification circuit 302 is further applied to the resonance circuit (timing tank) 303 to extract the f ₀ sine wave component (clock signal). As the resonance circuit 303, since a timing deviation is regarded as an important characteristic, a surface acoustic wave filter (SAW filter) designed with a relative bandwidth Q of about 800 is considered in consideration of temperature characteristics, secular change, detuning and the like. Used (Reference: Publication "Surface wave devices and their applications", Nikkan Kogyo Shimbun). On the other hand, when the code format of the input signal is RZ, since the signal itself has a clock component, the input signal is directly applied to the surface acoustic wave filter 303 to extract a sine wave clock signal.

Further, the identification circuit 203 in FIG.
It has a function to identify whether the received signal is "1" or "0" by using the clock signal extracted in 1. and is directly related to transmission characteristics such as error rate characteristics. . The discrimination circuit 203 is required to have the same operating speed as the frequency of the clock signal, that is, the data speed of the transmission line.

[Problems to be solved by the invention]

However, in such a conventional digital transmission device,
In the form of a timing extraction circuit, that is, a surface acoustic wave filter is used as a timing tank and a clock signal of f ₀ component in the GHz region is directly generated, there is a limit in the usable frequency region due to a problem of fine processing of the surface acoustic wave filter. At the same time, there is a problem in that the yield in the process is reduced, which leads to a decrease in the productivity of the PCM transmission device using this.

That is, the fundamental frequency f of the surface wave excited in the surface acoustic wave filter is determined by the surface wave propagation velocity V of the material and the electrode pitch L, and f = V / L. Therefore, when the excitation frequency is in the GHz region, the surface wave propagation velocity is generally 3 × 10 ³
Since it is (m / s), the electrode width must be 1 μm or less. As a specific example, the electrode width of the surface acoustic wave filter used for the 4 Gbps optical regenerator is 0.2 μm using a quartz substrate as the material, and the electrode length is 400 μm.
m (Ref: “Prototype of 4 Gbps optical regenerator”, Institute of Electronics, Information and Communication Engineers, Proceedings of General National Convention of 1987). In order to accurately process such an electrode width, there is a limit in processing technology such as photo etching and laser processing, so that it is difficult to realize a surface acoustic wave filter, and the PCM signal transmission device in the Gbps region is difficult to realize. There was a big problem that the timing extraction circuit could not be realized.

Furthermore, as the transmission capacity increases, the operating speed of the identification circuit is required to be high, and it becomes more difficult to commercialize an identification circuit with a medium-scale level of integration and commercialize it. There was a problem that was connected.

An object of the present invention is to provide a digital transmission device that solves the above problems.

[Means for solving the problem]

According to the present invention, in a digital transmission device having at least a timing extraction function and a discrimination function, a first timing extraction filter for extracting a basic timing component from an input received signal, and an output signal of the first timing extraction filter are / N
A frequency dividing circuit that divides the frequency into two, a first logical sum circuit that performs logical sum processing of the output signal of the frequency dividing circuit as one input signal and the other input signal, and an output of the first logical sum circuit A second timing extraction filter for extracting a stable timing signal of 1 / N frequency from the signal, and 1 / N extracted by the second timing extraction filter
A clock distribution circuit that distributes a clock signal of N + 1 phase and 1 / N frequency, which is optimum for performing a discrimination operation of the received signal from a frequency timing signal, and a constant delay to the N + 1th signal output from the clock distribution circuit A delay circuit for giving a time and inputting it to the first OR circuit as the other input signal, and a reception signal that is N-branched to the reception signal and is respectively input to the N-branching reception signal at the 1 / N frequency clock signal. It is characterized in that it comprises N discriminator circuits for discriminating signals, and a second OR circuit for ORing the output signals of the N discriminator circuits and outputting the signals.

[Action]

An identification circuit that extracts a coarse timing component from an input signal, divides the coarse timing component into a frequency region of 1 / N, generates a clock signal with a highly stable timing tank, and divides the clock signal into N pieces. To 1 / each
By adopting a configuration in which the identification reproduction signal is obtained by taking the logical sum of the identification results at N frequencies, it is possible to improve the feasibility of the timing extraction circuit in the GHz region and the feasibility of the entire transmission device.

〔Example〕

 Embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a digital transmission apparatus which is an embodiment of the present invention. This digital transmission apparatus includes an amplifier circuit 201 that amplifies a received signal that is input, a first timing extraction filter 104 that extracts a basic timing component from the amplified received signal, and an output signal of the first timing extraction filter. A frequency dividing circuit 105 that divides the frequency to 1 / N, and a first logical sum circuit 109 that performs logical OR processing with the output signal of the frequency dividing circuit as one input signal and the other input signal from the delay circuit described later. , Stable 1 from the output signal of the first OR circuit
A second timing extraction filter 106 for extracting a timing signal of / N frequency, and an N + 1 phase optimum for performing a receiving signal identification operation from the timing signal of 1 / N frequency extracted by the second timing extraction filter, and A clock distribution circuit 107 for distributing a clock signal of 1 / N frequency, and a delay circuit 1 for giving a constant delay time to the N + 1th signal output from the clock distribution circuit and inputting it to the first OR circuit 109.
08, the received signal is branched into N and input respectively, and the received signal branched into N is discriminated by the clock signal of 1 / N frequency N
It is composed of a plurality of latch circuits 101-1 to 101-N and a second logical sum circuit 103 which performs logical sum processing of output signals of these latch circuits and outputs the signals.

In the description below, the RZ (return to zero) code is assumed as the code format of the received signal.

The RZ reception signal input to the input terminal 100 is sufficiently amplified by the amplifier 201 and then applied to the latch circuits 101-1 to 101-N and the first timing extraction filter 104.

The first timing extraction filter 104 extracts a clock signal synchronized with the frequency f ₀ from the input RZ reception signal with coarse accuracy. Therefore, the timing tank to be used may be a filter having a relative band Q capable of extracting a clock signal that does not affect the amount of timing jitter (about 500 or less).

Rough f extracted by the first timing extraction filter 104
_{The 0-} component clock signal is counted down by the 1 / N frequency dividing circuit 105 at an arbitrary frequency dividing ratio N. This divider 105
As the frequency division ratio N, the frequency division ratio N can be arbitrarily selected so that the frequency division can be realized in a region where a high Q timing tank can be realized.

Clock signal f ₀ / N divided by 1 / N by 1 / N divider 105
Is input to the first OR circuit 109. In this first OR circuit 109, the signal input from the delay circuit 108 and 1 /
An output signal is generated by performing an OR operation with the signal input from the N frequency dividing circuit 105. Now, assuming that the time process is the initial stage, since the signal from the delay circuit 108 is no signal, the output signal of the first OR circuit 109 is the signal component input from the 1 / N frequency dividing circuit 105. Became dominant f ₀ /
The N component signal is output.

The output signal of the first OR circuit 109 is input to the second timing extraction filter 106. The center frequency of the second timing extraction filter 106 is set to f ₀ / N, and the high specific bandwidth Q is set in consideration of timing deviation, detuning, and the like.
Must be set to. Considering aging and temperature characteristics, it is desirable to use a surface acoustic wave filter (SAW filter) as the timing tank.

In FIG. 1, assuming that f ₀ is 4 GHz and the division ratio N is 8, f ₀ / N is 500 MHz. When the second timing extraction filter 106 is a surface acoustic wave filter made of quartz, the surface acoustic wave wavelength is about 6.3 μm. If the strip width and the gap of the interdigital electrode are selected to be equal, the strip width is about 1.6 μm, and such an electrode pattern can be formed by a normal photoetching technique.

The clock signal of f ₀ / N having a stable characteristic extracted by the second timing extraction filter 106 is a clock distribution circuit.
Supplied to 107. The clock distribution circuit 107 generates a clock signal whose frequency is divided by +1, that is, N + 1, from each other by T / N (T: one cycle time) from the input signal, and each of the latch circuits 101- Supply 1 to 101-N. Also N +
The first signal is input to the delay circuit 108, given a certain delay, and then supplied to the first OR circuit 109.

Therefore, as the output signal of the first OR circuit 109, the stable f ₀ / N clock signal input from the delay circuit 108 and the clock signal of the coarse f ₀ component from the first timing extraction filter 104 are 1 / The f ₀ / N clock signal as a result of performing the logical sum processing with the signal divided by N is output.

Each of the latch circuits 101-1 to 101-N latches the input received signal by the clock signal from the clock distribution circuit 107 and outputs it. Therefore, at this stage, the received signal has been subjected to the identification processing, and as a result, is converted into N series of data. The output signals of the latch circuits 101-1 to 101-N are input to the second logical sum circuit 103, the logical sum thereof is calculated, and the result is output to the output terminal 110. Therefore, the received signals that are identified at this stage and expanded in parallel become the signals converted into the original serial signals, and the signals that have been further identified and reproduced.

As described above, the high Q surface acoustic wave filter required for timing extraction is used in the frequency range of 1 / N to improve the feasibility of the timing extraction circuit of the high-speed PCM signal transmission system. At the same time, it is possible to realize an identification circuit that performs an identification operation with a stable clock signal.

In the above description, the code format of the received signal is RZ
Although the present invention has been described above, the present invention is also effective in the case of NRZ, and the differentiating circuit 30 as in the conventional example shown in FIG.
A similar form can be obtained by connecting to the first timing extraction filter 104 of FIG. 1 after going through the non-linear means of the double wave rectification circuit 302.

〔The invention's effect〕

As described above, the use of the digital transmission device according to the present invention improves the feasibility of the timing extraction circuit, the identification circuit, and the transmission device in the high-speed PCM signal transmission system.

[Brief description of the drawings]

 FIG. 1 is a configuration diagram showing an embodiment of the present invention, and FIGS. 2 and 3 are diagrams for explaining a conventional technique. 100 ... input terminal 101-1 to 101-N ... latch circuit 103,109 ... logical sum circuit 104 ... first timing extraction filter 105 ... 1 / N frequency dividing circuit 106 ... second timing extraction filter 107 ...... Clock distribution circuit 108 …… Delay circuit 110 …… Output terminal

Claims (1)

(57) [Claims] 1. A digital transmission device having at least a timing extraction function and an identification function, wherein a first timing extraction filter for extracting a basic timing component from an input received signal, and an output signal of the first timing extraction filter are provided. A frequency dividing circuit for dividing the frequency into 1 / N, a first logical sum circuit for performing logical sum processing of the output signal of the frequency dividing circuit as one input signal and the other input signal, and the first logical sum A second timing extraction filter for extracting a stable timing signal of 1 / N frequency from the output signal of the circuit, and an operation of identifying the received signal from the timing signal of 1 / N frequency extracted by the second timing extraction filter A clock distribution circuit that distributes a clock signal having an N + 1 phase and a 1 / N frequency, which is optimum for performing the above, and an N + 1th signal output from the clock distribution circuit. A delay circuit for giving a constant delay time and inputting it to the first OR circuit as the other input signal, and a reception signal which is N-branched and input respectively, and is N-branched by the clock signal of the 1 / N frequency. And a second OR circuit for performing OR operation on output signals of the N identification circuits and outputting the signal. Digital transmission equipment.