JPH084088B2 - Thin film formation method - Google Patents
Thin film formation methodInfo
- Publication number
- JPH084088B2 JPH084088B2 JP61040347A JP4034786A JPH084088B2 JP H084088 B2 JPH084088 B2 JP H084088B2 JP 61040347 A JP61040347 A JP 61040347A JP 4034786 A JP4034786 A JP 4034786A JP H084088 B2 JPH084088 B2 JP H084088B2
- Authority
- JP
- Japan
- Prior art keywords
- film
- thin film
- unevenness
- substrate
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000010409 thin film Substances 0.000 title claims description 20
- 238000000034 method Methods 0.000 title claims description 16
- 230000015572 biosynthetic process Effects 0.000 title description 3
- 239000010408 film Substances 0.000 claims description 54
- 239000000758 substrate Substances 0.000 claims description 31
- 239000004020 conductor Substances 0.000 claims description 20
- 238000004544 sputter deposition Methods 0.000 claims description 19
- 238000000151 deposition Methods 0.000 claims description 17
- 230000008021 deposition Effects 0.000 claims description 12
- 239000002245 particle Substances 0.000 claims description 10
- 229910052782 aluminium Inorganic materials 0.000 description 8
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 8
- 230000000694 effects Effects 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 3
- 229910052814 silicon oxide Inorganic materials 0.000 description 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910052786 argon Inorganic materials 0.000 description 2
- 238000001312 dry etching Methods 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 239000007789 gas Substances 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- -1 molybdenum Chemical class 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 229910021332 silicide Inorganic materials 0.000 description 1
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 description 1
- 238000004088 simulation Methods 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Landscapes
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Physical Vapour Deposition (AREA)
- Electrodes Of Semiconductors (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は、薄膜形成方法に関するもので、特に急峻な
側面を持ち微細でアスペクト比の高い凹凸のある基板表
面に、表面平坦性の良い薄膜を形成する方法に関するも
のである。Description: TECHNICAL FIELD The present invention relates to a thin film forming method, and particularly to a thin film having good surface flatness on a substrate surface having sharp sides and being fine and having a high aspect ratio. It relates to a method of forming.
（従来の技術） 半導体装置において配線を行う場合には、基板101上
の表面を保護する絶縁膜にコンタクトホールを開けて、
その上に導体膜を堆積することによりなされる。最近の
LSI等におけるコンタクトホールの形成は、露光技術や
ドライエッチング技術の進歩により、膜厚１〜２μｍの
絶縁膜102に約１μｍ角程度のものが可能となってい
る。このようなコンタクトホールは側面が急峻で段差が
大きいため、従来の平行平板型のスパッタ法あるいは蒸
着法で導体膜を堆積させると第２図に示すように、コン
タクトホールの段差の肩部分に多く堆積された導体膜20
1自身のシャドー効果のため段差被覆性が悪くなり、配
線が切れたり薄くなったりし易く、LSIの製造歩留まり
や信頼性が著しく低下していた。こうした欠点を防ぐた
め、微細なコンタクトホールの側面をテーパー形状とし
て傾斜を持たせ導体膜が均一に堆積するような形状が用
いられるようになってきているが、微細なコンタクトホ
ールの側面に傾斜を持たせることはLSIの高集積化を阻
害することになり、好ましい改善法ではない。その為、
急峻で高アスペクト比の溝あるいはコンタクトホールに
対して段差被覆性の良い状態で導体膜を堆積する方法が
提案されており、そのうちの１つとしては、プラネタリ
ー型の基板ホルダーを用いるスパッタ法がある。この方
法ではスパッタ粒子の飛来方向を乱雑にして段差被覆性
をよくしている。プラネタリー型のスパッタ法が平行平
板型のスパッタ法に比べて、段差被覆性の良い事は実験
的に検証されている。さらに最近では、膜形成時に基板
側にも電力を印加し、基板表面で、膜堆積とスパッタエ
ッチングを同時に行うというバイアススパッタ法によ
り、裏面に凹凸のある基板上に薄膜を段差被覆性良く、
あるいはコンタクトホール内を密に埋め込み、表面平坦
に堆積することも行われている。(Prior Art) When wiring is performed in a semiconductor device, a contact hole is opened in an insulating film that protects the surface of the substrate 101,
This is done by depositing a conductor film on it. Recent
With the progress of exposure technology and dry etching technology, it is possible to form a contact hole in an LSI or the like on an insulating film 102 having a film thickness of 1 to 2 μm, which is about 1 μm square. Since such a contact hole has a steep side surface and a large step, when a conductive film is deposited by the conventional parallel plate type sputtering method or vapor deposition method, as shown in FIG. Deposited conductor film 20
(1) Due to the shadow effect of itself, the step coverage deteriorates, the wiring is easily cut or thinned, and the manufacturing yield and reliability of the LSI are significantly reduced. In order to prevent such a defect, a side surface of a fine contact hole is tapered to have a slope so that a conductor film is uniformly deposited. The inclusion of this will hinder the high integration of the LSI and is not a preferable improvement method. For that reason,
A method for depositing a conductor film on a steep groove with a high aspect ratio or a contact hole with good step coverage has been proposed. One of them is a sputtering method using a planetary-type substrate holder. is there. In this method, the flying direction of the sputtered particles is made random to improve the step coverage. It has been experimentally verified that the planetary sputtering method has better step coverage than the parallel plate sputtering method. More recently, a bias sputtering method in which electric power is applied to the substrate side during film formation to simultaneously perform film deposition and sputter etching on the substrate surface, has a good step coverage of a thin film on a substrate with unevenness on the back surface.
Alternatively, the contact holes are densely filled and the surface is flatly deposited.
（発明が解決しようとしている問題点） 最近、プラネタリー型のスパッタ法による微細で深い
溝の段差被覆性についてのシュミレーションと実験との
比較がエイ・アール・ノイロイター（A.R.Neureuther）
らによりアイ・イー・イー・イー・トランザクションズ
オンエレクトロンデバイス（IEEE Trans.on ED.）27,14
49（1980）に報告されている。その報告によれば幅２μ
ｍ、アスペクト比（深さ／幅）0.5の溝に対してプラネ
タリー型のスパッタ法で膜を堆積すると、シャドー効果
のために段差被覆性が極めて悪化することが述べられて
いる。さらに最上らにより、1985プロシーディングセカ
ンドインターナショナルアイ・イー・イー・イーブイエ
ルエスアイマルチレベルインターコネクションカンファ
レンス（Proceeding Second International IEEE VLSI
Multilevel Interconnection Conference）,17〜13頁
（1985）に示されているように、バイアススパッタ法に
よる薄膜形成においても、表面の凹凸のアスペクト比が
ある程度以上大きくなると、通常のスパッタ法の場合と
同様に凹部に薄膜の堆積しない領域が残るという問題が
あった。(Problems to be solved by the invention) Recently, a comparison between the simulation and the experiment on the step coverage of a fine deep groove by the planetary type sputtering method is compared with ARNeureuther.
IE eTransactions on Electron Device (IEEE Trans.on ED.) 27,14
49 (1980). According to the report, width 2μ
It is stated that when a film is deposited on a groove having an m and an aspect ratio (depth / width) of 0.5 by a planetary type sputtering method, the step coverage is extremely deteriorated due to the shadow effect. Furthermore, according to Mogami et al., 1985 Proceeding Second International IEEE VLSI
Multilevel Interconnection Conference), pp. 17 to 13 (1985), even in thin film formation by bias sputtering, if the aspect ratio of the surface irregularities becomes larger than a certain level, the same as in the case of normal sputtering. There is a problem that a region where a thin film is not deposited remains in the recess.
本発明の目的は以上述べたごとき、従来の薄膜形成方
法の問題点に関して、特に高アスペクト比で微細な凹凸
に導体堆積膜を平坦性良く堆積する方法を提供すること
にある。As described above, an object of the present invention is to provide a method for depositing a conductor deposition film on a fine unevenness with a high aspect ratio with good flatness, with respect to the problems of the conventional thin film forming method.
（問題を解決するための手段） 本発明によれば、少なくとも基板表面の凹凸の凹部よ
りスパッタターゲットを見込む領域以外からのスパッタ
粒子の進入を遮蔽し、穴を有する遮蔽板をスパッタター
ゲットと基板との間に設け、該遮蔽板の穴を狭めて、基
板表面の凹凸の凸部の肩より生じる堆積膜の基板水平方
向へのせりだしを抑制するバイアススパッタ条件で導体
薄膜を堆積する第１の工程と、該遮蔽板の穴を広げてス
パッタ粒子の飛来方向分布を広げ、該凹凸の凹部の導体
膜の膜堆積速度が該凹凸の凸部の導体膜の膜堆積速度よ
りも大きいバイアススパッタ条件で導体薄膜を堆積し、
該凹凸の凹部の導体薄膜の膜厚を該凹凸の凸部の高さと
該凹凸の凸部上の導体薄膜の膜厚との和にほぼ等しくす
る第２の工程とを含むことを特徴とする薄膜形成方法が
得られる。(Means for Solving the Problem) According to the present invention, a shield plate having a hole is provided to shield sputtered particles from entering from a region other than the region in which the sputter target is seen through at least the concave and convex portions of the substrate surface. And a conductive thin film is deposited under a bias sputtering condition in which the hole of the shielding plate is narrowed to suppress the protrusion of the deposited film in the horizontal direction of the substrate caused by the shoulder of the convex portion of the unevenness of the substrate surface. Bias sputtering conditions in which the film deposition rate of the conductor film in the concave portion of the unevenness is larger than the film deposition rate of the conductive film in the convex portion of the unevenness To deposit a conductor thin film with
A second step of making the thickness of the conductor thin film in the concave portion of the irregularities substantially equal to the sum of the height of the convex portion of the irregularity and the film thickness of the conductor thin film on the convex portion of the irregularities. A thin film forming method is obtained.
（作用） 従来のスパッタ法あるいはバイアススパッタ法を用い
た薄膜形成方法においては、表面の凹凸の程度に応じ
て、基板に対するスパッタ粒子の飛来方向分布を変化さ
せたり、あるいは基板表面の凹凸のアスペクト比が大き
い場合に、基板に対して基板垂直方向から大きく傾いた
方向から入射するスパッタ粒子を遮断するといったこと
は、実施されていなかった。(Operation) In the conventional thin film forming method using the sputtering method or bias sputtering method, the distribution of the flying directions of sputtered particles on the substrate is changed or the aspect ratio of the unevenness of the substrate surface is changed according to the degree of the unevenness of the surface. In the case of a large value, it has not been carried out to block the sputtered particles which are incident on the substrate in a direction largely inclined from the direction perpendicular to the substrate.
本発明においては、以下のような原理で基板表面の凹
凸を密に埋め込むことができる。従来凸部の方がたくさ
んスパッタ粒子が飛来してきていたが、少なくとも基板
表面の凹凸の凹部よりスパッタターゲットを見込む領域
以外からのスパッタ粒子の進入を遮断することで、凹凸
の凸部の凹部とでターゲットから飛来するスパッタ粒子
の数が等しくなり、凹凸の凸部と凹部とで膜堆積速度と
が等しくなる。さらに、同時にバイアススパッタ条件を
調整して凹凸の凸部の肩より生じる堆積膜の基板水平方
向へのせりだしを抑制する。この２つの制限により、凹
凸の凸部の肩からの堆積膜のせりだしが無く、凸部の肩
部分の角がとれ、凹凸の凸部と凹部とで厚さがほぼ等し
い膜が堆積される。このようにすると凹凸の深さは変ら
ないけれど肩部分の角がとれているので、凹部の間口は
広がる。したがって第２の工程で表面が平坦になるよう
に膜を堆積するときシャドー効果で堆積しない領域が残
るようなことはない。このようにして、アスペクト比の
高い凹凸のある基板表面も表面平坦性よく密に薄膜を形
成することができる。In the present invention, the irregularities on the substrate surface can be densely embedded according to the following principle. Conventionally, more sputtered particles came to the convex portion, but by blocking the entry of sputtered particles from areas other than the area in which the sputter target is seen at least from the concave and convex portions of the substrate surface, the concave and convex portions of the concave and convex can be formed. The number of sputtered particles flying from the target becomes equal, and the convex and concave portions of the unevenness have the same film deposition rate. Further, at the same time, the bias sputtering condition is adjusted to suppress the protrusion of the deposited film in the horizontal direction of the substrate caused by the shoulders of the convex and concave portions. Due to these two restrictions, there is no protrusion of the deposited film from the shoulders of the convex and concave parts, the corners of the shoulder part of the convex part are removed, and a film with a thickness of the convex and concave parts of the concave and convex is approximately equal. . In this way, the depth of the unevenness does not change, but the corners of the shoulder portion are sharp, so that the frontage of the concave portion widens. Therefore, when the film is deposited so as to have a flat surface in the second step, the shadow effect does not leave an undeposited region. In this way, a thin film can be densely formed on the surface of a substrate having a high aspect ratio and unevenness with good surface flatness.
（発明の実施例） 本発明の実施例について、図面を参照して詳細に説明
する。第１図（ａ）〜（ｃ）は一実施例を工程を追って
順次示した模式的断面図である。第１図（ａ）は平坦な
表面を持つシリコン基板101上にシリコン酸化膜102をCV
D法で厚さ約１μｍ堆積した後、通常のホトレジスト工
程とドライエッチング工程を経て直径１μｍの開孔部を
形成した状態を示す。次いで第１図（ｂ）に示すよう
に、スパッタターゲットと基板との間に遮蔽板を設け、
その遮蔽板の穴を狭め、基板に対し、基板垂直方向から
大きく傾いた方向から入射するスパッタ粒子を遮断し、
基板水平面上の膜堆積速度とコンタクトホールの底面の
膜堆積速度が同程度となり、かつコンタクトホールの段
差の肩より生じる堆積膜の基板水平方向へのせりだしを
抑制するバイアススパッタ条件（アルゴンガス圧:3mTor
r、電極間距離:95mm、ターゲット側電力密度:5.7W/c
m2、バイアス電圧：−300V、ターゲット形状：円形、タ
ーゲットの大きさ：直径６インチ、遮蔽板の位置：基板
面より40mm、遮蔽板の穴の直径:40mm）でアルミニウム
膜103を0.5μｍ堆積する。その結果、段差被覆性は悪い
が、コンタクトホールの段差の肩からの堆積膜のせりだ
しが無く、段差の肩部分の角がとれ、コンタクトホール
内にも基板水平面と同程度の膜圧のアルミニウム膜が堆
積される。さらに第１図（ｃ）に示すように、コンタク
トホールの底部の導体薄膜の膜厚がコンタクトホールの
段差の高さとコンタクトホール段差上の導体薄膜の膜厚
との和にほぼ等しくなるように、遮蔽板の穴を広げ、か
つコンタクトホールの底部の導体膜の膜堆積速度が該コ
ンタクトホール段差上の導体膜の膜堆積速度よりも大き
いバイアススパッタ条件（アルゴンガス圧3mTorr、電極
間距離95mm、ターゲット側電力密度5.7W/cm2、バイアス
電圧：−600V、遮蔽板の穴の直径:90mm）でアルミニウ
ム膜104を堆積する。この結果、コンタクトホール内に
は約２μｍのアルミニウム膜が堆積し、コンタクトホー
ルの段差上の平坦面には約１μｍのアルミニウム膜が堆
積し、コンタクトホールを有するシリコン酸化膜上のア
ルミニウム膜表面は殆ど平坦になる。Embodiments of the Invention Embodiments of the present invention will be described in detail with reference to the drawings. 1 (a) to 1 (c) are schematic cross-sectional views sequentially showing one embodiment in order of steps. FIG. 1 (a) shows a CV of a silicon oxide film 102 on a silicon substrate 101 having a flat surface.
After depositing a thickness of about 1 μm by the D method, an opening having a diameter of 1 μm is formed through a normal photoresist process and a dry etching process. Next, as shown in FIG. 1 (b), a shield plate is provided between the sputter target and the substrate,
Narrowing the hole of the shield plate, to block the sputtered particles that enter the substrate from a direction that is greatly inclined from the direction perpendicular to the substrate,
The film deposition rate on the horizontal surface of the substrate is almost the same as the film deposition rate on the bottom surface of the contact hole, and the bias sputtering condition (Argon gas pressure) is used to suppress the protrusion of the deposited film in the horizontal direction of the substrate caused by the shoulder of the step of the contact hole. : 3mTor
r, distance between electrodes: 95 mm, target side power density: 5.7 W / c
m 2, the bias voltage: -300 V, the target shape: circular, target size: 6 inch diameter, the position of the shield plate: from the substrate surface 40 mm, the hole of the shield plate diameter: 40 mm) 0.5 [mu] m deposited aluminum film 103 in To do. As a result, the step coverage is poor, but there is no protrusion of the deposited film from the shoulder of the step of the contact hole, the corners of the shoulder of the step are removed, and the aluminum of the film pressure in the contact hole is similar to that of the horizontal surface of the substrate. The film is deposited. Further, as shown in FIG. 1C, the thickness of the conductor thin film at the bottom of the contact hole is approximately equal to the sum of the height of the step of the contact hole and the thickness of the conductor thin film on the step of the contact hole. Bias sputtering conditions (argon gas pressure 3 mTorr, interelectrode distance 95 mm, target) where the hole of the shield plate is widened and the film deposition rate of the conductor film at the bottom of the contact hole is higher than the film deposition rate of the conductor film on the step of the contact hole. An aluminum film 104 is deposited with a side power density of 5.7 W / cm 2 , bias voltage of −600 V, and hole diameter of the shielding plate: 90 mm. As a result, an aluminum film of about 2 μm is deposited in the contact hole, an aluminum film of about 1 μm is deposited on the flat surface on the step of the contact hole, and the aluminum film surface on the silicon oxide film having the contact hole is almost It becomes flat.
前記実施例においてはアルミニウム膜を堆積したが何
もこれに限る必要はなく、モリブデン等の他の金属、不
純物をドープした多結晶シリコン、シリサイド等の合金
も用いることができる。Although an aluminum film is deposited in the above-mentioned embodiment, the present invention is not limited to this, and other metals such as molybdenum, polycrystalline silicon doped with impurities, and alloys such as silicide can be used.
前記実施例においては穴が１つの遮蔽板を用いたが、
複数の穴をもつ遮蔽板を用いてもよい。複数の穴によっ
て基板への堆積膜の膜均一性は向上する。Although the shield plate having one hole is used in the above embodiment,
A shield plate having a plurality of holes may be used. The plurality of holes improves the film uniformity of the deposited film on the substrate.
（発明の効果） 以上説明したごとく、本発明によれば急峻な側面を持
ち高アスペクト比で微細なコンタクトホールにおいて
も、シャドー効果を生じることなく堆積導体膜を表面平
坦性良く堆積できる。その結果、２〜３層の多層配線構
造において配線の段切れや接触不良等を回避でき、それ
をLSIに使用した場合、信頼性、歩留りを飛躍的に向上
することができる。(Effects of the Invention) As described above, according to the present invention, even in a fine contact hole having a steep side surface and a high aspect ratio, a deposited conductor film can be deposited with good surface flatness without causing a shadow effect. As a result, it is possible to avoid disconnection of wiring, contact failure, etc. in a multilayer wiring structure of 2 to 3 layers, and when it is used in an LSI, reliability and yield can be dramatically improved.
第１図（ａ）〜（ｃ）は本発明の方法の一実施例を説明
するための模式的断面図、第２図は従来の平行平板型の
スパッタ法による膜堆積の一実施例を示した模式的断面
図である。 101……シリコン基板、102……シリコン酸化膜 103,104……アルミニウム膜、201……堆積導体膜1 (a) to 1 (c) are schematic sectional views for explaining one embodiment of the method of the present invention, and FIG. 2 shows one embodiment of film deposition by a conventional parallel plate type sputtering method. It is a typical sectional view. 101: Silicon substrate, 102: Silicon oxide film 103, 104: Aluminum film, 201: Deposited conductor film
Claims (1)
ッタターゲットを見込む領域以外からのスパッタ粒子の
進入を遮断し、穴を有する遮蔽板をスパッタターゲット
と基板との間に設け、該遮蔽板の穴を狭めて、基板表面
の凹凸の凸部の肩より生じる堆積膜の基板水平方向への
せりだしを抑制するバイアススパッタ条件で導体膜を堆
積する第一の工程と、該遮蔽板の穴を広げてスパッタ粒
子の飛来方向分布を広げ、該凹凸の凹部の導体膜の膜堆
積速度が該凹凸の凸部の導体膜の膜堆積速度よりも大き
いバイアススパッタ条件で導体薄膜を堆積し、該凹凸の
凹部の導体薄膜の膜厚を該凹凸の凸部の高さと該凹凸の
凸部上の導体薄膜の膜厚との和にほぼ等しくする第二の
工程を含むことを特徴とする薄膜形成方法。1. A shield plate having a hole is provided between the sputter target and the substrate to block intrusion of sputtered particles from a region other than the region where the sputter target is seen through at least the concave and convex portions of the substrate surface, and the hole of the shield plate is provided. The first step of depositing a conductor film under bias sputtering conditions that suppresses the protrusion of the deposited film in the horizontal direction of the substrate, which is caused by the shoulders of the protrusions of the unevenness on the substrate surface, and widens the hole of the shielding plate. The spread direction of the sputtered particles is widened, and the conductor thin film is deposited under bias sputtering conditions in which the film deposition rate of the conductor film in the concave portion of the unevenness is higher than the film deposition rate of the conductive film in the convex portion of the unevenness. A method of forming a thin film, comprising a second step of making the thickness of the conductor thin film in the recess substantially equal to the sum of the height of the protrusion of the unevenness and the thickness of the conductor thin film on the protrusion of the unevenness.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61040347A JPH084088B2 (en) | 1986-02-27 | 1986-02-27 | Thin film formation method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61040347A JPH084088B2 (en) | 1986-02-27 | 1986-02-27 | Thin film formation method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62199033A JPS62199033A (en) | 1987-09-02 |
| JPH084088B2 true JPH084088B2 (en) | 1996-01-17 |
Family
ID=12578099
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61040347A Expired - Lifetime JPH084088B2 (en) | 1986-02-27 | 1986-02-27 | Thin film formation method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH084088B2 (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CA2061119C (en) * | 1991-04-19 | 1998-02-03 | Pei-Ing P. Lee | Method of depositing conductors in high aspect ratio apertures |
| JP2725944B2 (en) * | 1991-04-19 | 1998-03-11 | インターナショナル・ビジネス・マシーンズ・コーポレイション | Metal layer deposition method |
| US5885425A (en) * | 1995-06-06 | 1999-03-23 | International Business Machines Corporation | Method for selective material deposition on one side of raised or recessed features |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6052043A (en) * | 1983-09-01 | 1985-03-23 | Nec Corp | Manufacture of wiring structure |
-
1986
- 1986-02-27 JP JP61040347A patent/JPH084088B2/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62199033A (en) | 1987-09-02 |
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