JPH088345B2 - Light receiving element with built-in circuit - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a structure for increasing the photosensitivity of a light receiving element having a signal processing circuit incorporated therein and increasing the response speed.

(Prior Art) A light receiving element with a built-in circuit is widely used for an optical sensor, a photocoupler, and the like. FIG. 5 is a schematic sectional view showing the structure of an example of a conventional general photodetector with a built-in circuit. In the figure, a photodiode A is formed as a light receiving element on the left side of the surface of one P-type semiconductor substrate 1, and an NPN transistor B is formed as a signal processing circuit element on the right side. This is produced as follows. First, the N type buried diffusion layers 2, 2− are formed in the predetermined regions of each element on the surface of one P type semiconductor substrate 1.
1 and the N-type epitaxial layer 4 is formed on them. Next, a P-type separation diffusion layer for separating each element
.. are formed, and a P-type diffusion layer 6 for anode is formed in the portion of the photodiode A, and a P-type diffusion layer 6-1 for base is formed in the portion of the NPN transistor B. Next, the N-type diffusion layer 7 for emitter is formed on a part of the P-type diffusion layer 6-1 of the NPN transistor B. Further, from the surface of the N-type epitaxial layer 4, the cathode N-type compensation diffusion layer 5 reaching the N-type buried diffusion layer 2 in the photodiode A portion and the N-type buried diffusion layer 2-1 in the NPN transistor B portion are reached. An N-type compensation diffusion layer 5-1 for collector is formed.
Therefore, in this structure, the photodiode A part is also NPN.
Similarly, the portion of the transistor B is also formed in the N-type epitaxial layer 4 having the same thickness and the same specific resistance.

(Problems to be Solved by the Invention) Due to recent demands for speeding up data transmission, improving S / N ratio, etc., it is desired to improve the photosensitivity of a photodetector with a built-in circuit and speed up the response speed. For that purpose, it is not appropriate to form both the light receiving element and the signal processing circuit element in the N type epitaxial layer having the same thickness and the same specific resistance as shown in FIG. In order to increase the photosensitivity of the light receiving element, it is necessary to make the thickness of the N-type epitaxial layer 4 in the photodiode A portion sufficiently thick according to the wavelength of the light used for the input signal. However, the N-type epitaxial layer 4
If the thickness is made too thick, the time for the generated photocarriers to travel through the remaining non-depleted layer in this layer becomes long, which hinders the response speed from increasing. Further, if the thickness of the N-type epitaxial layer 4 in the portion of the NPN transistor B is increased, the collector resistance of the NPN transistor B is increased, which is an obstacle to speeding up the response speed of the signal processing circuit.

On the other hand, in order to increase the response speed of the light receiving element, it is effective to reduce the junction capacitance of the photodiode A portion, and for that purpose, it is necessary to increase the specific resistance of the N-type epitaxial layer 4. However, when the specific resistance of the N-type epitaxial layer 4 in the portion of the NPN transistor B becomes high, the collector resistance of the NPN transistor B increases, which has the opposite effect to the speeding up of the response speed of the signal processing circuit.

From the above, in order to achieve both high photosensitivity and high response speed of the light receiving element with a built-in circuit, the N-type epitaxial layer 4 of the photodiode A has a high specific resistance and a large thickness, and the NPN transistor B has a high resistivity. It is desirable that the N-type epitaxial layer 4 has a low specific resistance and is thin. However, in the conventional structure, it is difficult to satisfy the contradictory conditions described above.

(Means for Solving the Problems) In the present invention, in order to solve the above-mentioned problems, the photodiode portion has an N-type high resistivity epitaxial layer on an N-type buried diffusion layer buried in a P-type semiconductor substrate. P type anode for reaching a lower N type high resistivity epitaxial layer from a part of the surface of the N type low resistivity epitaxial layer A diffusion layer is provided, and the NPN transistor part is P
The P-type buried diffusion layer in the thick N-type high resistivity epitaxial layer formed on the P-type buried diffusion layer buried in the N-type semiconductor substrate to compensate for P-type An N-type low resistivity epitaxial layer was thinly laminated via a type buried diffusion layer, and a base and an emitter diffusion layer were provided on this N-type low resistivity epitaxial layer.

(Operation) By adopting the structure as described above, the N-type epitaxial layer of the photodiode portion is effectively the thick N-type high resistivity epitaxial layer of the lower portion, and the epitaxial layer of the NPN transistor portion is effectively the upper portion. Since it is a thin N-type low resistance epitaxial layer, the above-mentioned contradictory conditions can be satisfied.

(Embodiment) FIG. 1 is a schematic cross-sectional view showing the structure of an embodiment of the present invention, and FIGS. 2 to 4 are schematic cross-sectional views of respective steps until the structure of FIG. 1 is obtained. .

First, as shown in FIG. 2, a first N-type buried diffusion layer 2 is provided in a predetermined region of a photodiode as a light-receiving element on the surface of a P-type semiconductor substrate 1, and an NP as a signal processing circuit element is provided.
A P-type buried diffusion layer 8 is formed in a predetermined area of the N transistor or the like.

Next, as shown in FIG. 3, for example, 100
The N-type high resistivity epitaxial layer 9 of about Ωcm is grown thick. After that, the second N-type buried diffusion layer 10 is formed on the surface of the planned region of the NPN transistor. During these steps, the first N-type buried diffusion layer 2 and the P-type buried diffusion layer 8 are vertically diffused. The N-type high resistivity epitaxial layer 9 is represented by i in the sense that it is close to an intrinsic semiconductor.

Furthermore, as shown in FIG.
An N type low resistivity epitaxial layer 11 of about 1 Ωcm is grown. Next, P-type isolation diffusion layers 3, 3, ... Are formed at the boundaries of the planned regions of the respective elements. At the same time as the formation of the P-type isolation diffusion layers 3, 3, ..., The anode P-type diffusion layer 3 reaching the surface of the N-type high specific resistance epitaxial layer 9 from the surface of the N-type low specific resistance epitaxial layer 11 in the photodiode planned region. -1 is formed. During these steps, the first N-type buried diffusion layer 2 and the P-type buried diffusion layer 8 and the second N-type buried diffusion layer 10 are formed.
Respectively diffuse up and down.

After this, as shown in FIG.
A cathode type compensation diffusion layer 5 reaching the first N-type buried diffusion layer 2 from the surface of the portion and a collector compensation diffusion layer 12 reaching the second N-type buried diffusion layer 10 from the surface of the NPN transistor B portion. Then, the base diffusion layer 6-1 is formed on a part of the surface of the N-type low resistivity epitaxial layer 11, and the emitter diffusion layer 7 is formed on a part thereof. Due to the heat treatment during these steps,
The N-type buried diffusion layer 2, the P-type buried diffusion layer 8, and the second N-type buried diffusion layer 10 are further diffused vertically, respectively, and the P-type separation diffusion layer 3 and the anode P-type diffusion layer are diffused. 3-1 diffuses downward and reaches the first N-type high resistivity epitaxial layer 9. In the portion of the NPN transistor B, the P-type isolation diffusion layer 3 reaches the P-type buried diffusion layer 8 diffused upward. Therefore, the elements are separated by the P-type isolation diffusion layer 3 and the P-type buried diffusion layer 8. The N-type high resistivity epitaxial layer 9 is completely compensated by the diffusion of the P-type buried diffusion layer 8 to become P-type. In this way, the light receiving element with a built-in circuit having the configuration of FIG. 1 is obtained.

In the structure of FIG. 1, the width of the element isolation region of the signal processing circuit portion is determined by the P-type isolation diffusion layer 3. This P
Since the depth of the type separation diffusion layer 3 may be almost the same as the thickness of the thin low-resistivity epitaxial layer 11, the lateral expansion of the P type separation diffusion layer 3 is reduced, and the signal processing circuit element such as the NPN transistor is reduced. The size of the active island region is suppressed small. Therefore, the parasitic capacitance of the signal processing circuit element such as the NPN transistor is suppressed small, and high-speed circuit operation can be realized.

In FIG. 1, the P-type buried diffusion layer 8 is provided over the entire area below the NPN transistor B, but it may be formed just below the P-type isolation diffusion layer 3. In this case, the N-type high-resistivity epitaxial layer 9 remains in a portion other than directly below the P-type isolation diffusion layer 3, but this may be left as it is or may be compensated by the N-type buried diffusion layer. it can.

The N-type compensation diffusion layer 5 for the cathode of the photodiode A section is the collector compensation diffusion layer 12 of the NPN transistor B.
It is also possible to diffuse in the same manner as above, and to provide an N-type buried diffusion layer in advance in a part of the N-type high-resistivity epitaxial layer 9 corresponding to the lower side so as to connect both.

Similarly to the P-type isolation diffusion layer 3, a P-type buried diffusion layer is provided in advance in a part of the N-type high specific resistance epitaxial layer 9 corresponding thereto, and the N-type low specific resistance epitaxial layer 11 is formed.
It can also be formed by diffusion from above and below.

Although the case of using the P-type semiconductor substrate has been described above, the present invention can be applied to the case of using the N-type substrate and appropriately changing the configuration of the diffusion layer.

(Effects of the Invention) According to the present invention, since the PN junction other than the side surface of the anode P-type diffusion layer 3-1 is formed in the N-type high / low resistivity epitaxial layer 9 in the photodiode A portion, the junction is formed. The capacity can be significantly reduced. Further, since the thickness of the high-low specific resistance N-type epitaxial layer can be increased without adversely affecting the signal processing circuit section, the photosensitivity can be improved. Further, the specific resistance and thickness of the high-low specific resistance N-type epitaxial layer are set so that the depletion layer reaches the first N-type buried diffusion layer 2 under the bias voltage in the actual use state. In this case, the generated photocarriers do not travel due to diffusion, have a so-called pin structure, and a photodiode having a good photoelectric conversion efficiency and a high reaction speed can be obtained.

Further, the transistor portion effectively has a thin film epitaxial layer having a low specific resistance, and a high-speed transistor having a low collector resistance can be formed.

By forming such a photodiode and a transistor on the same substrate, it is possible to obtain a light receiving element with a built-in circuit which is excellent in light sensitivity and response speed.

[Brief description of drawings]

FIG. 1 is a schematic sectional view showing the structure of an embodiment of the present invention, and FIG.
FIG. 3, FIG. 3 and FIG. 4 are schematic cross-sectional views of respective steps until the structure of FIG. 1 is obtained, and FIG. 5 is a schematic cross-sectional view of an example of the conventional structure. 1 ... P-type semiconductor substrate, 2 ... N-type buried diffusion layer, 3 ...
P-type isolation diffusion layer, 5 ... N-type compensation diffusion layer, 6 ... Anode P-type diffusion layer, 6-1 ... Base diffusion layer, 7 ... Emitter diffusion layer, 8 ... P-type buried diffusion layer , 9 ... N-type high resistivity epitaxial layer, 11 ... N-type low resistivity epitaxial layer, 12 ... Collector compensation diffusion layer.

Claims (1)

[Claims] 1. An N-type thin high-resistivity epitaxial layer formed on a P-type substrate and an N-type thin low-resistivity epitaxial layer laminated thereon, wherein the N-type thin low-resistivity epitaxial layer is formed. A light receiving element including an anode that penetrates through the specific resistance epitaxial layer to reach the N type thick high specific resistance epitaxial layer and a light receiving element including the N type thick high specific resistance epitaxial layer, and compensates the N type thick high specific resistance epitaxial layer A signal processing circuit element is formed by forming a diffusion layer on the N-type thin low-resistivity epitaxial layer on the surface of the P-type layer thus formed, and both elements are formed by the N-type thick high-resistivity epitaxial layer. A P-type layer formed by compensating layers, and a P-type separation diffusion layer formed at the same time as the formation of the anode reaching the P-type layer formed by compensation from the surface of the boundary between elements Specially separated in And the circuit built-in light-receiving element.