Deprecated: The each() function is deprecated. This message will be suppressed on further calls in /home/zhenxiangba/zhenxiangba.com/public_html/phproxy-improved-master/index.php on line 456
US7049692B2 - Stacked semiconductor device - Google Patents
[go: Go Back, main page]

US7049692B2 - Stacked semiconductor device - Google Patents

Stacked semiconductor device Download PDF

Info

Publication number
US7049692B2
US7049692B2 US10/763,267 US76326704A US7049692B2 US 7049692 B2 US7049692 B2 US 7049692B2 US 76326704 A US76326704 A US 76326704A US 7049692 B2 US7049692 B2 US 7049692B2
Authority
US
United States
Prior art keywords
semiconductor device
wiring substrate
device unit
conductive member
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime, expires
Application number
US10/763,267
Other languages
English (en)
Other versions
US20040178508A1 (en
Inventor
Takao Nishimura
Kazuyuki Aiba
Akira Takashima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Socionext Inc
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Assigned to FUJITSU LIMITED reassignment FUJITSU LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: AIBA, KAZUYUKI, NISHIMURA, TAKAO, TAKASHIMA, AKIRA
Publication of US20040178508A1 publication Critical patent/US20040178508A1/en
Application granted granted Critical
Publication of US7049692B2 publication Critical patent/US7049692B2/en
Assigned to FUJITSU MICROELECTRONICS LIMITED reassignment FUJITSU MICROELECTRONICS LIMITED ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU LIMITED
Assigned to FUJITSU SEMICONDUCTOR LIMITED reassignment FUJITSU SEMICONDUCTOR LIMITED CHANGE OF NAME (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU MICROELECTRONICS LIMITED
Assigned to SOCIONEXT INC. reassignment SOCIONEXT INC. ASSIGNMENT OF ASSIGNORS INTEREST (SEE DOCUMENT FOR DETAILS). Assignors: FUJITSU SEMICONDUCTOR LIMITED
Adjusted expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/141—One or more single auxiliary printed circuits mounted on a main printed circuit, e.g. modules, adapters
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/114—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations
    • H10W74/117—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed by a substrate and the encapsulations the substrate having spherical bumps for external connection
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0213—Electrical arrangements not otherwise provided for
    • H05K1/0216—Reduction of cross-talk, noise or electromagnetic interference
    • H05K1/023—Reduction of cross-talk, noise or electromagnetic interference using auxiliary mounted passive components or auxiliary substances
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/144—Stacked arrangements of planar printed circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/14—Structural association of two or more printed circuits
    • H05K1/145—Arrangements wherein electric components are disposed between and simultaneously connected to two planar printed circuit boards, e.g. Cordwood modules
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistors, capacitors or inductors
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/045—Hierarchy auxiliary PCB, i.e. more than two levels of hierarchy for daughter PCBs are important
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/04—Assemblies of printed circuits
    • H05K2201/049—PCB for one component, e.g. for mounting onto mother PCB
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10431—Details of mounted components
    • H05K2201/10507—Involving several components
    • H05K2201/10515—Stacked components
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613—Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621—Components characterised by their electrical contacts
    • H05K2201/10734—Ball grid array [BGA]; Bump grid array
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistors
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistors electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341—Surface mounted components
    • H05K3/3431—Leadless components
    • H05K3/3436—Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/22—Configurations of stacked chips the stacked chips being on both top and bottom sides of a package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/271—Configurations of stacked chips the chips having passive surfaces facing each other, i.e. in a back-to-back arrangement
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/28—Configurations of stacked chips the stacked chips having different sizes, e.g. chip stacks having a pyramidal shape
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/291—Configurations of stacked chips characterised by containers, encapsulations, or other housings for the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/20—Configurations of stacked chips
    • H10W90/297—Configurations of stacked chips characterised by the through-semiconductor vias [TSVs] in the stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/732—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between stacked chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the present invention generally relates to a stacked semiconductor device, and especially relates to a stacked semiconductor device having a three-dimensional structure wherein two or more semiconductor device units and semiconductor devices are stacked.
  • semiconductor devices used therein are increasingly required to be small in size, thin, capable of providing multiple functions and advanced features, and highly condensed.
  • the packaging structure of semiconductor devices is shifting to a three-dimensional structure wherein two or more semiconductor device units or two or more semiconductor devices are stacked.
  • a semiconductor device unit means a semiconductor device as it is, and a structure containing a semiconductor device in a package.
  • the patent reference 1 discloses a QFP (quad flat package) that employs a leadframe as an external terminal.
  • a QFP type semiconductor device provides a terminal on the upper part of the package by forming a convex section by deforming an inner lead section of the leadframe, on which package a stacking wiring substrate having terminals on both upper and bottom surfaces of the package is connected by a solder bump.
  • a semiconductor device wherein a plurality of molding-sealed semiconductor units are stacked.
  • penetration wiring is provided on the semiconductor device at the molding-seal section of the semiconductor device units such that a terminal is provided at the upper part of the package, at which upper part of the package a re-wiring substrate having a terminal on both upper and bottom surfaces is connected by a solder ball.
  • problems are that no more than one semiconductor device unit can be stacked beneath (i.e., two in total), and that a terminal has to be prepared at the upper part of the package by deforming a leadframe, requiring considerable manufacturing processes, with manufacturing cost becoming high.
  • An aspect of the present invention is to provide a stacked semiconductor device that includes:
  • a first semiconductor device unit that has a first wiring substrate, at least one semiconductor device being mounted on the first wiring substrate, and an external connection terminal,
  • a second semiconductor device unit that has a second wiring substrate installed below the first semiconductor device unit, at least one semiconductor device being mounted on the second wiring substrate, and a connection electrode being formed on a surface of the second wiring substrate, the surface facing the first semiconductor device unit, and
  • a third wiring substrate that includes a circuit board arranged between the first semiconductor device unit and the second semiconductor device unit, a first conductive member that is electrically connected to the above-mentioned connection electrode, a second conductive member that is formed corresponding to the form position of the above-mentioned external connection terminal, and electrically connected to the external connection terminal, and a third conductive member that connects the first conductive member and the second conductive member.
  • Another aspect of the present invention is to provide a stacked semiconductor device wherein the first conductive member is constituted by a solder bump that is formed by penetrating the circuit board, and connected to the third conductive member.
  • Another aspect of the present invention is to provide a stacked semiconductor device wherein:
  • the first conductive member is constituted by the solder bump as described above,
  • the second conductive member and the third conductive member are formed on a surface of the third wiring substrate, the surface facing the above second wiring substrate, and
  • a through hole is formed in the third wiring substrate for electrically connecting the external connection terminal with the second conductive member.
  • another aspect of the present invention is to provide a stacked semiconductor device wherein the second conductive member and the third conductive member are formed on both surfaces of the third wiring substrate, one of the surfaces facing the first semiconductor device unit, and the other surface facing the second semiconductor device unit, wherein the third conductive member formed on both surfaces is electrically connected by the through-hole electrodes formed by penetrating the circuit board.
  • another aspect of the present invention is to provide a stacked semiconductor device wherein the first semiconductor unit includes two or more semiconductor device units that are stacked.
  • another aspect of the present invention is to provide a stacked semiconductor device wherein the second semiconductor device unit includes two or more semiconductor device units that are stacked.
  • another aspect of the present invention is to provide a stacked semiconductor device wherein the third wiring substrate is a multilayered substrate.
  • another aspect of the present invention is to provide a stacked semiconductor device wherein a passive component is provided on the third wiring substrate.
  • another aspect of the present invention is to provide a stacked semiconductor device wherein a multilayered substrate is used as the third wiring substrate, and a passive component is prepared in the multilayered substrate.
  • the present invention provides a stacked semiconductor device that substantially obviates one or more of the problems caused by the limitations and disadvantages of the related art.
  • FIG. 1 is a cross-sectional view of a semiconductor device according to a first embodiment of the present invention
  • FIG. 2 is a cross-sectional view of the semiconductor device according to a second embodiment of the present invention.
  • FIG. 3 is a cross-sectional view of the semiconductor device according to a third embodiment of the present invention.
  • FIG. 4 is a cross-sectional view of the semiconductor device according to a fourth embodiment of the present invention.
  • FIG. 5 is a cross-sectional view of the semiconductor device according to a fifth embodiment of the present invention.
  • FIG. 6 is a cross-sectional view of the semiconductor device according to a sixth embodiment of the present invention.
  • FIG. 7 is a cross-sectional view of the semiconductor device according to a seventh embodiment of the present invention.
  • FIG. 1 shows a stacked semiconductor device (henceforth referred to as “semiconductor device”) 10 A according to the first embodiment of the present invention.
  • the semiconductor device 10 A includes an upper semiconductor device unit 11 A (henceforth called “upper device unit”), a lower semiconductor device unit 12 A (henceforth called “lower device unit”), and an interposer substrate 13 A.
  • the upper device unit 11 A is a general-purpose semiconductor device that is commercially available. That is, a commercial product that is guaranteed by a manufacturer is used as the upper device unit 11 A.
  • the device unit 11 A is a BGA (Ball Grid Array) type semiconductor device wherein a semiconductor element 14 A is mounted on the upper surface of a first wiring substrate 16 A, and external connection terminals 22 are arranged on the undersurface of the first wiring substrate 16 A.
  • a solder ball constitutes each of the external connection terminals 22 .
  • the semiconductor element 14 A is fixed with its face up on the first wiring substrate 16 A. Further, electrode pads 20 are formed on the first wiring substrate 16 A, and the semiconductor element 14 A is connected to the electrode pads 20 by wires 21 .
  • the external connection terminals 22 are connected to the electrode pads 20 by through holes formed in the first wiring substrate 16 A. Therefore, the semiconductor element 14 A is electrically connected to the external connection terminals 22 through the wires 21 and the electrode pads 20 . Further, a sealing resin 23 is formed covering the whole upper surface of the first wiring substrate 16 A such that the semiconductor element 14 A, the wires 21 , and others are protected.
  • the lower device unit 12 A includes a semiconductor element 15 A, a second wiring substrate 17 A, and external connection terminals 29 .
  • the semiconductor element 15 A is mounted on the second wiring substrate 17 A by flip chip bonding. That is, bumps 25 are beforehand formed in an electrode section (not shown) of the circuit surface of the semiconductor element 15 A, and the semiconductor element 15 A is electrically connected to the second wiring substrate 17 A by connecting the bumps 25 to bump connecting electrodes 27 formed on an upper surface 24 A of the second wiring substrate 17 A. Further, in order to strengthen the connections between the bumps 25 and the bump connecting electrodes 27 , an underfill resin 30 is arranged between the semiconductor element 15 A and the second wiring substrate 17 A.
  • the second wiring substrate 17 A is located below the upper device unit 11 A. That is, the lower device unit 12 A is arranged below the upper device unit 11 A.
  • the external connection terminals 29 are the terminals that are connected to an external substrate when the semiconductor device 10 A is mounted on the external substrate. Further, the lower electrodes 28 to which the external connection terminals 29 are connected are also connected to the connection electrodes 26 , or, as applicable, to the bump connecting electrodes 27 by an inner layer wiring (not shown) prepared inside the second wiring substrate 17 A.
  • the interposer substrate 13 A includes first conductive members 32 , as described below, which are connected to the connection electrodes 26 that are formed on the upper surface 24 A of the second wiring substrate 17 A. Further, the connection electrodes 26 are prepared at positions where the semiconductor element 15 A is not mounted.
  • the interposer substrate 13 A includes a circuit board 18 A, the first conductive members 32 , second conductive members 33 , and third conductive members 34 A.
  • the circuit board 18 A is arranged between the upper device unit 11 A and the lower device unit 12 A.
  • the interposer substrate 13 A is arranged between the upper device unit 11 A and the lower device unit 12 A.
  • the circuit board 18 A is a single surface wiring substrate made of epoxy/glass or BT (Bismaleimide Triazine)/glass, on an upper surface 31 A of which the second conductive members 33 serving as electrodes, and the third conductive members 34 A serving as a wiring section, are formed.
  • the first conductive members 32 are constituted by solder bumps, and are connected to the third conductive members 34 A via through holes prepared in the interposer substrate 13 A.
  • the first conductive members 32 electrically connect the lower device unit 12 A to the interposer substrate 13 A.
  • the lower device unit 12 A and the interposer substrate 13 A are electrically connected by the first conductive members 32 that are constituted by the solder bumps, which are easy and economical to prepare. Further, a process for stacking the lower device unit 12 A and the interposer substrate 13 A becomes simple and economical.
  • the second conductive members 33 and the third conductive members 34 A being structured as printed circuits made of copper, are formed on the upper surface 31 A of the circuit board 18 A. Further, the second conductive members 33 and the third conductive members 34 A are protected by a protective coat 35 A formed on the upper surface 31 A of the circuit board 18 A. Openings 44 are formed in the protective coat 35 A at positions corresponding to the external connection terminals 22 of the upper device unit 11 A.
  • the second conductive members 33 are connected to the external connection terminals 22 of the upper device unit 11 A.
  • the third conductive members 34 A electrically connect the first conductive members 32 and the second conductive members 33 .
  • the external connection terminals 22 of the upper device unit 11 A and the connection electrodes 26 of the lower device unit 12 A are electrically connected by the first conductive members 32 , the second conductive members 33 , and the third conductive members 34 A.
  • the upper device unit 11 A and the lower device unit 12 A stacked with the interposer substrate 13 A in the middle constitute the semiconductor device 10 A, wherein the interposer substrate 13 A functions as an interposer for electrically connecting the upper device unit 11 A and the lower device unit 12 A.
  • the second conductive members 33 are formed corresponding to the form positions of the external connection terminals 22 of the upper device unit 11 A, and there are no other restrictions as to the form positions of the second conductive members 33 . That is, the second conductive members 33 can be arranged on the upper surface 31 A of the circuit board 18 A according to the arrangement of the external connection terminals 22 . For this reason, a general-purpose semiconductor device, wherein the arrangement of the external connection terminals 22 is beforehand defined can be used as the upper device unit 11 A.
  • the yield of an end product such as the semiconductor device 10 A, constituted by multiple semiconductor device units (semiconductor device) is an accumulation of the yields of the multiple semiconductor devices, such as the upper device unit 11 A and the lower device unit 12 A, when the yield is determined after assembling the multiple semiconductor devices.
  • the semiconductor device 10 A according to the present embodiment uses a general-purpose semiconductor device, the quality of which is guaranteed, as the semiconductor device unit 11 A, the manufacturing yield of the whole semiconductor device 10 A is improved.
  • the semiconductor device 10 A of the present embodiment since the second conductive members 33 are formed corresponding to the upper device unit 11 A, the design flexibility is enhanced. Furthermore, the design flexibility of the third conductive members 34 A formed on the upper surface 31 A of the circuit board 18 A is also enhanced. In this manner, the wiring structure, which can otherwise become complicated due to stacking, becomes simple, facilitating design of the semiconductor device 10 A, and the semiconductor device 10 A that is capable of offering advanced features and multiple functions is realized.
  • FIG. 2 shows a semiconductor device 10 B according to the second embodiment of the present invention.
  • FIG. 2 that is for explaining the second embodiment
  • FIGS. 3 through 7 that are for explaining subsequent embodiments
  • the same label is used for the same component as shown in FIG. 1 , and explanation thereof is not repeated.
  • the semiconductor device 10 B of the present embodiment includes the upper device unit 11 A and the lower device unit 12 A, which are the same as in the semiconductor device 10 A of the first embodiment.
  • the semiconductor device 10 B of the present embodiment includes an interposer substrate 13 B that is different from the interposer substrate 13 A of the first embodiment.
  • both second conductive members 33 and third conductive members 34 A are formed on the upper surface 31 A of the circuit board 18 A.
  • the second conductive members 33 and third conductive members 34 B are formed on an undersurface 31 B of a circuit board 18 B.
  • the undersurface 31 B of the circuit board 18 B is the surface that faces the lower device unit 12 A. That is, the structure of the semiconductor device 10 B of the present embodiment is such that the second conductive members 33 and the third conductive members 34 are formed on the surface of the circuit board 18 B that faces the lower device unit 12 A, namely the undersurface 31 B.
  • the second conductive members 33 and the third conductive members 34 B formed on the undersurface 31 B of the circuit board 18 B are protected by a protective coat 35 B formed on the undersurface 31 B of the circuit board 18 B.
  • openings 44 B are formed in the protective coat 35 B at positions corresponding to the connection electrodes 26 of the lower device unit 12 A. The first conductive members 32 and the third conductive members 34 B are connected through the openings 44 B.
  • the external connection terminals 22 of the upper device unit 11 A are connected to the second conductive members 33 of the interposer substrate 13 B via through holes 36 formed in the circuit board 18 B corresponding to the form positions of the external connection terminals 22 of the upper device unit 11 A. In this manner, the external connection terminals 22 are electrically connected to the second conductive members 33 via the through holes 36 .
  • the external connection terminals 22 are constituted by solder balls as described above, the external connection terminals 22 are fused by heat-treatment carried out when mounting the upper device unit 11 A on the interposer substrate 13 B, and flow into respective through holes 36 . In this manner, the external connection terminals 22 and the second conductive member 33 s are electrically connected via the through holes 36 .
  • each of the external connection terminals 22 of the semiconductor device 10 B of the present embodiment is melted and fills the corresponding through hole 36 formed on the circuit board 18 B. That is, the distance between the upper device unit 11 A and the interposer substrate 13 B becomes smaller by the height corresponding to the amount of the external connection terminals 22 that melts and fills the respective through holes 36 .
  • a distance H 1 between the upper device unit 11 A and the interposer substrate 13 A of the semiconductor device 10 A according to the first embodiment as shown in a FIG. 1 is made smaller in the case of the semiconductor device 10 B of the present embodiment as indicated by arrows associated to a distance H 2 shown in FIG. 2 .
  • the distance H 2 between the upper device unit 11 A and the interposer substrate 13 B is less than the distance H 1 by the amount that the external connection terminals 22 melt and flow into the corresponding through holes 36 .
  • the semiconductor device 10 B of the present embodiment can be made thinner compared with the semiconductor device 10 A of the first embodiment.
  • FIG. 3 shows a semiconductor device 10 C according to the third embodiment of the present invention.
  • the semiconductor device 10 C includes the upper device unit 11 A and the lower device unit 12 A, which are the same as in the semiconductor device 10 A of the first embodiment.
  • an interposer substrate 13 C of the semiconductor device 10 C is different from the first and the second embodiments.
  • the third conductive members 34 A and 34 B are provided on the upper surface 31 A and the undersurface 31 B, respectively, of the circuit board 18 A and 18 B, respectively, i.e., only on one of the surfaces.
  • the third conductive members 34 A and 34 B are provided on upper surface 31 A and undersurface 31 B, respectively.
  • the third conductive members 34 A and the second conductive members 33 that are bonded to the external connection terminals 22 are provided on the upper surface 31 A of the circuit board 18 C, and the third conductive members 34 B are formed on the undersurface 31 B of the circuit board 18 C.
  • the protective coats 35 A and 35 B are formed on the third conductive members 34 A and 34 B, respectively.
  • the openings 44 A are formed in the protective coat 35 A at positions corresponding to the external connection terminals 22 of the upper device unit 11 A, and the openings 44 B are formed in the protective coat 35 B at positions corresponding to the connection electrodes 26 of the lower device unit 12 A.
  • through-hole electrodes 37 penetrating the circuit board 18 C are formed, which electrically connect the third conductive members 34 A formed on the upper surface 31 A of the circuit board 18 C and the third conductive members 34 B formed on the undersurface 31 B.
  • the through-hole electrodes 37 are formed by through holes in the circuit board 18 C, the through holes being filled with copper, and constituting vias.
  • the third conductive members 34 A and 34 B are formed on both surfaces of the circuit board 18 C of the interposer substrate 13 C according to the semiconductor device 10 C of the present embodiment, a complicated circuit pattern can be accommodated, enhancing design flexibility, compared with a configuration wherein the third conductive members 34 A or 34 B, as applicable, are provided only on one of the surfaces. Further, the third conductive members 34 A and 34 B function as reinforcing materials, and the rigidity of the interposer substrate 13 C is increased, suppressing curvature and deformation of the substrate due to temperature change. Accordingly, the manufacturing yield is raised, and the reliability of the semiconductor device 10 C is improved.
  • FIG. 4 shows a semiconductor device 10 D according to the fourth embodiment of the present invention.
  • the semiconductor device 10 D of the present embodiment is characterized by two or more upper device units 11 B and 11 C being stacked on an interposer substrate 13 D.
  • the upper device unit 11 B located in the topmost part includes a semiconductor element 14 B and a semiconductor element 14 C on a first wiring substrate 16 B.
  • the semiconductor element 14 C is flip chip bonded to the first wiring substrate 16 B, and the semiconductor element 14 B is adhesively fixed to the semiconductor element 14 C by an adhesive 45 with its face up. Further, the semiconductor element 14 B is electrically connected to the first wiring substrate 16 B by wires. Furthermore, connection electrodes 26 A are formed on the undersurface of the first wiring substrate 16 B, that is, on the surface that faces the upper device unit 11 C.
  • the upper device unit 11 C is arranged below the upper device unit 11 B.
  • the upper device unit 11 C includes a semiconductor element 14 D, and a first wiring substrate 16 C to which the semiconductor element 14 D is flip chip bonded. Further, the external connection terminals 22 are formed on the first wiring substrate 16 C, facing the interposer substrate 13 D. Furthermore, connection electrodes 26 B are formed on the upper surface of the first wiring substrate 16 C, the upper surface facing the upper device unit 11 B.
  • the upper device unit 11 B and the upper device unit 11 C are electrically connected by stacking bumps 38 A that connect the connection electrodes 26 A formed on the first wiring substrate 16 B of the upper device unit 11 B and the connection electrodes 26 B formed on the first wiring substrate 16 C of the upper device unit 11 C.
  • the lower device unit 12 B includes two semiconductor devices 15 B and 15 C in the present embodiment.
  • the bumps 25 are formed on each of the semiconductor devices 15 B and 15 C, which devices are flip chip bonded with the bumps 25 being connected to the bump connecting electrodes 27 formed on the second wiring substrate 17 B.
  • the second conductive members 33 and the third conductive members 34 A are formed on the upper surface 31 A of the interposer substrate 13 D, and the third conductive members 34 B, to which the first conductive members 32 are bonded, are formed on the undersurface 31 B of the interposer substrate 13 D.
  • the third conductive members 34 A and the third conductive members 34 B are electrically connected by vias that are formed through a circuit board 18 D of the interposer substrate 13 D.
  • the semiconductor device 10 D of the present embodiment includes the two upper device units 11 B and 11 C stacked and mounted on the interposer substrate 13 D. In this manner, the semiconductor device 10 D can provide further advanced features and multiple functions.
  • the number of the upper device units that are stacked is not limited to two as in the present embodiment, and three or more upper device units may be stacked. Electrical connections between upper device units, and electrical connections between each upper device unit and the interposer substrate 13 D can be carried out by flip chip bonding, TAB connection, wire connection, etc. Further, in each upper device unit, the semiconductor device can be mounted on either or both of the upper surfaces and the undersurface of the first wiring substrate.
  • FIG. 5 shows a semiconductor device 10 E according to the fifth embodiment of the present invention.
  • the semiconductor device 10 E is characterized by two or more lower device units 12 A and 12 C being mounted below an interposer substrate 13 D.
  • the lower device unit 12 A located at the bottom part is the same as the lower device unit 12 A of the semiconductor device 10 A according to the first embodiment as shown in FIG. 1 .
  • the lower device unit 12 C is stacked on the lower device unit 12 A.
  • a semiconductor element 15 E is flip chip bonded on the undersurface of a second wiring substrate 17 C of the lower device unit 12 C, and a semiconductor element 15 D is flip chip bonded on the upper surface of the second wiring substrate 17 C. In this manner, the packaging density of the semiconductor devices 15 D and 15 E is increased. Further, the connection electrodes 26 C are formed on the upper surface of the second wiring substrate 17 C, and the connection electrodes 26 D are formed on the undersurface of the second wiring substrate 17 C.
  • the lower device unit 12 A and the lower device unit 12 C are electrically connected by stacking bumps 38 B that connect the connection electrodes 26 D formed on the second wiring substrate 17 C and the connection electrodes 26 formed on the second wiring substrate 17 A. Further, the interposer substrate 13 D and the lower device unit 12 C are electrically connected by the first conductive members 32 that connect the third conductive member 34 B formed on the undersurface 31 B of the circuit board 18 D and the connection electrodes 26 C formed on the second wiring substrate 17 C.
  • the upper device unit 11 D of the present embodiment includes a semiconductor element 14 E and a semiconductor element 14 F that are stacked on a first wiring substrate 16 D.
  • the semiconductor element 14 F is adhesively fixed by an adhesive 45 F with its face up to the upper surface of the first wiring substrate 16 D
  • the semiconductor element 14 E is adhesively fixed by an adhesive 45 E with its face up on the top of the semiconductor element 14 F.
  • the semiconductor devices 14 E and 14 F are electrically connected to the first wiring substrate 16 D by wires.
  • the interposer substrate 13 D is the same as the interposer substrate 13 D of the fourth embodiment shown in FIG. 4 .
  • the semiconductor device 10 E of the present embodiment includes the two lower device units 12 A and 12 C that are stacked below the interposer substrate 13 D. In this manner, the semiconductor device 10 E is capable of offering advanced features and multiple functions.
  • the number of the lower device units that are stacked is not limited to two as in the present embodiment, and the number can be three or greater, where electrical connections between the lower device units, and the electrical connections between each lower device unit and the interposer substrate 13 D can be selected from flip chip bonding, TAB connection, wire connection, etc. Further, in each lower device unit, a semiconductor device can be mounted on either or both of the upper surface and the undersurface of the second wiring substrate 17 C.
  • the present embodiment employs a multilayer substrate with inner layer wiring as the interposer substrate 13 D, a single surface wiring substrate and a double surface wiring substrate may be employed as shown in the embodiments described above.
  • FIG. 6 shows a semiconductor device 10 F according to the sixth embodiment of the present invention.
  • the semiconductor device 10 F is characterized by including passive components 40 mounted on a circuit board 18 E that is a multilayered substrate constituting an interposer substrate 13 E.
  • the circuit board 18 E of the interposer substrate 13 E includes third conductive members 34 C serving as an inner layer wiring.
  • the third conductive members 34 C are electrically connected to the first conductive members 32 and the second conductive members 33 .
  • an upper device unit 11 E that is mounted on the circuit board 18 E by flip chip bonding includes a first wiring substrate 16 D on which a semiconductor element 14 G is mounted.
  • the passive components 40 are mounted on the upper surface of the interposer substrate 13 E.
  • the passive components 40 are small electronic parts, such as a chip capacitor and a chip resistor.
  • the passive components 40 are soldered to the upper surface of the interposer substrate 13 E.
  • the semiconductor device 10 F of the present embodiment employs the multilayered substrate as the interposer substrate 13 E, the third conductive members 34 C, serving as the inner layer wiring, can be densely arranged.
  • the interposer substrate 13 E since the inner layer wiring (served by the third conductive members 34 C) is formed inside the interposer substrate 13 E, the interposer substrate 13 E has high rigidity compared with a single surface wiring substrate and a double surface wiring substrate, suppressing curvature and deformation due to temperature change occurring in the interposer substrate 13 E, and, therefore, the reliability of the semiconductor device 10 F is enhanced.
  • the semiconductor device 10 F of the present embodiment includes the passive components 40 mounted on the interposer substrate 13 E, an RF device having desired electrical properties can be provided.
  • the present embodiment is described as an example using a multilayer substrate with inner layer wiring as the interposer substrate 13 E, a single surface monolayer wiring substrate, and a double surface monolayer wiring substrate can also be used as described above.
  • FIG. 7 shows a semiconductor device 10 G according to the seventh embodiment of the present invention.
  • the passive components 40 are prepared separately from the circuit board 18 E, and mounted on the interposer substrate 13 E by soldering.
  • the semiconductor device 10 G includes an interposer substrate 13 F that is multilayered and includes the third conductive members 34 C and a circuit board 18 F.
  • the circuit board 18 F includes an inductor section 41 and a capacitor section 42 that serve as passive components constituted by inner layer wiring.
  • the passive components are formed by inner layer wiring according to the present embodiment, the passive components may be structured in other manners, such as embedding independent passive components in the multilayered substrate, with the independent passive components being wire-connected to the inner layer wiring.
  • the passive components 41 and 42 are incorporated into the interposer substrate 13 F by forming the inductor section 41 and the capacitor section 42 as inner layer wiring of the circuit board 18 F that is a multilayer substrate. In this manner, no passive components independent from the circuit board 18 F need to be prepared, reducing the number of components to be mounted, and reducing manufacturing cost.
  • the present invention provides semiconductor devices that offer various effects and advantages as follows.
  • the stacked semiconductor device of the present invention uses general-purpose semiconductor device units, external connection terminals arrangement of which are beforehand given, design flexibility is improved, and a system device served by multiple semiconductor devices can be easily realized. In this manner, the requirements for advanced features and multiple functions are satisfied.
  • solder bumps are used as the first conductive members, and a simple and low cost stacking structure is realized.
  • the stacked semiconductor device of the present invention is made thin.
  • the present invention also provides a stacked semiconductor device with a multi-layer substrate
  • the third conductive members can provide a complicated circuit pattern, compared with a configuration wherein the third conductive members are formed only on one surface, and, therefore, the design flexibility of the semiconductor device is improved. Further, since the rigidity of the third wiring substrate is increased, curvature and deformation of the substrate occurring due to temperature change is suppressed, enhancing the reliability of the semiconductor device.
  • the present invention also provides a stacked semiconductor device that is capable of providing advanced features and multiple functions.
  • the present invention provides a stacked semiconductor device with a higher-density wiring substrate by using a multilayered substrate as the third wiring substrate. Further, since rigidity of the multilayered substrate is increased compared with a single surface wiring substrate and a double surface wiring substrate, curvature and deformation of the third wiring substrate occurring due to temperature change is suppressed, and the manufacturing yield is raised.
  • a semiconductor device suitably serving as an RF device can be constituted.
  • passive components are incorporated in the third wiring substrate, thereby dispensing with independent passive components, reducing the manufacturing cost.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
US10/763,267 2003-03-11 2004-01-26 Stacked semiconductor device Expired - Lifetime US7049692B2 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003-065392 2003-03-11
JP2003065392A JP3917946B2 (ja) 2003-03-11 2003-03-11 積層型半導体装置

Publications (2)

Publication Number Publication Date
US20040178508A1 US20040178508A1 (en) 2004-09-16
US7049692B2 true US7049692B2 (en) 2006-05-23

Family

ID=32959181

Family Applications (1)

Application Number Title Priority Date Filing Date
US10/763,267 Expired - Lifetime US7049692B2 (en) 2003-03-11 2004-01-26 Stacked semiconductor device

Country Status (2)

Country Link
US (1) US7049692B2 (ja)
JP (1) JP3917946B2 (ja)

Cited By (94)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050133932A1 (en) * 2003-12-19 2005-06-23 Jens Pohl Semiconductor module with a semiconductor stack, and methods for its production
US20060076665A1 (en) * 2004-10-07 2006-04-13 Jae-Hong Kim Package stack and manufacturing method thereof
US20070007643A1 (en) * 2005-07-05 2007-01-11 Samsung Electro-Mechanics Co., Ltd. Semiconductor multi-chip package
US7242081B1 (en) * 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US20080099800A1 (en) * 2006-10-25 2008-05-01 Miller Melvy F Integrated matching network and method for manufacturing integrated matching networks
US20080150132A1 (en) * 2006-12-21 2008-06-26 Tom Hu Stack up pcb substrate for high density interconnect packages
US20080155820A1 (en) * 2006-12-27 2008-07-03 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method thereof, and semiconductor device
US20080185614A1 (en) * 2005-04-28 2008-08-07 Nxp B.V. Integrated Circuit Assembly with Passive Integration Substrate for Power and Ground Line Routing on Top of an Integrated Circuit Chip
US20080211084A1 (en) * 2007-03-03 2008-09-04 Seng Guan Chow Integrated circuit package system with interposer
US20080230887A1 (en) * 2007-03-23 2008-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US20080230889A1 (en) * 2007-02-27 2008-09-25 Martin Standing Semiconductor package
US20090243073A1 (en) * 2008-03-27 2009-10-01 Flynn Carson Stacked integrated circuit package system
US20090243072A1 (en) * 2008-02-29 2009-10-01 Jong-Woo Ha Stacked integrated circuit package system
US20090296310A1 (en) * 2008-06-03 2009-12-03 Azuma Chikara Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors
US20100000775A1 (en) * 2008-07-03 2010-01-07 Advanced Semiconductor Engineering, Inc. Circuit substrate and method of fabricating the same and chip package structure
US20100102327A1 (en) * 2008-02-26 2010-04-29 International Rectifier Corporation (El Segundo, Ca) Semiconductor device and passive component integration in a semiconductor package
US20100155914A1 (en) * 2007-03-12 2010-06-24 Lim Seung-Won Power Module Having Stacked Flip-Chip and Method of Fabricating the Power Module
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US20100171207A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Shen Stackable semiconductor device packages
US20100171205A1 (en) * 2009-01-07 2010-07-08 Kuang-Hsiung Chen Stackable Semiconductor Device Packages
US20110049704A1 (en) * 2009-08-31 2011-03-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with integrated heatsinks
US20110117700A1 (en) * 2009-11-18 2011-05-19 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US20110127636A1 (en) * 2009-11-27 2011-06-02 Samsung Electro-Mechanics Co., Ltd. Integrated passive device assembly
US20110156251A1 (en) * 2009-12-31 2011-06-30 Chi-Chih Chu Semiconductor Package
US20110193205A1 (en) * 2010-02-10 2011-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having stacking functionality and including interposer
US8227905B1 (en) * 2004-06-08 2012-07-24 Amkor Technology, Inc. Stackable semiconductor package
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US20130181359A1 (en) * 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
US20130264716A1 (en) * 2007-12-26 2013-10-10 Stats Chippac, Ltd. System-In-Package Having Integrated Passive Devices and Method Therefor
US8569885B2 (en) 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8643167B2 (en) 2011-01-06 2014-02-04 Advanced Semiconductor Engineering, Inc. Semiconductor package with through silicon vias and method for making the same
US8674516B2 (en) 2011-06-22 2014-03-18 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
US9013892B2 (en) 2012-12-25 2015-04-21 Industrial Technology Research Institute Chip stacking structure
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US20150359119A1 (en) * 2013-02-22 2015-12-10 Panasonic Corporation Electronic component package
US20160126196A1 (en) 2014-11-03 2016-05-05 Rf Micro Devices, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US9368566B2 (en) 2014-07-17 2016-06-14 Qualcomm Incorporated Package on package (PoP) integrated device comprising a capacitor in a substrate
US20160204092A1 (en) * 2004-06-30 2016-07-14 Renesas Electronics Corporation Semiconductor device
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US20170323804A1 (en) * 2016-05-09 2017-11-09 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US9831165B2 (en) * 2014-08-29 2017-11-28 Phoenix Pioneer Technology Co., Ltd. Interposer substrate and method of manufacturing the same
US20170358511A1 (en) 2016-06-10 2017-12-14 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US20180019184A1 (en) 2016-07-18 2018-01-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US20180044177A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US9953931B1 (en) * 2016-10-25 2018-04-24 Advanced Semiconductor Engineering, Inc Semiconductor device package and a method of manufacturing the same
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US9978715B2 (en) 2013-06-14 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US10020206B2 (en) 2015-03-25 2018-07-10 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10038055B2 (en) 2015-05-22 2018-07-31 Qorvo Us, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US20180228030A1 (en) 2014-10-01 2018-08-09 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10062637B2 (en) 2013-10-31 2018-08-28 Qorvo Us, Inc. Method of manufacture for a semiconductor device
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10109550B2 (en) 2016-08-12 2018-10-23 Qorvo Us, Inc. Wafer-level package with enhanced performance
US20190013255A1 (en) 2017-07-06 2019-01-10 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US20190074271A1 (en) 2017-09-05 2019-03-07 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer
US20190333875A1 (en) * 2018-04-27 2019-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated inductor and manufacturing method thereof
US10486963B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10529676B2 (en) 2016-06-08 2020-01-07 Samsung Electronics Co., Ltd. Semiconductor assembly with package on package structure and electronic device including the same
US10553563B2 (en) * 2018-05-30 2020-02-04 Epistar Corporation Electronic device
US20200235054A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784233B2 (en) * 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11018215B2 (en) * 2019-03-14 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package and manufacturing method thereof
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US20210296199A1 (en) 2018-11-29 2021-09-23 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US20220108938A1 (en) 2019-01-23 2022-04-07 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
USRE49046E1 (en) 2012-05-03 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
US20220139862A1 (en) 2019-01-23 2022-05-05 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US12046535B2 (en) 2018-07-02 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon
US12062701B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
US12482731B2 (en) 2020-12-11 2025-11-25 Qorvo Us, Inc. Multi-level 3D stacked package and methods of forming the same

Families Citing this family (59)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7294928B2 (en) * 2002-09-06 2007-11-13 Tessera, Inc. Components, methods and assemblies for stacked packages
JP4110992B2 (ja) 2003-02-07 2008-07-02 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法および電子デバイスの製造方法
JP4096774B2 (ja) 2003-03-24 2008-06-04 セイコーエプソン株式会社 半導体装置、電子デバイス、電子機器、半導体装置の製造方法及び電子デバイスの製造方法
JP2004349495A (ja) 2003-03-25 2004-12-09 Seiko Epson Corp 半導体装置、電子デバイス、電子機器および半導体装置の製造方法
US7265446B2 (en) * 2003-10-06 2007-09-04 Elpida Memory, Inc. Mounting structure for semiconductor parts and semiconductor device
JP2005123463A (ja) 2003-10-17 2005-05-12 Seiko Epson Corp 半導体装置及びその製造方法、半導体装置モジュール、回路基板並びに電子機器
US7365428B2 (en) * 2004-10-22 2008-04-29 Intel Corporation Array capacitor with resistive structure
JP2006196709A (ja) * 2005-01-13 2006-07-27 Sharp Corp 半導体装置およびその製造方法
US8643163B2 (en) * 2005-08-08 2014-02-04 Stats Chippac Ltd. Integrated circuit package-on-package stacking system and method of manufacture thereof
US20070108583A1 (en) * 2005-08-08 2007-05-17 Stats Chippac Ltd. Integrated circuit package-on-package stacking system
SG130055A1 (en) 2005-08-19 2007-03-20 Micron Technology Inc Microelectronic devices, stacked microelectronic devices, and methods for manufacturing microelectronic devices
SG130066A1 (en) 2005-08-26 2007-03-20 Micron Technology Inc Microelectronic device packages, stacked microelectronic device packages, and methods for manufacturing microelectronic devices
US7829989B2 (en) * 2005-09-07 2010-11-09 Alpha & Omega Semiconductor, Ltd. Vertical packaged IC device modules with interconnected 3D laminates directly contacts wafer backside
US7838977B2 (en) * 2005-09-07 2010-11-23 Alpha & Omega Semiconductor, Ltd. Packages for electronic devices implemented with laminated board with a top and a bottom patterned metal layers
EP2290682A3 (en) 2005-12-14 2011-10-05 Shinko Electric Industries Co., Ltd. Package with a chip embedded between two substrates and method of manufacturing the same
TWI459512B (zh) * 2005-12-22 2014-11-01 萬國半導體股份有限公司 使用相互連接的三維層片將垂直封裝的ｍｏｓｆｅｔ和積體電路功率器件構建成集成模組
US7990727B1 (en) * 2006-04-03 2011-08-02 Aprolase Development Co., Llc Ball grid array stack
US7390700B2 (en) * 2006-04-07 2008-06-24 Texas Instruments Incorporated Packaged system of semiconductor chips having a semiconductor interposer
JP5598787B2 (ja) 2006-04-17 2014-10-01 マイクロンメモリジャパン株式会社 積層型半導体装置の製造方法
JP4976767B2 (ja) * 2006-07-19 2012-07-18 キヤノン株式会社 積層形半導体装置
JP5005321B2 (ja) * 2006-11-08 2012-08-22 パナソニック株式会社 半導体装置
US20080180921A1 (en) * 2007-01-31 2008-07-31 Cyntec Co., Ltd. Electronic package structure
JP2009094434A (ja) 2007-10-12 2009-04-30 Elpida Memory Inc 半導体装置およびその製造方法
JP2009135398A (ja) * 2007-11-29 2009-06-18 Ibiden Co Ltd 組合せ基板
US8247893B2 (en) * 2007-12-27 2012-08-21 Stats Chippac Ltd. Mountable integrated circuit package system with intra-stack encapsulation
US7800212B2 (en) * 2007-12-27 2010-09-21 Stats Chippac Ltd. Mountable integrated circuit package system with stacking interposer
JP5543072B2 (ja) * 2008-01-23 2014-07-09 ピーエスフォー ルクスコ エスエイアールエル 積層型半導体装置
US7919871B2 (en) * 2008-03-21 2011-04-05 Stats Chippac Ltd. Integrated circuit package system for stackable devices
US7750455B2 (en) * 2008-08-08 2010-07-06 Stats Chippac Ltd. Triple tier package on package system
US20100133534A1 (en) * 2008-12-03 2010-06-03 Byung Tai Do Integrated circuit packaging system with interposer and flip chip and method of manufacture thereof
US8441133B2 (en) 2009-03-31 2013-05-14 Ibiden Co., Ltd. Semiconductor device
CN101887878A (zh) * 2009-05-14 2010-11-17 艾普特佩克股份有限公司 光电传感器封装
US8106499B2 (en) * 2009-06-20 2012-01-31 Stats Chippac Ltd. Integrated circuit packaging system with a dual substrate package and method of manufacture thereof
JP2011146519A (ja) * 2010-01-14 2011-07-28 Panasonic Corp 半導体装置及びその製造方法
KR101046394B1 (ko) * 2010-02-03 2011-07-05 주식회사 하이닉스반도체 스택 패키지
CN102403275B (zh) * 2010-09-17 2014-01-15 深南电路有限公司 一种堆叠封装结构及其制作方法
KR101808478B1 (ko) * 2011-08-16 2017-12-12 인텔 코포레이션 Ｐｏｐ 구조체
KR101247342B1 (ko) * 2011-09-30 2013-03-26 에스티에스반도체통신 주식회사 패키지 온 패키지 제조방법
US9691636B2 (en) 2012-02-02 2017-06-27 Taiwan Semiconductor Manufacturing Co., Ltd. Interposer frame and method of manufacturing the same
US8749043B2 (en) * 2012-03-01 2014-06-10 Taiwan Semiconductor Manufacturing Company, Ltd. Package on package structure
KR20150033937A (ko) 2013-09-25 2015-04-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 및 그 제작 방법
WO2015047330A1 (en) * 2013-09-27 2015-04-02 Intel Corporation Die package with superposer substrate for passive components
KR102245770B1 (ko) 2013-10-29 2021-04-28 삼성전자주식회사 반도체 패키지 장치
US20150279815A1 (en) * 2014-03-28 2015-10-01 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Substrate Having Conductive Columns
TWI554174B (zh) * 2014-11-04 2016-10-11 上海兆芯集成電路有限公司 線路基板和半導體封裝結構
US9859202B2 (en) * 2015-06-24 2018-01-02 Dyi-chung Hu Spacer connector
KR101616272B1 (ko) * 2015-07-29 2016-05-02 앰코 테크놀로지 코리아 주식회사 반도체 패키지 제작 방법
CN106971993B (zh) * 2016-01-14 2021-10-15 三星电子株式会社 半导体封装件
KR102595276B1 (ko) 2016-01-14 2023-10-31 삼성전자주식회사 반도체 패키지
WO2018123699A1 (ja) * 2016-12-27 2018-07-05 株式会社村田製作所 高周波モジュール
US10804115B2 (en) 2017-08-03 2020-10-13 General Electric Company Electronics package with integrated interconnect structure and method of manufacturing thereof
US10541209B2 (en) * 2017-08-03 2020-01-21 General Electric Company Electronics package including integrated electromagnetic interference shield and method of manufacturing thereof
US10879197B2 (en) * 2017-08-30 2020-12-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package structure and method of fabricating package structure
US10468384B2 (en) * 2017-09-15 2019-11-05 STATS ChipPAC Pte. Ltd. Semiconductor device and method of forming embedded die substrate, and system-in-package modules with the same
KR102538181B1 (ko) 2018-10-24 2023-06-01 삼성전자주식회사 반도체 패키지
JP2020181842A (ja) * 2019-04-23 2020-11-05 京セラ株式会社 回路基板およびプローブカード
JP2021148653A (ja) * 2020-03-19 2021-09-27 キオクシア株式会社 半導体装置、検査用部品、および検査装置
WO2022129408A1 (de) * 2020-12-17 2022-06-23 Tdk Electronics Ag Verbindungsplättchen zur elektrischen verbindung von leiterplatten und verfahren zur herstellung eines verbindungsplättchens
CN113573499B (zh) * 2021-06-29 2023-03-10 联宝(合肥)电子科技有限公司 一种PoP装配工艺及设备

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252334A (ja) 1993-02-26 1994-09-09 Hitachi Constr Mach Co Ltd 半導体装置
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
JPH11260999A (ja) 1998-03-13 1999-09-24 Sumitomo Metal Ind Ltd ノイズを低減した積層半導体装置モジュール
JP2001358248A (ja) 2000-06-13 2001-12-26 Hitachi Ltd キャパシタを内蔵した回路基板とその製造方法
JP2002158312A (ja) 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd ３次元実装用半導体パッケージ、その製造方法、および半導体装置

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH06252334A (ja) 1993-02-26 1994-09-09 Hitachi Constr Mach Co Ltd 半導体装置
US5594275A (en) * 1993-11-18 1997-01-14 Samsung Electronics Co., Ltd. J-leaded semiconductor package having a plurality of stacked ball grid array packages
JPH11260999A (ja) 1998-03-13 1999-09-24 Sumitomo Metal Ind Ltd ノイズを低減した積層半導体装置モジュール
JP2001358248A (ja) 2000-06-13 2001-12-26 Hitachi Ltd キャパシタを内蔵した回路基板とその製造方法
JP2002158312A (ja) 2000-11-17 2002-05-31 Oki Electric Ind Co Ltd ３次元実装用半導体パッケージ、その製造方法、および半導体装置

Cited By (166)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050133932A1 (en) * 2003-12-19 2005-06-23 Jens Pohl Semiconductor module with a semiconductor stack, and methods for its production
US7456495B2 (en) * 2003-12-19 2008-11-25 Infineon Technologies Ag Semiconductor module with a semiconductor stack, and methods for its production
US8227905B1 (en) * 2004-06-08 2012-07-24 Amkor Technology, Inc. Stackable semiconductor package
US8466545B1 (en) 2004-06-08 2013-06-18 Amkor Technology, Inc. Stackable semiconductor package
US20160204092A1 (en) * 2004-06-30 2016-07-14 Renesas Electronics Corporation Semiconductor device
US10672750B2 (en) 2004-06-30 2020-06-02 Renesas Electronics Corporation Semiconductor device
US7420814B2 (en) * 2004-10-07 2008-09-02 Samsung Electronics Co., Ltd. Package stack and manufacturing method thereof
US20060076665A1 (en) * 2004-10-07 2006-04-13 Jae-Hong Kim Package stack and manufacturing method thereof
US20080185614A1 (en) * 2005-04-28 2008-08-07 Nxp B.V. Integrated Circuit Assembly with Passive Integration Substrate for Power and Ground Line Routing on Top of an Integrated Circuit Chip
US8178901B2 (en) * 2005-04-28 2012-05-15 St-Ericsson Sa Integrated circuit assembly with passive integration substrate for power and ground line routing on top of an integrated circuit chip
US20070007643A1 (en) * 2005-07-05 2007-01-11 Samsung Electro-Mechanics Co., Ltd. Semiconductor multi-chip package
US7242081B1 (en) * 2006-04-24 2007-07-10 Advanced Semiconductor Engineering Inc. Stacked package structure
US7667334B2 (en) * 2006-10-25 2010-02-23 Freescale Semiconductor, Inc. Integrated matching networks and RF devices that include an integrated matching network
US20080099800A1 (en) * 2006-10-25 2008-05-01 Miller Melvy F Integrated matching network and method for manufacturing integrated matching networks
US7528062B2 (en) * 2006-10-25 2009-05-05 Freescale Semiconductor, Inc. Integrated matching network and method for manufacturing integrated matching networks
US20090152698A1 (en) * 2006-10-25 2009-06-18 Freescale Semiconductor, Inc. Integrated matching networks and rf devices that include an integrated matching network
US20080150132A1 (en) * 2006-12-21 2008-06-26 Tom Hu Stack up pcb substrate for high density interconnect packages
US20080155820A1 (en) * 2006-12-27 2008-07-03 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method thereof, and semiconductor device
US7901986B2 (en) 2006-12-27 2011-03-08 Shinko Electric Industries Co., Ltd. Wiring substrate, manufacturing method thereof, and semiconductor device
US9054090B2 (en) 2007-02-27 2015-06-09 International Rectifier Corporation Power semiconductor package
US20080230889A1 (en) * 2007-02-27 2008-09-25 Martin Standing Semiconductor package
US9837393B2 (en) 2007-02-27 2017-12-05 Infineon Technologies Americas Corp. Semiconductor package with integrated semiconductor devices and passive component
US8786072B2 (en) 2007-02-27 2014-07-22 International Rectifier Corporation Semiconductor package
US9041187B2 (en) 2007-02-27 2015-05-26 International Rectifier Corporation Power semiconductor package with multiple dies
US20080211084A1 (en) * 2007-03-03 2008-09-04 Seng Guan Chow Integrated circuit package system with interposer
US8685792B2 (en) * 2007-03-03 2014-04-01 Stats Chippac Ltd. Integrated circuit package system with interposer
TWI479642B (zh) * 2007-03-03 2015-04-01 星科金朋有限公司 具有間隔件之積體電路封裝件系統
US8766419B2 (en) * 2007-03-12 2014-07-01 Fairchild Korea Semiconductor, Ltd. Power module having stacked flip-chip and method of fabricating the power module
US9130065B2 (en) 2007-03-12 2015-09-08 Fairchild Korea Semiconductor, Ltd Power module having stacked flip-chip and method for fabricating the power module
US20100155914A1 (en) * 2007-03-12 2010-06-24 Lim Seung-Won Power Module Having Stacked Flip-Chip and Method of Fabricating the Power Module
US20080230887A1 (en) * 2007-03-23 2008-09-25 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US8143101B2 (en) 2007-03-23 2012-03-27 Advanced Semiconductor Engineering, Inc. Semiconductor package and the method of making the same
US9171797B2 (en) * 2007-12-26 2015-10-27 Stats Chippac, Ltd. System-in-package having integrated passive devices and method therefor
US20130264716A1 (en) * 2007-12-26 2013-10-10 Stats Chippac, Ltd. System-In-Package Having Integrated Passive Devices and Method Therefor
US9147644B2 (en) * 2008-02-26 2015-09-29 International Rectifier Corporation Semiconductor device and passive component integration in a semiconductor package
US20100102327A1 (en) * 2008-02-26 2010-04-29 International Rectifier Corporation (El Segundo, Ca) Semiconductor device and passive component integration in a semiconductor package
US20090243072A1 (en) * 2008-02-29 2009-10-01 Jong-Woo Ha Stacked integrated circuit package system
US9236319B2 (en) 2008-02-29 2016-01-12 Stats Chippac Ltd. Stacked integrated circuit package system
US7750454B2 (en) 2008-03-27 2010-07-06 Stats Chippac Ltd. Stacked integrated circuit package system
US8067268B2 (en) 2008-03-27 2011-11-29 Stats Chippac Ltd. Stacked integrated circuit package system and method for manufacturing thereof
US20090243073A1 (en) * 2008-03-27 2009-10-01 Flynn Carson Stacked integrated circuit package system
US20100224979A1 (en) * 2008-03-27 2010-09-09 Flynn Carson Stacked integrated circuit package system and method for manufacturing thereof
US20090296310A1 (en) * 2008-06-03 2009-12-03 Azuma Chikara Chip capacitor precursors, packaged semiconductors, and assembly method for converting the precursors to capacitors
US8158888B2 (en) 2008-07-03 2012-04-17 Advanced Semiconductor Engineering, Inc. Circuit substrate and method of fabricating the same and chip package structure
US20100000775A1 (en) * 2008-07-03 2010-01-07 Advanced Semiconductor Engineering, Inc. Circuit substrate and method of fabricating the same and chip package structure
US20100171206A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Chu Package-on-Package Device, Semiconductor Package, and Method for Manufacturing The Same
US8076765B2 (en) 2009-01-07 2011-12-13 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages including openings partially exposing connecting elements, conductive bumps, or conductive conductors
US20100171207A1 (en) * 2009-01-07 2010-07-08 Chi-Chih Shen Stackable semiconductor device packages
US8012797B2 (en) 2009-01-07 2011-09-06 Advanced Semiconductor Engineering, Inc. Method for forming stackable semiconductor device packages including openings with conductive bumps of specified geometries
US20100171205A1 (en) * 2009-01-07 2010-07-08 Kuang-Hsiung Chen Stackable Semiconductor Device Packages
US20110049704A1 (en) * 2009-08-31 2011-03-03 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with integrated heatsinks
US20110117700A1 (en) * 2009-11-18 2011-05-19 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US8198131B2 (en) 2009-11-18 2012-06-12 Advanced Semiconductor Engineering, Inc. Stackable semiconductor device packages
US20110127636A1 (en) * 2009-11-27 2011-06-02 Samsung Electro-Mechanics Co., Ltd. Integrated passive device assembly
US20110156251A1 (en) * 2009-12-31 2011-06-30 Chi-Chih Chu Semiconductor Package
US8405212B2 (en) 2009-12-31 2013-03-26 Advanced Semiconductor Engineering, Inc. Semiconductor package
US9196597B2 (en) 2010-01-13 2015-11-24 Advanced Semiconductor Engineering, Inc. Semiconductor package with single sided substrate design and manufacturing methods thereof
US8823156B2 (en) 2010-02-10 2014-09-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having stacking functionality and including interposer
US20110193205A1 (en) * 2010-02-10 2011-08-11 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having stacking functionality and including interposer
US9349611B2 (en) 2010-03-22 2016-05-24 Advanced Semiconductor Engineering, Inc. Stackable semiconductor package and manufacturing method thereof
US8278746B2 (en) 2010-04-02 2012-10-02 Advanced Semiconductor Engineering, Inc. Semiconductor device packages including connecting elements
US8624374B2 (en) 2010-04-02 2014-01-07 Advanced Semiconductor Engineering, Inc. Semiconductor device packages with fan-out and with connecting elements for stacking and manufacturing methods thereof
US8569885B2 (en) 2010-10-29 2013-10-29 Advanced Semiconductor Engineering, Inc. Stacked semiconductor packages and related methods
US8643167B2 (en) 2011-01-06 2014-02-04 Advanced Semiconductor Engineering, Inc. Semiconductor package with through silicon vias and method for making the same
US9171792B2 (en) 2011-02-28 2015-10-27 Advanced Semiconductor Engineering, Inc. Semiconductor device packages having a side-by-side device arrangement and stacking functionality
US8674516B2 (en) 2011-06-22 2014-03-18 Stats Chippac Ltd. Integrated circuit packaging system with vertical interconnects and method of manufacture thereof
US9646922B2 (en) 2012-01-13 2017-05-09 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for thinner package on package structures
US20130181359A1 (en) * 2012-01-13 2013-07-18 TW Semiconductor Manufacturing Company, Ltd. Methods and Apparatus for Thinner Package on Package Structures
TWI601266B (zh) * 2012-01-13 2017-10-01 台灣積體電路製造股份有限公司 半導體裝置結構及其製造方法
USRE49046E1 (en) 2012-05-03 2022-04-19 Taiwan Semiconductor Manufacturing Company, Ltd. Methods and apparatus for package on package devices
US9013892B2 (en) 2012-12-25 2015-04-21 Industrial Technology Research Institute Chip stacking structure
US20150359119A1 (en) * 2013-02-22 2015-12-10 Panasonic Corporation Electronic component package
US9474179B2 (en) * 2013-02-22 2016-10-18 Panasonic Corporation Electronic component package
US9812350B2 (en) 2013-03-06 2017-11-07 Qorvo Us, Inc. Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
US10134627B2 (en) 2013-03-06 2018-11-20 Qorvo Us, Inc. Silicon-on-plastic semiconductor device with interfacial adhesion layer
US9978715B2 (en) 2013-06-14 2018-05-22 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US10229894B2 (en) 2013-06-14 2019-03-12 Advanced Semiconductor Engineering, Inc. Semiconductor package structure and semiconductor process
US10062637B2 (en) 2013-10-31 2018-08-28 Qorvo Us, Inc. Method of manufacture for a semiconductor device
US9368566B2 (en) 2014-07-17 2016-06-14 Qualcomm Incorporated Package on package (PoP) integrated device comprising a capacitor in a substrate
US10319607B2 (en) * 2014-08-22 2019-06-11 Taiwan Semiconductor Manufacturing Company, Ltd. Package-on-package structure with organic interposer
US9831165B2 (en) * 2014-08-29 2017-11-28 Phoenix Pioneer Technology Co., Ltd. Interposer substrate and method of manufacturing the same
US9824951B2 (en) 2014-09-12 2017-11-21 Qorvo Us, Inc. Printed circuit module having semiconductor device with a polymer substrate and methods of manufacturing the same
US10492301B2 (en) 2014-10-01 2019-11-26 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US20180228030A1 (en) 2014-10-01 2018-08-09 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10085352B2 (en) 2014-10-01 2018-09-25 Qorvo Us, Inc. Method for manufacturing an integrated circuit package
US10199301B2 (en) 2014-11-03 2019-02-05 Qorvo Us, Inc. Methods of manufacturing a printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US20160126196A1 (en) 2014-11-03 2016-05-05 Rf Micro Devices, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US10121718B2 (en) 2014-11-03 2018-11-06 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US10109548B2 (en) 2014-11-03 2018-10-23 Qorvo Us, Inc. Printed circuit module having a semiconductor device with a protective layer in place of a low-resistivity handle layer
US9960145B2 (en) 2015-03-25 2018-05-01 Qorvo Us, Inc. Flip chip module with enhanced properties
US10020206B2 (en) 2015-03-25 2018-07-10 Qorvo Us, Inc. Encapsulated dies with enhanced thermal performance
US10038055B2 (en) 2015-05-22 2018-07-31 Qorvo Us, Inc. Substrate structure with embedded layer for post-processing silicon handle elimination
US10276495B2 (en) 2015-09-11 2019-04-30 Qorvo Us, Inc. Backside semiconductor die trimming
US10020405B2 (en) 2016-01-19 2018-07-10 Qorvo Us, Inc. Microelectronics package with integrated sensors
US10062583B2 (en) * 2016-05-09 2018-08-28 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US20170323804A1 (en) * 2016-05-09 2017-11-09 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10090262B2 (en) 2016-05-09 2018-10-02 Qorvo Us, Inc. Microelectronics package with inductive element and magnetically enhanced mold compound component
US10882740B2 (en) 2016-05-20 2021-01-05 Qorvo Us, Inc. Wafer-level package with enhanced performance and manufacturing method thereof
US10773952B2 (en) 2016-05-20 2020-09-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10784149B2 (en) 2016-05-20 2020-09-22 Qorvo Us, Inc. Air-cavity module with enhanced device isolation
US11037890B2 (en) 2016-06-08 2021-06-15 Samsung Electronics Co., Ltd. Semiconductor assembly with package on package structure and electronic device including the same
US10529676B2 (en) 2016-06-08 2020-01-07 Samsung Electronics Co., Ltd. Semiconductor assembly with package on package structure and electronic device including the same
US20180197803A1 (en) 2016-06-10 2018-07-12 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US20170358511A1 (en) 2016-06-10 2017-12-14 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10103080B2 (en) 2016-06-10 2018-10-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US10262915B2 (en) 2016-06-10 2019-04-16 Qorvo Us, Inc. Thermally enhanced semiconductor package with thermal additive and process for making the same
US20180019184A1 (en) 2016-07-18 2018-01-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10079196B2 (en) 2016-07-18 2018-09-18 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10468329B2 (en) 2016-07-18 2019-11-05 Qorvo Us, Inc. Thermally enhanced semiconductor package having field effect transistors with back-gate feature
US10109550B2 (en) 2016-08-12 2018-10-23 Qorvo Us, Inc. Wafer-level package with enhanced performance
US20180044177A1 (en) 2016-08-12 2018-02-15 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10486963B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10486965B2 (en) 2016-08-12 2019-11-26 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10804179B2 (en) 2016-08-12 2020-10-13 Qorvo Us, Inc. Wafer-level package with enhanced performance
US10109502B2 (en) 2016-09-12 2018-10-23 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10985033B2 (en) 2016-09-12 2021-04-20 Qorvo Us, Inc. Semiconductor package with reduced parasitic coupling effects and process for making the same
US10090339B2 (en) 2016-10-21 2018-10-02 Qorvo Us, Inc. Radio frequency (RF) switch
US9953931B1 (en) * 2016-10-25 2018-04-24 Advanced Semiconductor Engineering, Inc Semiconductor device package and a method of manufacturing the same
US10749518B2 (en) 2016-11-18 2020-08-18 Qorvo Us, Inc. Stacked field-effect transistor switch
US10068831B2 (en) 2016-12-09 2018-09-04 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US20180342439A1 (en) 2016-12-09 2018-11-29 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10790216B2 (en) 2016-12-09 2020-09-29 Qorvo Us, Inc. Thermally enhanced semiconductor package and process for making the same
US10490471B2 (en) 2017-07-06 2019-11-26 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10755992B2 (en) 2017-07-06 2020-08-25 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US20190013255A1 (en) 2017-07-06 2019-01-10 Qorvo Us, Inc. Wafer-level packaging for enhanced performance
US10366972B2 (en) 2017-09-05 2019-07-30 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US10784233B2 (en) * 2017-09-05 2020-09-22 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US20190074271A1 (en) 2017-09-05 2019-03-07 Qorvo Us, Inc. Microelectronics package with self-aligned stacked-die assembly
US11152363B2 (en) 2018-03-28 2021-10-19 Qorvo Us, Inc. Bulk CMOS devices with enhanced performance and methods of forming the same utilizing bulk CMOS process
US12062700B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12062701B2 (en) 2018-04-04 2024-08-13 Qorvo Us, Inc. Gallium-nitride-based module with enhanced electrical performance and process for making the same
US12125739B2 (en) 2018-04-20 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US12046505B2 (en) 2018-04-20 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same utilizing localized SOI formation
US20190333875A1 (en) * 2018-04-27 2019-10-31 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated inductor and manufacturing method thereof
US11380632B2 (en) * 2018-04-27 2022-07-05 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor package device with integrated inductor and manufacturing method thereof
US10553563B2 (en) * 2018-05-30 2020-02-04 Epistar Corporation Electronic device
US11063021B2 (en) 2018-06-11 2021-07-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US10804246B2 (en) 2018-06-11 2020-10-13 Qorvo Us, Inc. Microelectronics package with vertically stacked dies
US12046535B2 (en) 2018-07-02 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12165951B2 (en) 2018-07-02 2024-12-10 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US10964554B2 (en) 2018-10-10 2021-03-30 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US11069590B2 (en) 2018-10-10 2021-07-20 Qorvo Us, Inc. Wafer-level fan-out package with enhanced performance
US20210296199A1 (en) 2018-11-29 2021-09-23 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11646242B2 (en) 2018-11-29 2023-05-09 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US11942389B2 (en) 2018-11-29 2024-03-26 Qorvo Us, Inc. Thermally enhanced semiconductor package with at least one heat extractor and process for making the same
US20220139862A1 (en) 2019-01-23 2022-05-05 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US20200235054A1 (en) 2019-01-23 2020-07-23 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US11923313B2 (en) 2019-01-23 2024-03-05 Qorvo Us, Inc. RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same
US12368056B2 (en) 2019-01-23 2025-07-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11387157B2 (en) 2019-01-23 2022-07-12 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046570B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12046483B2 (en) 2019-01-23 2024-07-23 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12057374B2 (en) 2019-01-23 2024-08-06 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US20220108938A1 (en) 2019-01-23 2022-04-07 Qorvo Us, Inc. Rf devices with enhanced performance and methods of forming the same
US12062623B2 (en) 2019-01-23 2024-08-13 Qorvo Us, Inc. RF device without silicon handle substrate for enhanced thermal and electrical performance and methods of forming the same
US11961813B2 (en) 2019-01-23 2024-04-16 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12125825B2 (en) 2019-01-23 2024-10-22 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12112999B2 (en) 2019-01-23 2024-10-08 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US12132074B2 (en) * 2019-03-14 2024-10-29 Taiwan Semiconductor Manufacturing Company, Ltd. Package
US11018215B2 (en) * 2019-03-14 2021-05-25 Taiwan Semiconductor Manufacturing Company, Ltd. Package and manufacturing method thereof
US12074086B2 (en) 2019-11-01 2024-08-27 Qorvo Us, Inc. RF devices with nanotube particles for enhanced performance and methods of forming the same
US11646289B2 (en) 2019-12-02 2023-05-09 Qorvo Us, Inc. RF devices with enhanced performance and methods of forming the same
US11923238B2 (en) 2019-12-12 2024-03-05 Qorvo Us, Inc. Method of forming RF devices with enhanced performance including attaching a wafer to a support carrier by a bonding technique without any polymer adhesive
US12129168B2 (en) 2019-12-23 2024-10-29 Qorvo Us, Inc. Microelectronics package with vertically stacked MEMS device and controller device
US12482731B2 (en) 2020-12-11 2025-11-25 Qorvo Us, Inc. Multi-level 3D stacked package and methods of forming the same
US12062571B2 (en) 2021-03-05 2024-08-13 Qorvo Us, Inc. Selective etching process for SiGe and doped epitaxial silicon

Also Published As

Publication number Publication date
JP2004273938A (ja) 2004-09-30
US20040178508A1 (en) 2004-09-16
JP3917946B2 (ja) 2007-05-23

Similar Documents

Publication Publication Date Title
US7049692B2 (en) Stacked semiconductor device
US6828665B2 (en) Module device of stacked semiconductor packages and method for fabricating the same
US6812567B2 (en) Semiconductor package and package stack made thereof
US9449941B2 (en) Connecting function chips to a package to form package-on-package
KR100430861B1 (ko) 배선기판, 반도체장치 및 패키지 스택 반도체장치
US6252298B1 (en) Semiconductor chip package using flexible circuit board with central opening
US7435680B2 (en) Method of manufacturing a circuit substrate and method of manufacturing an electronic parts packaging structure
US8030135B2 (en) Methods for a multiple die integrated circuit package
US7514297B2 (en) Methods for a multiple die integrated circuit package
US7312405B2 (en) Module structure having embedded chips
US20090310322A1 (en) Semiconductor Package
JPH1098130A (ja) チップスケールの半導体パッケージ及びその製造方法
KR20060079754A (ko) 반도체 패키지용 칩 패드가 라우트된 리드 프레임
US8008765B2 (en) Semiconductor package having adhesive layer and method of manufacturing the same
KR20020061812A (ko) 볼 그리드 어레이형 멀티 칩 패키지와 적층 패키지
KR100711675B1 (ko) 반도체 장치 및 그 제조 방법
US10741499B2 (en) System-level packaging structures
US20060055018A1 (en) Semiconductor device
US7276800B2 (en) Carrying structure of electronic components
US20050023659A1 (en) Semiconductor chip package and stacked module having a functional part and packaging part arranged on a common plane
EP1093165A1 (en) Integrated circuit assembly
EP1848029B1 (en) Carrying structure of electronic components
US20250233100A1 (en) Semiconductor package
US20020043702A1 (en) Semiconductor package comprising substrate with mounting leads and manufacturing method therefor
US8026615B2 (en) IC package reducing wiring layers on substrate and its carrier

Legal Events

Date Code Title Description
AS Assignment

Owner name: FUJITSU LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNORS:NISHIMURA, TAKAO;AIBA, KAZUYUKI;TAKASHIMA, AKIRA;REEL/FRAME:014923/0869

Effective date: 20040114

STCF Information on status: patent grant

Free format text: PATENTED CASE

AS Assignment

Owner name: FUJITSU MICROELECTRONICS LIMITED, JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089

Effective date: 20081104

Owner name: FUJITSU MICROELECTRONICS LIMITED,JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU LIMITED;REEL/FRAME:021976/0089

Effective date: 20081104

FPAY Fee payment

Year of fee payment: 4

AS Assignment

Owner name: FUJITSU SEMICONDUCTOR LIMITED, JAPAN

Free format text: CHANGE OF NAME;ASSIGNOR:FUJITSU MICROELECTRONICS LIMITED;REEL/FRAME:024651/0744

Effective date: 20100401

FPAY Fee payment

Year of fee payment: 8

AS Assignment

Owner name: SOCIONEXT INC., JAPAN

Free format text: ASSIGNMENT OF ASSIGNORS INTEREST;ASSIGNOR:FUJITSU SEMICONDUCTOR LIMITED;REEL/FRAME:035508/0469

Effective date: 20150302

MAFP Maintenance fee payment

Free format text: PAYMENT OF MAINTENANCE FEE, 12TH YEAR, LARGE ENTITY (ORIGINAL EVENT CODE: M1553)

Year of fee payment: 12