JP2633647B2 - Protective relay - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial application field) The present invention relates to a digital protection relay device, particularly to a protection relay device realized by a counter by a program.

(Prior Art) A technique of applying a microcomputer to a protective relay device for protecting a power system is well known. Today, with the increase in the size of the power system, the increase in system protection equipment has become a problem. As one solution to this problem, it is possible to determine failures for a large number of protection targets and to use protection devices. There are digital protection relays that can be made smaller.

Generally, in a protective relay device, in addition to a relay element for protecting a system, a timer for outputting a trip command (so-called trip sequence timer) for maintaining various kinds of coordination by using these relay element outputs as input, , A timer (so-called constant monitoring timer) for discriminating between system accidents and monitoring failures and preventing unnecessary monitoring failures,
A large number of timers such as a timer for controlling automatic inspection and determining a defect (a so-called inspection timer) are stored.

In a conventional analog relay, these timers are generally configured by passive elements such as resistors and capacitors and active elements such as transistors. A typical timer is a time limit timer (time delay timer), and it can be said that most of the timers housed in the protection relay device are also time limit timers. Here, the time limit timer is roughly classified into an on-delay timer (time-limited operation type) and an off-delay timer (time-limited return type). The former is, after the input changes to 0 → 1, the output has a timer after a predetermined time T _D, the latter, after the input changes to 1 → 0, a timer after the output is lost a certain time T _D. When using such a timer, depending on the time T _D of the above are set, delay function is by charging phenomenon and discharge phenomenon former components, characteristics of the device changes and the circuit configuration and the like Causes the delay time to vary for the same set value T _D. If the time error in this case is expressed as ± ε, the actual delay time is
T _D ± ε. In the error class of the timed timer defined by JEC-174E, for example, the class 2.5 is set to ± 2.5% and the class 5 is set to ± 5%. On the negative side, errors are allowed within the same range.

On the other hand, in the case of a digital protection relay, functions such as a trip sequence, constant monitoring, and automatic inspection are almost realized by software, and the above-mentioned delay timer is mostly realized by counting by a program. I have. This method is also called the counting method, and the RAM
When a predetermined address or the content of the register is updated and reaches a predetermined value, it is determined that there is a timer output. The value being updated corresponds to the count value described above,
Further, the timer set value T _D is compared with the count value is readily converted to a form, memory for stored as a predetermined value of said. The timer error generated in this case is an error generated by counting at a fixed cycle, and its magnitude is determined by the counting cycle.

FIG. 6 is a diagram showing a configuration example of a conventional digital protection relay device, which will be described below. As shown in FIG. 6, the digital protection relay includes an analog-to-digital conversion unit 1, a digital operation processing unit 2, a settling unit 3, and an input / output interface 4 (hereinafter referred to as I / O) with the outside. , Bus 5
It is composed of The units 1 to 4 are interconnected via a bus 5.

The analog-to-digital conversion unit 1 includes analog filters 1-11 to 1-1n and sampling and holding units 1-21 to 1-1-1.
2n (hereinafter, referred to as S / H), a multiplexer 1-3, and an analog / digital converter 1-4 (hereinafter, referred to as an A / D converter). N (n> 1) analog information A-1 to be protected
An is input, and the analog information is stored in S / H1-21 to
It is held at a predetermined sampling interval by 1-2n. The held signal is the multiplexer 1-3, A / D
It is converted to a digital quantity via the converter 1-4. These pieces of digital information are sequentially transferred to the RAM 2-2, and are used for a relay determination operation.

On the other hand, the digital arithmetic processing unit 2 includes a CPU 2-1 and a RAM 2-
2. The CPU 2-1 performs various processes, such as a relay determination operation, according to a program read from the RAM 2-3.

The setting section 3 has a function of setting the relay sensitivity and the trip sequence timer set values SK-1 to SK-n. Generally, the settled value is stored in a non-volatile memory, and is read out and used at any time according to the program.

I / O4 takes in external controller such as CB information, relay operation,
This is an interface for outputting a return output, a trip command, etc. to an external device.

FIG. 7 shows an example of a trip sequence realized by the above configuration. In addition to the trip sequence, the protective relay has functions such as constant monitoring and automatic inspection.
Since the timers according to the present invention are similar to each other, a method for realizing the timer and problems will be described below by limiting the timer to a trip sequence. FIG. 7 shows a trip sequence of a general distance relay. The output of the second-stage distance relay 44SX2 P-1 is an on-delay timer 44S.
The 51D P-3 which drives the T2 P-2 and also acts as a fail-safe for the 44SX2 is an off-delay timer 51DT P
-4 is driven. The trip command P-5 is output on condition that 51DT is output after the 44ST2 time limit.

FIG. 8 shows a program flow when this is realized by a program stored in the ROM of the digital protection relay. First, when the CPU is initialized and the program starts, the input data fetch S1 is started by a CPU interrupt signal generated after the analog-to-digital conversion, and the digital amount is fetched into the RAM. Next, in S2, a trip sequence process including a relay operation and a timer process is performed by a time division process. Regarding the software configuration of the digital protection relay, for example,
Although described in Vol. 41, No. 4, “Digital Relay,” page 33, etc., in general, in order to process a plurality of relay elements by one CPU, a configuration in which a plurality of relay elements are time-divisionally processed over a plurality of samplings is used. Has been taken. In this example, 1
A plurality of relay calculations and trip sequence processing are performed in the time division processing of m through m.

For example, in S2-1, the processing related to 44SX2, that is, the relay calculation of 44SX2 and the timer processing of 44ST2, are performed.
In step 2, 51D-related processing, ie, 51D relay operation and 51DT
Is performed. Generally, in a digital protection relay that is put into practical use, one sample interval is an electrical angle of 30 °, that is, a value obtained by equally dividing one cycle into twelve.
1 / 600Hz ≒ 1.67ms for 50Hz system, 1 for 60Hz system
/720Hz≒1.39ms. Therefore, it can be said that the processing of S2-1 and S2-2 has a time difference of 1.67 ms or 1.39 ms. Hereinafter, other relay element processes from S2-3 to S2-m are performed in the same manner. Therefore, the same processing S2-X (X = 1)
To m) are performed at intervals of mT intervals, where T is one sampling interval and m is the number of time divisions.

At S3, the presence / absence of the trip command output is determined by combining the timer outputs processed at S2 step. For example, if both 44ST2 output and 51DT output are ON, there is a trip command.
Output to / O. In S4, processing other than the above protection function, that is, monitoring / inspection processing is performed. Here, for the sake of convenience, the time division processing is not described, but generally, the time division processing is performed. In S5, the standby state having the interrupt signal to the next CPU is continued, and when an interrupt signal is generated, that is, at the start of the next sampling, the process returns to S1 to take in new data. Hereinafter, similarly, the program is executed from S1.

FIG. 9 shows the allocation of the S2 step in the case of 12 samplings in one cycle. Here, the number of time divisions is m = 6. Therefore, each of the same processes is performed at 6 × T
Every hour.

Next, for details of timer processing, 44SX related processing
Taking S2-1 as an example, FIG.
This will be described with reference to the drawings. First, in S2-1-1, the timer set value T _D of 44ST2 is read. T _D is converted to the same dimension as the count value by the following equation in order to compare it with the counter value n counted during 44SX2 operation.

T _D ÷ mT = C _D + C _ε (1) where C _D is a quotient of division (an integer that is C _D 0), and C _ε is a remainder (0C _ε <1). The counter value n is 0 → 1
Integers are calculated as → 2, and integer values are sufficient for comparison. In addition, when handling with a microcomputer, integer values are easier to process. in apparatus, the C _D, used as a value converted to the counter dimension of the timer setting value T _D. That, C _epsilon is truncated, T _D as _{÷ mT ≒ C D ... (2} ), sets the counter comparison value C _D at S2-1-1.

In S2-1-2, the relay operation of 44SX2 is performed. As is well known, the relay characteristics are realized by variously combining sampling data taken in S1. S2-1
In -3, the operation result of 44SX2 is checked.
At -4, the counter n is incremented by 1 to count up. If not operating, the counter n is reset to 0. S2
In -1-6, counter value n, when a comparison value C _D above, determines that 44ST2 output Yes in S2-1-7, also terminated by clamping the counter n to C _D. n is less than C _D, ends as 44ST2 output no.

(Problems to be Solved by the Invention) As is clear from the above, in this processing, the timer setting value
T _D with respect occurs an error represented by the following formula.

_{ε = n × mT-T D} = C D mT- (C D + C ε) mT = -C ε mT ... (3) Since this case is _0C ε <1, an error occurs at a range of -mt <.epsilon.0 become. This is shown in FIG.
In FIG. 11, the counter value n
There started counting up when it reaches the comparison value C _D, 44ST
It shows that the output of 2 becomes positive. Even after 44ST2 output,
If 44SX2 operates, but the n as dotted will count up, as described above, in fact it is clamped to C _D. Here, T is one sampling interval,
Since this processing is performed once every m times, n is counted up by +1 every mT time. From the figure, for the set value T _D ,
An error of ε time occurs. That is, ε earlier than the set value T _D , 44
The output of ST2 will be output. This is a fundamental error that occurs due to counting up every mT.
When showing the relationship between the operation time T _C and setpoint T _D, it is shown in Figure 12. T _C is all distributed below the true value.

In the above example, although the operation in nC _D, n> C _D i.e., n
There When operation if it exceeds _{C D, T C = (C} D +1) is mT, = n × error epsilon is _{ε mT-T D = (C} D +1) mT - (C D + C ε) mT = (1-Cε) mT ... ( 4) next, since it is 0C _epsilon <1, error occurs in the range of 0ε <mT. Therefore, in the example of FIG. 12, the operating value T _C is distributed upward (in a longer direction) with respect to the true value T _D. The absolute value of the error is the same as in (3), and an error of | mT |

As described above, in the timer that counts in the period of mT, an error of a maximum size of | mT | occurs.
This is because the value of C _{ε in the} equation is ignored in the counting method. That is, it can be said that the C _epsilon contains error information determined by T _d and mT.

 The description will be given below with actual numerical values.

44ST2 Set value T _D = 45 ms, number of time divisions m = 12, 1 sampling interval T = 1.39 ms Substituting the above into equation (1), T _D ÷ mT = 45 ms ÷ 12 × 1.39 ms = 2.7 = 2 + 0.7 C _D = 2 and Cε = 0.7.

(3) Substituting above formula, the ε = -C ε mT ≒ _-11.68ms.

Therefore, the trip command is output 11.68 ms earlier. This is a 26% error (11.6
7ms ÷ 45ms = 0.26). Further, depending on the set value, there is a possibility that an error of up to 11.67 ms may occur as described above. This poses a problem in the protection function when considering that the various timers of the relay device are set in cooperation with the timers of the own device and the other device in units of several tens of ms. That is, if a theoretically conceivable error is large, the timer must be settled in consideration of cooperation with a margin for the error. As a result, the timer setting is prolonged, the trip time is extended, and the system operation may be seriously hindered. If the number m of time divisions is reduced, the error is proportionally reduced, but the processing load on the CPU is increased accordingly, and a disadvantage arises in that it is impossible to store a large number of relay elements.

The present invention has been made in order to solve the above problems, and has a smaller value of the error ε caused by the above-described principle, and is capable of realizing a highly accurate timer. It is intended to provide.

[Structure of the Invention] (Means for Solving the Problems) FIG. 1 is a functional block diagram showing a basic concept of the present invention, and the present invention is based on a setting area set in a setting section 3 or a ROM 2-3 in advance. a timer setting value is read, a timer set value setting section 11 to be converted into a manageable form by a microprocessor, time division processing number m, 1 sampling interval T, the timer error information obtained by the timer set value T _D A counter comparison value setting means 12 for controlling the value of the counter comparison value, a counting means 13 for checking the state of occurrence of an event which causes a timer to start, and updating the counter when an event occurs, an updated counter and the counter And a counter comparison / judgment means for outputting a timer output based on the result of comparison with the comparison value. In addition,
Here, the timer error information is defined as C _ε =
Means (TD / mT) -C _D.

(Operation) First, the timer setting value is set by the timer setting value setting means 11.
And converted into an appropriate form. On this occasion,
A measure for reducing the timer error is performed by the counter comparison value setting means 12, and a timer output is output at an appropriate time after the occurrence of an event to start the timer.

(Example) Hereinafter, an example is described with reference to drawings.

Since the hardware configuration of the digital protection relay according to the present invention is the same as that of FIG. 6 described as a conventional example,
Description is omitted. FIG. 2 shows a flowchart of a program for realizing the functions of the present invention. This program corresponds to S2-1, S2-2, and the like in FIG. 8 shown as a conventional example, and is started and executed once every cycle mT. Although the present example is an example of the on-delay timer processing, the case of the off-delay timer can be similarly considered.

First, read from the settling area S2X-1-1 In the timer setting value T _D is set in advance in the settling unit 3, or ROM2-3. T _D is converted in the same manner as in the above equation (1) to obtain a counter comparison value C _D and timer error information _Cε . This step corresponds to the means 11 in FIG.

In S2X-1-2, the occurrence of an event that is a factor for starting the timer is checked. The occurrence of an event corresponds to the operation of a relay element, the occurrence of a monitoring failure, or the like. When an event occurs, S2X
The counter n is updated by -1-3. If no event has occurred, the counter n is reset in S2X-1-4. This step corresponds to the means 13 in FIG.

Next, S2X-1-5 and S2X-1-6 will be described. This portion is a feature of the present invention and corresponds to the means 12 in FIG. First, in S2X-1-5, compares the timer error information C _epsilon shown in the above (1) to a predetermined value k. C _ε is
(1) As expressions clear, 0C _epsilon <1, by the following equation, and controls the value of the counter comparison value CD.

_C ε <k → C _D No change _{(5-a) C ε k} → C D = C D +1 (5-b) (5-b) expression is equivalent to S2X-1-6. Where 0
<K <1.

Next, comparison between the C _D and the counter value n obtained by the above process is performed by S2X-1-7, NCD if, S2X
And a timer output Yes at -1-8, also, n as n ← C _D
Is clamped. the timer output-free at n <C _D if S2X-1-9. The processing is completed as described above, and after the mT cycle,
This processing is started again, and the processing is repeated in the same manner.

The reason why the timer error is smaller in the above-described processing than in the conventional apparatus under the condition control of the expression (5) will be described.

According to the present invention, the range of error ε = n × mT-T _D is as follows.

0C _epsilon <For _{k ε = C D × mT- (} C D + C ε) mT = -C ε mT ∴-kmT <ε0 (6-a) kC ε <1 if _{ε = (C D +1) mT-} ( C _D + C _ε ) mT = (1−C _ε ) mT∴0 <ε (1-k) mT (6-b) When (6-a) and (6-b) are combined, −kmT <ε (1 −k) mT (6-c) If the timer error of the conventional device is the maximum mT, 0 <k <
Since it is 1, it can be seen that the error is clearly reduced.

FIGS. 3 and 4 show the state of ε when k = 0.5.

According to the equation (6-c) when k = 0.5, And the error is reduced by 50% as compared with the conventional device.

FIG. 3 shows that when the output is ε earlier than the set value T _D ,
To Fig. 4 setpoint T _D, shows the case where there ε slow output. In each case, The error is distributed at ε.

When showing the relationship between the operation time T _C and setpoint T _D, FIG. 5 (a)
become that way. T _C is distributed above and below the true value (a).

According to the above numerical example, T _D = 45 ms, m = 12, T = 1.39
If k = 0.5 in ms, then C _ε 0.7> 0.5, so from equation (6-b), ε = (1−Cε) mT = 5.0 ms (8) Therefore, the error of the conventional device becomes −11.67 ms → 5.0 ms. , Timer error is greatly improved.

FIG. 5B compares the timer error (A) generated by the conventional device with the timer error (A) generated by the present invention. The shaded area in the figure is the range where the improvement is obtained, and indicates that the improvement effect increases as the period mT increases.

As described above, the means shown in FIG. 2 makes it possible to greatly reduce the timer error of the method of counting by a program, and realizes a highly accurate timer. Thereby, the timer setting becomes easy, and a highly reliable holding relay device can be provided.

In the above embodiment, n (an integer of n0) is used as the counter value, but the effect is the same even if a value n × mT multiplied by the period mT is used. In this case, the timer error information is C _ε
× is mT, the counter comparison value is C _D × mT. The above (5
-A) (as 5-b) and equivalent control, Cε × mT <k × mT → CD × mT no change (9-a) Cε × mT > k × mT → CD × mT = C D × mT + mT (9-b). Counter comparison determination, since it is _{n × mT-C D × mT0} , resulting error becomes equal to (6-a), (6 -b).

Further, in the first embodiment, it is dealing with counter comparison value as an integer C _D, the same effect even in real value can be expected. In other words, when dealing with real counter comparison value without truncating the C _epsilon, performs counter comparison value control and count comparison decision by the following Although the above description has been limited to the on-delay timer of the trip sequence, the off-delay timer of the trip sequence, the constant monitoring timer, the automatic inspection timer,
The same effect can be expected regardless of whether the set value of the timer is variable or fixed.

[Effects of the Invention] As described above, according to the present invention, the error information determined by the timer count period and the timer set value provides:
Because the timer count comparison value is controlled,
Compared with the conventional device, it is possible to obtain a highly accurate timer in which the error is greatly reduced and the error is distributed uniformly above and below the true value. This makes it possible to provide a digital type protection relay having excellent reliability.

[Brief description of the drawings]

FIG. 1 is a functional block diagram showing a basic concept of a digital protection relay device according to the present invention, FIG. 2 is a flowchart showing processing contents, and FIG. 3 is a timer error when an output comes out earlier than a set value. FIG. 4 is a diagram showing a mode of occurrence of a timer error when an output comes out later than the set value, FIG. 5 is a diagram showing a reduction effect of the timer error, and FIG. FIG. 7 is an example diagram of a sequence timer, FIG. 8 is a flowchart showing processing contents of the conventional device, FIG. 9 is a diagram for explaining sampling processing, FIG. Is a flowchart showing a specific example of timer processing, FIG. 11 is a diagram showing a mode of occurrence of a timer error when an output comes out earlier than a set value, and FIG. 12 is a case where an output comes out later than the set value. Of timer error Is a diagram showing the appearance. 10 Digital protection relay 11 Timer setting value setting means 12 Counter comparison value setting means 13 Counting means 14 Count comparison judging means

Claims (1)

(57) [Claims] An analog electric quantity from a protected object is sampled and held at a predetermined timing, and a protection operation is performed based on digital data obtained by converting the held analog quantity into a digital quantity. In the protective relay device, counting means for realizing a timer using a counter counted at a counting cycle that is a cycle of a predetermined multiple of the sampling interval, timer setting value setting means for setting a timer setting value, When the value of the timer error information obtained from the remainder obtained by dividing the timer setting value of the timer setting value by the counting cycle of the counting means is larger than a predetermined value, the timer setting value of the timer setting value setting means is counted by the counting means. The counter ratio that counts up the counter comparison value obtained from the quotient of the division divided by the counting cycle of 1. Protection comprising: a value setting unit; and a count comparison determining unit that compares a counter value of the counting unit with a counter comparison value of the counter comparison value setting unit and derives a timer output based on the comparison result. Relay device.