JP2640973B2 - Semiconductor element connection structure - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a connection structure of a semiconductor device.

(Prior Art) FIG. 3 shows a schematic structure of a conventional flip chip connection of a semiconductor element. 1 is a semiconductor element, 2 is a wiring board, 3 is a solder bump, 4 is an electrode provided on each of the semiconductor element 1 and the wiring board 2, and AA 'indicates the center of the semiconductor element.

In flip-chip connection, electrical connection between the semiconductor element 1 and the electrode 4 of the wiring board 2 can be performed by batch connection in which the solder bumps 3 are heated and melted, so that workability is superior to that of the wire bonding method. Also, wire bonding method and
Unlike the TAB (Tape Automated Bonding) method, the arrangement of electrodes is not limited to the periphery of the semiconductor element, so that the number of connection terminals can be greatly increased.

However, in this connection structure, as shown in FIG. 4, when a temperature change occurs, a dimensional deviation B occurs due to a difference in a thermal expansion coefficient between the semiconductor element 1 and the wiring board 2, and shear distortion occurs in the solder bump 3. Connection reliability decreases.

Since the shear strain increases with an increase in the center distance between the solder bump 3 and the semiconductor element 1, the area where the solder bump 3 can be arranged is limited due to the allowable shear strain of the solder bump 3, and the number of terminals and the area of the large area are increased. It has been difficult to apply it to semiconductor devices.

As a means for reducing the shear distortion of the solder bumps, a method using a wiring board material having a thermal expansion coefficient close to that of the semiconductor element can be considered, but there is a disadvantage that the wiring board material is limited.

On the other hand, a method has been proposed in which a solder bump supported by a polyimide film is overlaid to form a multistage bump to reduce shear distortion (Japanese Patent Publication No. Sho 62-29370).

However, the above-mentioned method has a drawback that the number of necessary members increases and the number of connection steps increases due to the stacking of solder bumps.

FIG. 5 shows a semiconductor element connection structure in which metal bumps are brought into contact with each other by pressure to obtain electrical connection. In Figure 5,
Metal bumps 13 are formed on the respective electrodes 4 of the semiconductor element 1 and the wiring board 2. Pressure is applied to the metal bumps 13 due to the contraction force of the resin 5 at the time of curing, and the metal bumps 13 are pressed.
13 contact each other mechanically, and an electrical connection is obtained.

However, in this connection structure, there are portions where the height of the metal bumps 13 varies and electrical connection cannot be obtained.
In addition, since the coefficient of thermal expansion of the resin 5 is larger than that of the metal bump 13, the pressure is weakened when a temperature change occurs,
However, there has been a problem that connection reliability is lacking because the contact becomes unstable.

(Problems to be Solved by the Invention) The present invention provides an electric resistance against a large shear strain generated between the semiconductor element and the wiring board described above, a variation in bump height, and a pressure fluctuation due to a thermal expansion coefficient of a resin. It is an object of the present invention to provide an inexpensive semiconductor element connection structure having high connection reliability and capable of fine connection.

(Means for Solving the Problem, Function) The present invention is a semiconductor element connection structure proposed to solve the above-mentioned problem, wherein a semiconductor is obtained in which a superelastic material is interposed and a bump is pressed or connected to the bump. This is an element connection structure.

In the conventional flip chip connection method, due to thermal strain,
Strain concentrates on the solder bumps, and often shear fractures occur at the bumps. Conventionally, a Pb-Sn solder has been mainly used as the bump member, and plastic deformation is repeatedly superimposed on that portion due to thermal deformation, and reaches a critical strain for destruction and breaks.

The present invention aims to prevent breakage by using a superelastic material as a material of the portion subjected to the thermal strain and repeating deformation within an elastic range even with repeated strain. As this superelastic material, for example, Ni-Ti, C
u-Al-Ni, Au-Cd, Ag-Cd, Cu-Zn-Al, Cu-Sn, Fe-Pt, F
e-Pd, In-Tl, Ni-Al, etc. are used, and have an elastic deformation of 0.5
It is desirable to use a superelastic body showing an elongation of not less than%.
As a method of forming this super elastic body on the bump, plating,
Evaporation or the like is used.

Two bonding methods are used as a semiconductor element mounting structure using the bumps.

One is a method in which a semiconductor IC and a wiring board are joined by pressing force using resin curing or the like via bumps.

The other is a method in which both are integrated by melting or the like via bumps and joined. As a joining method, a method of melting the bump itself or forming a solder layer or the like on the superelastic bump by vapor deposition or the like, and melting and joining the bump and the like may be employed.

The required amount of elastic deformation varies depending on the type, dimensions, temperature difference, etc. of the semiconductor IC and the substrate material.
% Is preferable.

By using a superelastic material for the bump, it was possible to flexibly cope with a large shear strain due to a difference in thermal expansion, and a highly reliable flip chip connection became possible.

 Hereinafter, an embodiment will be described.

(Example) Example 1 As a superelastic material, 50.5 at% Ni-Ti (elastic elongation 8
%), Flip-chip connection was performed as shown in the explanatory view of FIG.

That is, as shown in FIG.
The bump 3 of the super elastic body of Ti is formed by plating or evaporation.
It is formed on the electrode pad 4 of the semiconductor IC1.

The IC with bumps is positioned on the electrodes of the substrate, and the ultraviolet curable resin 5 flows as shown in FIG.

Next, as shown in FIG. 1 (c), the resin is cured by irradiating ultraviolet rays 6 while applying a force so that all the bumps contact the substrate electrode.

At this time, the pressing force is such that all bumps contact the electrodes of the substrate,
In addition, the deformation of the superelastic bump is adjusted to be within the elastic range.

With such a structure, no disconnection was observed even when the temperature cycle of 0 to 150 ° C. was repeated 1,000 times.

Example 2 As a superelastic material, flip-chip connection was performed using Cu-14 wt% Al-4 wt% Ni (elastic elongation: 7%) as shown in FIG.

That is, as shown in FIG.
The semiconductor I is formed by vapor deposition of a superelastic bump 3 of 4 wt% Ni.
It is formed on C1 and the electrode pad 4 of the substrate 2.

A low melting point solder layer 7 and the like are formed on these bumps by vapor deposition or the like, the IC and the substrate are aligned, and the bumps are brought into contact with each other as shown in FIG.

This is put into a reflow furnace as shown in FIG. 3 (c), and the solder layer portions are melt-bonded and integrated.

With such a structure, no disconnection was observed even when the temperature cycle of 0 to 150 ° C. was repeated 1000 times.

(Effect of the Invention) By connecting the semiconductor IC and the electrode of the substrate by the above-described method, a highly reliable flip-chip connection with respect to breakage due to thermal strain has been made possible.

[Brief description of the drawings]

FIG. 1 is an explanatory view of a semiconductor element connection structure for obtaining an electrical connection by applying pressure. FIG. 2 is an explanatory view of a semiconductor element connection structure for obtaining electrical connection by bonding. FIG. 3 shows a general flip chip bonding, and FIG. 4 is a view showing a state in which the bump of FIG. 3 is deformed due to thermal strain. FIG. 5 is an explanatory diagram of a state in which a metal bump is pressed to obtain an electrical connection. 1 ... Semiconductor IC, 2 ... Substrate, 3 ... Bump material, 4 ...
Electrode pads, 5: resin, 6: ultraviolet light, 7: low melting point solder, 13: metal bump material.

 ──────────────────────────────────────────────────続 き Continued on the front page (72) Inventor Keisuke Watanabe 1-7-12 Toranomon, Minato-ku, Tokyo Inside Oki Electric Industry Co., Ltd. (72) Inventor Yasuo Iguchi 1-7-12 Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Takashi Kanamori 1-7-12 Toranomon, Minato-ku, Tokyo 1-7 Oki Electric Industry Co., Ltd. (72) Inventor Yoshio Ozeki 1618 Ida, Nakahara-ku, Kawasaki City, Kanagawa Prefecture New Japan (1) Technical Research Institute No. 1 of Research Institute of Steel Corporation (56) Reference

Claims (3)

(57) [Claims] 1. A semiconductor element connection structure in which an electrical connection is formed with a superelastic material interposed. 2. The semiconductor element connection structure according to claim 1, wherein the connection is obtained by applying pressure. 3. The semiconductor element connection structure according to claim 1, wherein the connection is obtained by bonding.