JP2709496B2 - Semiconductor element connection structure - Google Patents
Semiconductor element connection structureInfo
- Publication number
- JP2709496B2 JP2709496B2 JP1027302A JP2730289A JP2709496B2 JP 2709496 B2 JP2709496 B2 JP 2709496B2 JP 1027302 A JP1027302 A JP 1027302A JP 2730289 A JP2730289 A JP 2730289A JP 2709496 B2 JP2709496 B2 JP 2709496B2
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- connection
- bump
- superelastic
- connection structure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W74/00—Encapsulations, e.g. protective coatings
- H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
- H10W74/15—Encapsulations, e.g. protective coatings characterised by their shape or disposition on active surfaces of flip-chip devices, e.g. underfills
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
- H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 （産業上の利用分野） 本発明は半導体素子の接続構造に関するものである。Description: TECHNICAL FIELD The present invention relates to a connection structure of a semiconductor device.
（従来の技術） 従来の半導体素子のフリップチップ接続の概略構造を
第３図に示す。１は半導体素子,2は配線基板,3ははんだ
バンプ,4は半導体素子１と配線基板２のそれぞれに設け
られた電極であり、Ａ−Ａ′は半導体素子の中心を示し
ている。(Prior Art) FIG. 3 shows a schematic structure of a conventional flip chip connection of a semiconductor element. 1 is a semiconductor element, 2 is a wiring board, 3 is a solder bump, 4 is an electrode provided on each of the semiconductor element 1 and the wiring board 2, and AA 'indicates the center of the semiconductor element.
フリップチップ接続は、半導体素子１と配線基板２の
電極４との電気的接続を、はんだバンプ３を加熱溶融す
る一括接続で行えるので、ワイヤボンディング法に比べ
て作業性が優れている。又、ワイヤボンディング法及び
TAB（Tape Automated Bonding）法のように電極配置が
半導体素子の周辺に限定されないので、大幅に接続端子
数を増大できるという特徴をもっている。In flip-chip connection, electrical connection between the semiconductor element 1 and the electrode 4 of the wiring board 2 can be performed by batch connection in which the solder bumps 3 are heated and melted, so that workability is superior to that of the wire bonding method. Also, wire bonding method and
Unlike the TAB (Tape Automated Bonding) method, the arrangement of the electrodes is not limited to the periphery of the semiconductor element, so that the number of connection terminals can be greatly increased.
しかしながら、この接続構造では第４図に示すよう
に、温度変化が生じた場合半導体素子１と配線基板２と
の熱膨張係数の差による寸法ずれＢが発生し、はんだバ
ンプ３に剪断歪みを生じ接続信頼性が低下する。However, in this connection structure, as shown in FIG. 4, when a temperature change occurs, a dimensional deviation B occurs due to a difference in the coefficient of thermal expansion between the semiconductor element 1 and the wiring board 2, and a shear distortion occurs in the solder bump 3. Connection reliability decreases.
剪断歪みは、はんだバンプ３と半導体素子１との中心
距離の増加とともに増大するため、はんだバンプ３の許
容し得る剪断歪み量からはんだバンプ３を配置できる領
域が制限され、多端子化ならびに大面積の半導体素子へ
の適用が困難であった。Since the shear strain increases with an increase in the center distance between the solder bump 3 and the semiconductor element 1, the area where the solder bump 3 can be arranged is limited due to the allowable shear strain of the solder bump 3, and the number of terminals and the area are increased. Is difficult to apply to semiconductor devices.
このはんだバンプの剪断歪みを低減させる手段とし
て、半導体素子と熱膨張係数の近い配線基板材料を用い
る方法が考えられるが、配線基板材料が制限されてしま
うという欠点がある。As a means for reducing the shear strain of the solder bumps, a method using a wiring board material having a thermal expansion coefficient close to that of the semiconductor element can be considered, but there is a disadvantage that the wiring board material is limited.
一方、ポリイミドフィルムで支持したはんだバンプを
重ねて多段バンプを形成し、剪断歪みを低減する方法
（特開昭62−293730号公報）が提案されている。On the other hand, there has been proposed a method (Japanese Patent Laid-Open No. 62-293730) in which a multistage bump is formed by stacking solder bumps supported by a polyimide film to reduce shear distortion.
しかしながら、はんだバンプを積み重ねるため、必要
部材の増加、接続工数の増加に伴う価格上昇という欠点
がある。However, since the solder bumps are stacked, there are disadvantages in that the number of necessary members increases and the cost increases due to an increase in the number of connection steps.
又、第５図は金属バンプを圧力で当接させて電気的接
続を得る半導体素子接続構造である。第５図において、
半導体素子１と配線基板２のそれぞれの電極４上には金
属バンプ13が形成されている。この金属バンプ13には樹
脂５の硬化時の収縮力により圧力が加わり、金属バンプ
13同士が機械的に接続し電気的接続が得られる。FIG. 5 shows a semiconductor element connection structure in which metal bumps are brought into contact with each other by pressure to obtain electrical connection. In FIG.
Metal bumps 13 are formed on the respective electrodes 4 of the semiconductor element 1 and the wiring board 2. Pressure is applied to the metal bumps 13 due to the contraction force of the resin 5 at the time of curing, and the metal bumps 13 are pressed.
13 are mechanically connected to each other to obtain an electrical connection.
しかしながら、この接続構造では金属バンプ13の高さ
がバラツクと電気的接続が得られない箇所が生ずる。
又、樹脂５の熱膨張係数は金属バンプ13に比べて大きい
ため、温度変化が生じると圧力が弱まり、金属バンプ13
の接触が不安定になるので、接続信頼性に欠けるという
問題があった。However, in this connection structure, there are portions where the height of the metal bumps 13 varies and electrical connection cannot be obtained.
In addition, since the coefficient of thermal expansion of the resin 5 is larger than that of the metal bump 13, the pressure is weakened when a temperature change occurs,
However, there has been a problem that the connection reliability is poor because the contact of the wire becomes unstable.
（発明が解決しようとする課題） 本発明では、上記に述べた半導体素子と配線基板の間
に発生する大きな剪断歪み、バンプ高さのバラツキ及び
樹脂との熱膨張係数の差による圧力変動に対して電気的
接続の信頼性が高く、しかも微細接続が可能な安価な半
導体素子接続構造を提供するものである。(Problems to be Solved by the Invention) In the present invention, the above-described large shear strain generated between the semiconductor element and the wiring board, variation in bump height, and pressure fluctuation due to the difference in thermal expansion coefficient between the resin and the resin are considered. It is intended to provide an inexpensive semiconductor element connection structure having high electrical connection reliability and capable of fine connection.
（課題を解決するための手段） 本発明は、超弾性体材料を介在させて加圧により電気
的接続を得る半導体素子接続構造で、かつ接続部間を可
動構造としたことを特徴とする半導体素子接続構造であ
る。(Means for Solving the Problems) The present invention provides a semiconductor element connection structure in which a superelastic material is interposed to obtain an electrical connection by pressurization, and a movable structure is provided between connection portions. This is an element connection structure.
本発明では、前述の課題を解決するために、バンプ材
として超弾性体材料を用い、加圧によって電気的接続を
得る構造にしたものである。バンプ構造をした超弾性体
材料を加圧し、超弾性体材料の弾性変形能力によりバン
プ高さのバラツキを吸収し、かつ半導体素子と基板等の
熱膨張係数差によって生ずる剪断歪みに対しては、接続
部間可動構造として、歪みを吸収するので、安定な電気
的接続を得ることができる。In the present invention, in order to solve the above-mentioned problem, a structure is used in which a superelastic material is used as a bump material and an electrical connection is obtained by pressing. Pressing the superelastic material having the bump structure, absorbing the variation of the bump height by the elastic deformation ability of the superelastic material, and against the shear strain caused by the difference in thermal expansion coefficient between the semiconductor element and the substrate, Since the movable structure between the connection portions absorbs the strain, a stable electric connection can be obtained.
可動構造としては、超弾性体バンプ間に導電体のボー
ルを挿入したり、超弾性体バンプに摩擦係数の小さい導
電体をコーティングするなどの手段を採用すればよい。As the movable structure, means such as inserting a conductive ball between the superelastic bumps or coating the superelastic bump with a conductor having a small friction coefficient may be employed.
超弾性体材料としては、弾性変形が0.5％以上の金
属、例えばTi−Ni,Cu−Zn−Sn,Au−Cu−Zn,Ag−Cd,Au−
Cd,Fe−Pt,Fe−Pdなどを用いることが望ましい。As the superelastic material, a metal whose elastic deformation is 0.5% or more, for example, Ti-Ni, Cu-Zn-Sn, Au-Cu-Zn, Ag-Cd, Au-
It is desirable to use Cd, Fe-Pt, Fe-Pd, or the like.
（実施例） 次に本発明を実施例に基づいて説明する。(Examples) Next, the present invention will be described based on examples.
実施例１ 第１図（ａ），（ｂ）は本発明の接続部の断面構造を
示すものであり、半導体素子１の電極４に蒸着で形成さ
れたTi−50.5at％Niのバンプ構造の超弾性体６と、基板
２の電極４に形成されたバンプ構造の超弾性体６の間に
ニッケル及びタングステンの超弾性体６よりも硬質の導
電体ボール７を挿入して、硬化時の収縮率の大きな樹脂
を使用して加圧力を与える。このときバンプ構造の超弾
性体６は圧縮変形し、繰返しの熱歪みに対して弾性範囲
内で変形を繰返す。Example 1 FIGS. 1 (a) and 1 (b) show a cross-sectional structure of a connection portion according to the present invention, in which a bump structure of Ti-50.5at% Ni formed on an electrode 4 of a semiconductor element 1 by vapor deposition is shown. A conductive ball 7 harder than the nickel and tungsten superelastic body 6 is inserted between the superelastic body 6 and the superelastic body 6 having a bump structure formed on the electrode 4 of the substrate 2, and contracts during curing. A pressing force is applied by using a resin having a high rate. At this time, the superelastic body 6 having the bump structure undergoes compressive deformation, and repeatedly deforms within the elastic range with respect to repeated thermal strain.
また第１図（ｂ）に示す如く半導体素子１と基板２の
熱膨張係数差によって生ずる剪断歪みに対しては、バン
プ構造の超弾性体６間に挟まれたボール７が回転するこ
とにより超弾性体６同士の相対的動きに対応し追従する
ので、安定的な電気的接続を維持することができる。ボ
ールとしてニッケル，タングステンのいずれを使った場
合にも良好な電気的接続が得られた。As shown in FIG. 1 (b), the ball 7 sandwiched between the superelastic bodies 6 having a bump structure rotates against the shear strain caused by the difference in the thermal expansion coefficient between the semiconductor element 1 and the substrate 2. Since it follows and follows the relative movement of the elastic bodies 6, stable electrical connection can be maintained. Good electrical connection was obtained when using either nickel or tungsten as the ball.
実施例２ 第２図（ａ），（ｂ）は本発明の第２の実施例の接続
部の断面構造を示したもので、半導体素子１の電極４に
蒸着で形成したTi−50.5at％Niのバンプ構造の超弾性体
材料８の先端に導電体でなおかつ摩擦係数の小さなグラ
ファイト層９を蒸着形成する。そして基板２の電極４
と、硬化時の収縮率の大きな樹脂を使用して加圧力を与
え電気的な接続を得る構造である。このとき超弾性体材
料８は加圧力により圧縮変形しており熱歪みに対して弾
性範囲内で変形追従する。また第２図（ｂ）に示す如く
半導体素子１と基板２の熱膨張係数差によって生ずる剪
断歪みに対しては、基板２の電極４と摩擦係数の小さな
グラファイト層９間ですべりを生ずることにより吸収す
るので安定な電気的接続を維持することができる。な
お、グラファイト層９を基板２の電極４に形成したり、
又、バンプ構造の超弾性体材料８を基板２の電極４に形
成し、半導体素子１の電極４と超弾性体材料８間にグラ
ファイト層９がある構造としても特性上何ら問題は無
い。Example 2 FIGS. 2 (a) and 2 (b) show a cross-sectional structure of a connection portion according to a second example of the present invention, in which Ti-50.5 at% formed on the electrode 4 of the semiconductor element 1 by vapor deposition. A graphite layer 9 which is a conductor and has a small friction coefficient is formed by vapor deposition on the tip of a superelastic material 8 having a Ni bump structure. And the electrode 4 of the substrate 2
And a structure in which a resin having a large shrinkage rate at the time of curing is used to apply a pressing force to obtain an electrical connection. At this time, the superelastic material 8 is compressively deformed by the pressing force, and follows the thermal strain within the elastic range. In addition, as shown in FIG. 2 (b), a shearing strain caused by a difference in thermal expansion coefficient between the semiconductor element 1 and the substrate 2 is caused by a slip between the electrode 4 of the substrate 2 and the graphite layer 9 having a small friction coefficient. Stable electrical connection can be maintained because of absorption. The graphite layer 9 is formed on the electrode 4 of the substrate 2 or
In addition, there is no problem in terms of characteristics even if the superelastic material 8 having a bump structure is formed on the electrode 4 of the substrate 2 and the graphite layer 9 is provided between the electrode 4 of the semiconductor element 1 and the superelastic material 8.
（発明の効果） 本発明により、半導体素子と基板等の接続において最
も熱歪みを受ける接続部に超弾性体材料を使用すること
により、弾性範囲内で繰返し歪みに対して変形しても安
定した電気的接続を得ることができる。(Effect of the Invention) According to the present invention, by using a superelastic material for a connection portion which receives the most thermal strain in the connection between a semiconductor element and a substrate or the like, it is stable even if it is repeatedly deformed within an elastic range. An electrical connection can be obtained.
第１図（ａ），（ｂ）は本実施例の半導体素子接続構造
の断面図である。 第２図（ａ），（ｂ）は本実施例の半導体素子接続構造
の断面図である。 第３図は従来のフリップチップ接合を示したもので、第
４図は熱歪みによりバンプが変形した状態を示す。 第５図は金属バンプを加圧して電気的接続を得る構造の
断面図である。 1:半導体素子、2:配線基板、3:バンプ材、4:電極パッ
ド、5:樹脂、13:金属バンプ材、6,8:超弾性体材料、7:
ボール、9:グラファイト層1 (a) and 1 (b) are cross-sectional views of the semiconductor element connection structure of the present embodiment. 2 (a) and 2 (b) are cross-sectional views of the semiconductor element connection structure of this embodiment. FIG. 3 shows a conventional flip chip bonding, and FIG. 4 shows a state in which the bump is deformed by thermal strain. FIG. 5 is a sectional view of a structure for obtaining an electrical connection by pressing a metal bump. 1: semiconductor element, 2: wiring board, 3: bump material, 4: electrode pad, 5: resin, 13: metal bump material, 6, 8: superelastic material, 7:
Ball, 9: graphite layer
───────────────────────────────────────────────────── フロントページの続き (72)発明者 大関 芳雄 神奈川県川崎市中原区井田1618番地 新 日本製鐵株式會社第１技術研究所内 (72)発明者 渡辺 敬介 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (72)発明者 金森 孝史 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (72)発明者 井口 泰男 東京都港区虎ノ門１丁目７番12号 沖電 気工業株式会社内 (56)参考文献 特開 昭57−28337（ＪＰ，Ａ) 特開 平２−137240（ＪＰ，Ａ) 特開 平２−206124（ＪＰ，Ａ) 特開 平２−206175（ＪＰ，Ａ) 特開 平２−206139（ＪＰ，Ａ) 特開 平２−178940（ＪＰ，Ａ) ──────────────────────────────────────────────────続 き Continuing from the front page (72) Inventor Yoshio Ozeki 1618 Ida, Nakahara-ku, Kawasaki-shi, Kanagawa Prefecture New Nippon Steel Corporation 1st Technical Research Institute (72) Inventor Keisuke Watanabe 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (72) Inventor Takashi Kanamori 1-7-1, Toranomon, Minato-ku, Tokyo Oki Electric Industry Co., Ltd. (72) Inventor Yasuo Iguchi 1-7-7 Toranomon, Minato-ku, Tokyo No. 12 Oki Electric Industry Co., Ltd. (56) References JP-A-57-28337 (JP, A) JP-A-2-137240 (JP, A) JP-A-2-206124 (JP, A) JP-A JP-A-2-206175 (JP, A) JP-A-2-206139 (JP, A) JP-A-2-178940 (JP, A)
Claims (3)
的接続を得る半導体素子接続構造で、かつ接続部間を可
動構造としたことを特徴とする半導体素子接続構造。1. A semiconductor element connection structure in which a superelastic material is interposed to obtain electrical connection by pressurization, and wherein a movable structure is provided between connection portions.
ボールを挿入してなる請求項１記載の半導体素子接続構
造。2. The semiconductor element connection structure according to claim 1, wherein the movable structure comprises a conductive ball inserted between the superelastic bumps.
小さな導電体をコーティングしてなる請求項１記載の半
導体素子接続構造。3. The semiconductor element connection structure according to claim 1, wherein the movable structure is formed by coating a superelastic bump with a conductor having a small friction coefficient.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027302A JP2709496B2 (en) | 1989-02-06 | 1989-02-06 | Semiconductor element connection structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1027302A JP2709496B2 (en) | 1989-02-06 | 1989-02-06 | Semiconductor element connection structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH02206141A JPH02206141A (en) | 1990-08-15 |
| JP2709496B2 true JP2709496B2 (en) | 1998-02-04 |
Family
ID=12217297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1027302A Expired - Fee Related JP2709496B2 (en) | 1989-02-06 | 1989-02-06 | Semiconductor element connection structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2709496B2 (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2736569B1 (en) * | 1995-07-13 | 1997-08-08 | Thomson Csf | CONNECTION DEVICE AND CONNECTION METHOD |
-
1989
- 1989-02-06 JP JP1027302A patent/JP2709496B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH02206141A (en) | 1990-08-15 |
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