JP3524515B2 - Level shifter - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] TECHNICAL FIELD The present invention relates to a read-only
Memory (hereinafter referred to as ROM), static lander
Access memory (hereinafter referred to as SRAM), die
NAMIC Random Access Memory (hereinafter DRA)
M, etc.) in a memory circuit or the like.
Sing that detects and amplifies the flow and enables high-speed reading
Level shifters used in
To do. [0002] 2. Description of the Related Art Conventionally, technologies in such a field include:
For example, there is one described in the following literature. Reference 1: Electronics Letters (ELECTRONICS LET)
TERS),twenty three[13] (1987-6-18) (US) C. TEMES,
W. H. KI “FAST CMOS CURRENT AMPLIFIER AND BUFFER
 STAGE ”P.696-697 Reference 2: IEEE Journal of Solid-State
It Circuits (IEEE JOURNAL OF SOLID-STATE CI
RCUITS),26[4] (1991-4) (USA) Evert Seevinck,
etc “Current-Mode Techniques for High-Speed VL
SI Circuits with Application to Current Sense Ampl
ifier for CMOS SRAM^,s "P.525-536 [0003] Reference 1 describes a sense amplifier.
Reference 2 describes more specific applications to memory circuits.
It is described in. FIG. 2 is described in the above-mentioned documents 1 and 2.
FIG. 9 is a main circuit diagram of a memory circuit including a conventional sense circuit.
You. In this memory circuit, a plurality of switch means 1
Data line DL, and the data line DL
The input terminal IN of the circuit 10 is connected. Sense times
Although not shown, the output terminal OUT of the path 10
Connected to differential amplifier. The switch means 1 is, for example, a memory circuit.
In the case of a ROM, it is a memory cell itself. Memory circuit
Is a DRAM, the switch means 1 is connected to the data line DL.
Between a second potential supply terminal (for example, ground GND)
N-channel MOS transistors connected in series to
(Hereinafter, referred to as NMOS) 1a and 1b. N
The gate of the MOS 1a is connected to the column selection line CL.
Further, the gate of the NMOS 1b is connected to the bit line BL.
I have. Generally, in a DRAM, data
The line DL is a complementary pair line, and is actually a switch.
Means 1, data line DL and sense circuit 10 are another set
And the output terminals OUT of the two sense circuits 10
Connected to a pair of input terminals of the voltage differential amplifier
It is omitted in FIG. 2 for simplification of the description. The sense circuit 10 includes a data line load circuit 11
And a current-voltage conversion circuit 12 and an inverting amplifier 13.
ing. The data line load circuit 11 has a gate connected to GND.
Connected P-channel MOS transistor (hereinafter referred to as PMO
11a, whose source is the first potential
Supply terminal (for example, V_CC), The drain is the input terminal IN
Connected to each other. The current-voltage conversion circuit 12
PMOS connected in series between input terminal IN and GND
12a and an NMOS 12b. PMOS
12a, the source is the input terminal IN and the gate is the node N
2, the drain is connected to the output terminal OUT and the node N1.
Each is connected. The NMOS 12b has a drain and
Gate connected to node N1 and source connected to GND
Have been. The nodes N1 and N2 are connected to the inverting amplifier 13
Input node A_inAnd output node A_{ou t}Are connected
Have been. The inverting amplifier 13 has V_CCAnd between GND and
Composed of column-connected PMOS 13a and NMOS 13b
Have been. The PMOS 13a has a source of V_CCTo the game
And drain are output node A_outConnected to
ing. The NMOS 13b has a drain connected to the output node A.
_outAnd the gate is the input node A_inAnd the source is GND
Each is connected. Next, the operation will be described. Data line load circuit
The PMOS 11a in the device 11 operates in an unsaturated state. That is,
The data line DL is connected to V_CCBiased to a high potential near
The bias voltage is converted to a current-to-voltage via the input terminal IN.
Applied to the circuit 12. For example, one selected switch means 1
Is turned on and the current ΔI flows into the data line DL, the data
Switch means 1 and a current-voltage conversion circuit for the data line DL
12 are connected in parallel with each other,
Bias current flowing into the path 12 is reduced by ΔIa (≒ ΔI)
Less. The decrease in the bias current is determined by the
The voltage is converted to a voltage at 12 and the output voltage is output from the output terminal OUT.
Is output. The current / voltage conversion circuit 12
The exchange is performed as follows. That is, current-voltage conversion
When the bias current flowing through the circuit 12 decreases, the resistance means
The voltage drop of the NMOS 12b acting as
The potential of the node N1, which is also the input of the inverting amplifier 13, drops.
As a result, the node N which is the output of the inverting amplifier 13
2 increases, and the conductance of the PMOS 12a increases.
Become smaller. Therefore, the current flows through the current-voltage conversion circuit 12.
The current is throttled smaller. In other words, the current-voltage conversion circuit
Positive feedback is applied to the path 12, and a large voltage is applied to the output terminal OUT.
The pressure amplitude will be obtained. On the other hand, attention is paid to the data line load circuit 11.
As the current flowing to the data line DL increases,
The current flowing through the current-voltage conversion circuit 12 decreases. That
Therefore, the change in the current flowing through the data line load circuit 11 is small.
And the change in the potential of the data line DL can be reduced.
The Rukoto. As described above, in the conventional memory circuit, the input
Terminals IN and V_CCThe gate was connected to GND
A data line load circuit 11 composed of a PMOS 11a is provided,
A current-to-voltage conversion circuit 12 is connected between the input terminal IN and GND.
And the current-voltage conversion circuit 12 and the data line D
The switch means 1 connected to L is connected in parallel.
It is configured as follows. Therefore, the current-voltage conversion circuit 12
Since a large bias voltage can be applied, the operating voltage can be reduced.
However, sufficient operation margin and operation speed can be obtained (immediately
(Excellent low power supply voltage operation). Moreover, current-voltage conversion
The input of the inverting amplifier 13 that controls the circuit 12 is an output terminal
By obtaining directly from OUT, the entire sense circuit 10 is correct.
Since the feedback is used, the voltage of the input terminal IN
A large gain can be obtained while suppressing the change in position. In addition, before
In Document 1, in order to obtain the above operation stably, NM
The ratio of the capabilities of the OSs 12b and 13b and the PMOS 12a and
It is necessary to make the ratio of the capabilities of
It is stated that. [0013] SUMMARY OF THE INVENTION However, the conventional
In the circuit, (a) set each circuit constant to operate stably.
And (b) especially for DRAM
The voltage amplitude of the data line DL is sufficiently small
There was a problem that it was not possible. Below, the problem
Will be described. (A) Determination of circuit constants for stable operation
Difficulty First, it is difficult to obtain a circuit that operates stably.
I will explain the problem. For example, in FIG.
The load circuit 11 and the current / voltage conversion circuit 12
(Hereinafter referred to as circuit 1), and inverting amplifier 13
It is assumed that the circuit 2 is used. The input of the circuit 1 is the node N2 and the output is
Considering the case of N1, circuit 1 functions as an inverting amplifier. Immediately
That is, the output of the first inverting amplifier (circuit 1) is
Input to the second inverting amplifier (circuit 2).
The output of 2) is input to the first inverting amplifier (circuit 1)
I have. FIG. 3 illustrates the stability of such a circuit.
FIG. 3 is an input / output characteristic diagram of a circuit 1 and a circuit 2 for performing the above. In FIG.
Is the input potential V of the circuit 1 on the horizontal axis._I1And the output potential V of the circuit 2
_O2Is taken, and the vertical axis represents the output potential V of the circuit 1._O1And circuit 2
Force potential V_I2Has been taken. Curve C in FIG.₁Is the circuit 1
Input / output characteristic curve, curve C_TwoIs the input / output characteristic curve of circuit 2.
It is. Next, each characteristic will be described.
In order to improve the performance,
Shoulder voltage is V_TN, Enhancement type PMOS
Threshold voltage to V_TP(<0). Also,
In the following description, each transistor is not specifically noted.
Entities should be of the enhancement type. The circuit 1 in the sense circuit 10 has its input
As the potential of the node N2 increases.
The potential of the node N1 decreases. And the input potential
Is V _CC− | V_TP|, Circuit 1 is cut off
You. At this time, the output potential of the circuit 1 is V_TNIt is. one
On the other hand, in the circuit 2, the potential of the input node N1 is low.
As the voltage drops, the potential of the output node N2 rises.
Go. When the potential of this input is V _TNCircuit 2 is cut when
Off, and the output potential at this time is V_CC− | V_TP|.
Therefore, the input / output characteristic curve C₁And C_TwoChanges at the operating point P
Not only that, but also at another point Q. this
As described above, since the conventional circuit has a plurality of operating points P and Q,
At the same time, it enters the holding state as a latch or
And it is difficult to obtain stable operation.
There was a problem. Here, the input / output characteristic curve C₁And C_TwoIs point Q
As a method of avoiding contact with the
13) The source of the PMOS 13a is V_CCInstead of
V_CCSlightly lower potential V_REFMay be applied
It is. However, V_CC-V_{RE F}→ Potential that is 0
It is not easy to generate and stably supply. I
This V_REFAnd V_CCIf the difference is too small, the noise
For example, the circuit may oscillate. On the other hand, V_CC-V_TP= V_REFWill be
Una, relatively V_CCIt is easy to generate a potential with a large difference from
You. However, such a potential V_REFOf the PMOS 13a
When applied to the source, the current-voltage conversion circuit 12 and the inverting
Since the symmetry of the circuit constant with the pump 13 becomes worse,
As described above, the performance ratio of each transistor is described in the above reference 1.
Amplification will not be achieved just by setting
You. In the conventional configuration, the sense circuit 1
To increase the output amplitude of 0, the inverting amplifier 13
Output amplitude also increases, and the positive feedback loop gain increases.
There is also the problem of too much. That is, the output voltage amplitude and
There is a problem that the road gain cannot be adjusted independently,
It was not easy to apply to various fields. (B) Data line when used for DRAM
Difficulty in suppressing voltage amplitude Next, when used in a DRAM, the voltage amplitude of the data line DL
The problem that can not be kept small enough
explain. Generally, in a DRAM, a word line is active.
The voltage amplitude of the bit line pair immediately after
Therefore, the change in the current flowing through the data line DL is extremely small. one
Column address straw in page mode
Word line is activated as in the case of
After a sufficient time has passed since the completion of the
The voltage amplitude is large and flows through the data line DL.
The change in the applied current is large. In other words, DRAM
Requires a sense circuit with a wide dynamic range.
Is required. In the conventional configuration, the data line load circuit 1
1 is a PMOS 11a having a gate connected to GND.
Therefore, there were the following problems. That is,
At the point when the voltage amplitude of the pair of
When the capability of the PMOS 11a is determined so that the
At the time of read operation when the voltage amplitude of the pair of cut lines is large
At the same time, the saturation of the PMOS 11a starts,
The potential change of the line DL becomes unnecessarily large. For this reason,
For the next one, reading the next address is delayed or
There is a problem that the operation of the sense circuit 10 becomes unstable. On the other hand, the above document 2 discloses a data line load circuit.
For 11, use NMOS connected gate and drain
Examples are also provided. In such a configuration, the load
Since the curve does not bend sharply,
Can be widened. However, such data line load
When the path 11 is used, the current-voltage conversion circuit 12
Voltage is V_CC-V_TNN(However, V_TNNIncludes the substrate effect
The threshold voltage of the NMOS, V_TNN≫V_TN)
Can be applied only up to Therefore, especially low power supply voltage operation
In the V_CC≫V_CC-V_TNNThe operating speed and
There is a major inconvenience in terms of operating margin. [0024] The present invention has been made to solve the above-mentioned problems.
Inverting amplifier 1 that controls the current-voltage conversion circuit 12
3 is obtained from the output terminal OUT of the sense circuit 10.
Therefore, it is difficult to obtain a circuit that operates stably, and the output amplitude
That the size of the circuit and the gain of the circuit cannot be adjusted independently
The data line load circuit 11 has a gate connected to GN.
PMOS 11a connected to D, or drain and gate
Low power supply
Sense circuit with wide dynamic range in voltage operation
Sense that solved the problem that 10 could not be obtained
Provides a level shifter used for circuits, etc.
You. That is, an object of the present invention is to configure a sense circuit.
It is suitable and useful for other fields.
To provide a lid. [0025] [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
In the present invention,The input voltage input from the input terminal is
The level at which the output voltage is output from the output terminal after a bell shift
In the shifter, an amplification circuit (amplifier) and a source follower
It has a wa. The source of the amplifier has a first potential
Source connected to the supply terminal, input for input voltage
A second terminal having a gate and a drain connected to the input terminal;
Depletion-type first MOS transistor of one conductivity type
Transistor and the drain of the first MOS transistor
Drain connected to the first MOS transistor
And a second potential supply connected to the drain of
A negative electrode of a second conductivity type having a source connected to the terminal;
A loading second MOS transistor. Previous
The source follower is connected to the first potential supply terminal.
Drain, a gate connected to the input terminal, and
And outputs an output voltage obtained by level shifting the input voltage.
The second conductivity type having a source connected to the output terminal
Enhancement-type third MOS transistor
Connected to the source of the third MOS transistor
Drain, the gate of the second MOS transistor
Connected to the connected gate and the second potential supply terminal.
Connected to the second MOS transistor
And a negative current of the second conductivity type that constitutes a current mirror
And a loading fourth MOS transistor. [0026]By adopting such a configuration,
When the input voltage is input to the input terminal, the input voltage
Amplified by the first and second MOS transistors,
To the gate of the MOS transistor. This
And a source composed of third and fourth MOS transistors.
The amplitude of the output voltage output from the follower to the output terminal is
It can be larger than the amplitude of the input voltage. Also, input terminal
Is the drain of the first MOS transistor and the third MO
The source of the S transistor is capacitively coupled. First
The drain of the MOS transistor
Miller effect due to the amplified voltage signal of opposite polarity
Occurs, but at the same time, the source of the third MOS transistor
On the input side, the amplified voltage of the positive polarity
A signal occurs. This voltage signal is applied to the third MOS transistor.
The input terminal is electrically connected by the gate-source capacitance of the
And positive feedback is applied. With this positive feedback,
The capacitance between the gate and drain of one MOS transistor
The resulting Miller effect is canceled out to very high frequencies
Output characteristics without gain deterioration can be obtained. [0027] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG.
FIG. 4 is a circuit diagram of a sense circuit showing a first reference example of FIG. this
In the sense circuit, the input terminal IN is connected to the node N11.
The node N11 and a first potential supply terminal (for example, V
_CC) Is connected to the data line load circuit 100.
You. The node N11 and a second potential supply terminal (for example, GN
D), the current-voltage conversion circuit 200 is connected
I have. The current-voltage conversion circuit 200 includes a PMOS 201 and
It is composed of a series circuit of resistance means 210. PMOS
201 has a source at the node N11 and a gate at the node N
12, a drain is connected to one end of the resistance means 210 and an output terminal
OUT, respectively. Of the resistance means 210
The other end is connected to GND. Inverting amplifier 3 is connected to nodes N11 and N12.
00 input node A_inAnd output node A_outAre each
It is connected. Inverting amplifier 300 is depleted
And a series circuit of a PMOS 301 and a resistor 310.
Has been established. The PMOS 301 has a source of V_CC,
Is the input node A_inThe drain of the resistance means 310
One end and output node A_outAre connected to
You. The other end of the resistance means 310 is connected to GND.
You. Next, the operation will be described. Input terminal IN is V
_CCIs biased to a predetermined level close to. Data line
A constant bias voltage is applied from the load circuit 100 to the input terminal IN.
Style I₁Is flowing (I₁= 0.) or,
From data line load circuit 100 to current-voltage conversion circuit 200
Also has a constant bias current I_TwoIs flowing. This state
Then, the PMOS 201 is designed to be in a saturated state.
I have. For example, the current I flowing out of the input terminal IN
₁Is ΔI₁Only increase. Then, the data line load
The current flowing through the circuit 100 decreases and the input terminal IN (immediately
That is, the level of the node N11) slightly decreases. This is
Amplified by the inverting amplifier 300, the level of the node N12
Bell rises. Therefore, the source voltage of the PMOS 201 is
The gate potential rises and its gate potential rises.
・ Drain voltage is small and conductance is small
It becomes. Since the PMOS 201 is saturated,
The conductance greatly changes, and the current-voltage conversion circuit 20
Current I flowing through 0_TwoIs ΔI_Two(≒ ΔI₁) Only decrease
You. As a result, the potential of the output terminal OUT becomes ΔV = −ΔI_Two
・ R₁₁(However, r₁₁; Only the resistance value of the resistance means 210)
The resistance r₁₁Is appropriately determined and the desired output power
Pressure amplitude can be obtained. On the other hand, the electric current flowing through the data line load circuit 100
Style I_LFor the current I₁Current I_TwoBut
There is no major change as it decreases. Therefore, the input terminal I
The potential of N is kept almost constant. Thus, input
It supports the input current signal while suppressing the voltage amplitude of the terminal IN.
An output signal having a large voltage amplitude can be obtained. The present embodiment has the following advantages. (A) Current-voltage conversion circuit between input terminal IN and GND
Since the path 200 is provided, in a memory circuit or the like,
When a data line is connected to the input terminal IN and used,
Switch means and current-voltage conversion circuit connected to the data line
And 200 are connected in parallel, enough for both
A bias voltage can be applied. Therefore, lower the power supply voltage
However, it is excellent in operation speed and operation margin.
It is excellent in low power supply voltage operation. (B) In the inverting amplifier 300,
Input node A_inMOS transistor connected to
The inversion amplifier 300 is
There is no cutoff, and the bias
Rank V_CCCan be brought close enough. Therefore, the current
The voltage conversion circuit 200 has almost V_CCBias power until full
Voltage and can operate at low power supply voltage.
Can be (C) Controlling the current-voltage conversion circuit 200
Node A of the inverting amplifier 300 _inTimes the signal of
Operation stability because it is obtained directly from the input terminal IN of the road.
Is excellent. Hereinafter, this point will be described in detail. For example, in FIG.
The data line load circuit 100 and the current-voltage conversion circuit 2
00 as a circuit 1 and an inverting amplifier 30
0 is a circuit 2. The input of circuit 1 to circuit 2 is no
And the output is a node N11. Meanwhile, times
The input of circuit 2 to path 1 is node N11 and the output
Is the node N12. That is, the inputs of the circuit 1 and the circuit 2
The outputs are cross-connected to each other. Here, focusing on the circuit 1, the output of the circuit 1 will be described.
The force (node N11) is applied to its input (node N12).
It has become a source follower. That is, the circuit 1
Since it works as a source follower for Road 2,
The input and output do not become out of phase, and the amplification factor is smaller than 1. Yo
No positive feedback is applied, and the latch
Without the risk of entering or oscillating.
A stable product is obtained. In order to increase the output voltage amplitude,
What is necessary is just to make the value of the resistance means 210 large. sense
In order to increase the gain of the entire circuit, the inverting amplifier 300
Or the current-voltage conversion circuit 200
The bias potential of the gate of the PMOS 201 is properly determined.
Adjustment such as deepening the saturation of the PMOS 201
Just fine. Thus, the magnitude of the output voltage amplitude and the overall circuit
Body gain can be adjusted independently, so desired characteristics can be easily adjusted
Can be obtained. (Second Reference Example) FIG. 5 shows the first reference example shown in FIG.
FIG. 2 is a circuit diagram that further embodies the sense circuit of the reference example of FIG.
Elements common to those in FIG. 4 are denoted by common reference numerals.
You. In this sense circuit, the data line load circuit 10 of FIG.
0 is a PMOS 101 having a gate connected to GND.
And the resistance means 2 in the current-voltage conversion circuit 200.
10 is an NMOS 211 having a gate and a drain connected to each other.
And the resistance means 31 in the inverting amplifier 300.
0 is an NMOS 311 having a gate and a drain connected to each other.
It is configured. Other configurations are the same as those in FIG. This embodiment has the following advantages.
You. (1) The resistance means in the inverting amplifier 300 is connected to the gate and the gate.
It is composed of NMOS 311 connected to rain.
The output node A of the inverting amplifier 300_outVoltage amplitude of
Is limited. Therefore, the gain of the entire circuit is small.
However, the dynamic range can be widened. So
The other configuration is basically the same as that of the first reference example.
Thus, as in the first reference example, it has excellent low power supply voltage operation,
It has the advantage of excellent crop stability. (2) In this reference example, the same as the first reference example
The magnitude of the output voltage amplitude and the gain of the entire circuit
Can be adjusted vertically. Here, FIG.
This will be specifically described with reference to FIG. First, in FIG.
The data line load circuit 100 and the current-voltage conversion circuit 200
Collectively, the circuit 1 is used, and its input is connected to the node N12.
And the output is a node N11. Also, the inverting amplifier 30
0 is a circuit 2. Then, the circuit 1 and the circuit 2
The force and the output are cross-connected to each other. FIG. 6 shows the stability of a circuit having such a configuration.
FIG. 9 is an input / output characteristic diagram for determination. The horizontal axis in FIG.
Input potential V of path 1_I1And the output potential V of the circuit 2_O2And
The vertical axis represents the output potential V of the circuit 1._O1And the input potential V of the circuit 2
_I2It is. Curve C₁Is the input / output characteristic curve of the circuit 1
Line C_TwoIs the input / output characteristic curve of the circuit 2. As in the first embodiment, the circuit 1 is replaced by the circuit 2.
On the other hand, it works as a source follower. Therefore, the characteristic curve
C₁Is the input potential V_I1Rises and the output potential V_O2Also rise
Shape. Circuit 2 is an inverting amplifier 300
And its characteristic curve C_TwoIs the input potential V_I2Appears when
Force potential V_O2Is descending. Therefore, the characteristic curve C
₁And C_TwoIntersect at one operating point P. Thus, dynamic
Since there is only one point P, an extremely stable circuit
can get. (Third Reference Example) FIG. 7 shows a first reference example.
4 shows a third reference example that embodies the sense circuit of FIG.
FIG. 6 is a circuit diagram of a sense circuit, which shares elements with FIGS. 4 and 5.
Common elements are denoted by common reference numerals. This sense circuit is similar to the sense circuit of FIG.
And the same as the sense circuit of FIG.
NMOS 101 for data line load and current-voltage conversion circuit
200 and a configuration difference from the inverting amplifier 300.
Is provided. Inverting amplifier
300A is a depletion type PMOS 301 and NM
It is composed of a series circuit of OS311. PMOS30
1 means the source is V_CCAnd the gate is the input node A_inTo
Rain is output node A_outAre connected to
You. The NMOS 311 has a drain connected to the output node A.
_outAnd the gate is the input node A_inAnd the source is GND
Are connected respectively. Other configurations are the same as in FIG.
It is. In this embodiment, the gate of the NMOS 311 is
Input node A of inverting amplifier 300A _inConnected to
The gain of the inverting amplifier 300A can be increased. Yo
The overall dynamic range of the circuit is rather narrow.
However, the gain of the circuit can be improved. The operation is basically
Are the same as in the first and second reference examples.
Similar advantages are obtained. FIG. 8 shows a fourth embodiment of the present invention.
FIG. 4 is a circuit diagram of a sense circuit showing a reference example, and includes first to third sense circuits;
Elements common to the elements in FIGS. 4, 5 and 7 showing the reference example
The primes are assigned common symbols. In this sense circuit, the data shown in FIGS.
Data line load circuit 1 having a different configuration from data line load circuit 100
00A and the same current-voltage conversion circuit 200
And a switching amplifier 300. Data line load circuit 1
00A is the input node L connected to the node N11._inWhen
V_CCAnd an input node between the PMOS 101
Is the input node L_inAnd the output is via node N21.
Level shifter 1 connected to the gate of PMOS 101
02, and Other configurations are the first to third
Since it is the same as the reference example, the basic
The operation is the same. Therefore, the configuration and basic
The description of the operation is omitted, and the following description will be made mainly on the data line load circuit
The characteristics of 00A will be described. FIG. 9 shows the data line load circuit 100A of FIG.
5 is a characteristic diagram showing a load curve of FIG. The horizontal axis in FIG.
De L_inPotential V_LINThe vertical axis represents the data line load circuit 100A.
Current I flowing through PMOS 101 in_LIt is. Solid line song
Line l₁Is a load curve of the data line load circuit 100A.
You. Dashed curve l_TwoAnd l_ThreeWas added for explanation
So the curve l_TwoUses only the PMOS 101 as a load,
Gate potential V_GTo V _G= V_CC-V_SHFWith the load curve
is there. Curve l_ThreeUses only the PMOS 101 as a load,
Gate potential V_GTo V_GIt is a load curve with = 0V.
Voltage V_SHFIs the shift voltage by the level shifter 102
Yes, | V_SHF| ≧ | V_TP| For example, V_LIN= V_CCThen
Is applied to the voltage V by the level shifter 102._SHFOnly
The PMOS 101 through the node N21.
Output to the gate. Therefore, the game of the PMOS 101
Potential V_GIs V_G= V_CC-V_SHFIt becomes. The potential V_LINDecreases, the gate potential
V_GAlso decreases, the current flowing through the PMOS 101
I_LWill increase. Further, the potential V_LINDecreases and V
_LIN<V_SHFThen V_G= 0V and the potential V_LIN
The current I_LBecomes constant. That
Therefore, the load curve l₁Is the potential V_LINIs V_CCIn the area near
Is the curve l_TwoTangent in the unsaturated region at
Characteristic and the potential V _LINDecreases and the curve l_ThreeApproach
Shows a form that saturates. Thus, the data line negative
In the load circuit 100A as a whole, an apparently unsaturated region is formed.
Acts like an extended MOS transistor. Here, the curve l_ThreeIs the conventional data line load
Considering that it is equivalent to the characteristics of the road, the data of this reference example
In the line load circuit 100A, the current value at which the characteristic starts to be saturated is
When they are equal, the equivalent resistance value is larger than the conventional one.
I can do it. That is, the input node L_inVoltage swing
When the maximum allowable width is designed to be equal,
As a result, a minute current signal can be reliably sensed.
On the other hand, the equivalent resistance value of the data line load circuit is made equal.
Then, the characteristics of this reference example are better than those of the conventional one.
The current value at which the saturation starts can be increased. As described above, this embodiment has the following advantages.
Have a point. (I) The data line load circuit 100A is a PMOS 101
And the level shifter 102,
Has improved linearity and wider dynamic range than before.
A good sense circuit can be obtained. The operation of the level shifter 102
As a result, the potential of the input terminal IN becomes V_CCEven the load
PMOS 101 does not cut off.
Set the bias potential of the child IN to V_CCCan be close to
Therefore, even if the dynamic range is wide,
The advantage of good operation is not impaired. (Ii) The sense circuit of the present embodiment has the first
Instead of the data line load circuit 100 of the reference example,
A data line load circuit 100A is provided.
Identical. Therefore, similarly to the first reference example, the low power supply
Excellent pressure operation, excellent operation stability, and desired characteristics
It has the advantage of being easily obtained. (Iii) Application of data line load circuit 100A of this reference example
Is not only a sense circuit, but also a
Used as load means for various circuits requiring current-voltage characteristics
Is also effective. (Embodiment) FIG. 1 shows an embodiment of the present invention.
FIG. 4 is a circuit diagram of the sense circuit shown, showing first to fourth reference examples;
Elements shown in FIG. 4, FIG. 5, FIG. 7, and FIG.
Are denoted by common symbols. This sense circuit
8, a data line load PMOS 101 similar to FIG.
A similar current-voltage conversion circuit 200 and a level with an amplification function
And a shifter 400. For data line load
The PMOS 101 has input terminals IN and V_CCSeries connection between
Connected between the input terminal IN and GND.
The circuit 200 is connected. Current-voltage conversion circuit 200
Is similar to FIG.
And a connection point between the two is provided at the output terminal O.
Connected to UT. The level shifter 400 is connected to the input terminal IN.
Input node A connected via node N31_inAnd PM
Connected to the gate of OS201 via node N32.
First output node A_out1To the gate of PMOS 101
Second output node A connected via node N33
_out2And This level shifter 400 corresponds to FIG.
Level shifter 102 and inverting amplifier 300
Input node A_inThe gate is connected to
WasThe first MOS transistorDepression type
And the input node A_inConnected to the gate
Was doneA third MOS transistorNMOS 402
When,NMOS as a second MOS transistor for load
411 and a fourth MOS transistor for load, N
MOS 412And a current mirror circuit 410 comprising
It is configured.Here, the PMOS 401 and the load N
An amplifier is constituted by the MOS 411 and the NMOS 40
2 and the load NMOS 412 make the source follower
It is configured. The source of the PMOS 401 isFirst potential supply
Supply terminalV_CCAnd the drain is a current mirror circuit 4
10 current input nodes I_inAre connected to
You. The NMOS 402 has a drainFirst potential supply terminal
IsV_CCThe source is the current mirror circuit 410
Outflow node I_out And the output terminalSecond output node
A_out2 WhenAre connected respectively. Current mirror
The circuit 410 is composed of the NMOSs 411 and 412
Each sourceA second potential supply terminalConnected to GND
And each gate is connected to the first output node A_out1Connected to
ing. The drain and gate of the NMOS 411
Input node I_inIt is connected to the. NMOS 412
Rain is the current output node I_outIt is connected to the. Next, (1) the operation of the level shifter 400
And (2) input node A_inAnd the first output node A
_out2And (3) the operation of the entire sense circuit and
The advantages of the present embodiment will be described. (1) Operation of level shifter 400 Input node A_inAnd output node A_out1Between the PMO
Connected with an inverting amplifier consisting of S401 and NMOS 411
This part is the same as the inverting amplifier 300 of FIG.
It is a structure of. Therefore, output node A_out1Input
Code A_in(That is, the voltage signal at the input terminal IN) is inverted and amplified.
Is output. (2) Input node A_inPotential and the second output
Force node A_out2FIG. 10 shows the level of FIG.
Output node A of shifter 400_out2To explain the operation of
FIG. 6 is an operation characteristic diagram of FIG. The vertical axis in this figure is current, and the horizontal axis is voltage
It is. For example, the capabilities of NMOSs 411 and 412 are equal.
Shall be. Referring to FIG._NaOutputs the horizontal axis
Node A_out2The vertical axis represents the potential flowing through the NMOS 402.
Given the size of the flow, input node A_inPotential of V_aAnd
4 is a current-voltage characteristic curve of the NMOS 402 at the time. FIG.
0, the output node A_out2Is V_a-V
_TNNAt lower levels, current begins to flow. Curve C_Nb
Is the input node A_inPotential of V_bNMOS when
402 is a current-voltage characteristic curve of FIG.
Curve C_NaIs the same as In this case, output node A
_out2Is V_b-V_TNNAt lower levels, current will flow
start. Curve l_aAnd l_bIs the output node A on the horizontal axis
_out2And the vertical axis represents the current flowing through the NMOS 412.
Current-voltage characteristic curve of the NMOS 412 when the size is
Line. Curve l_aIs the input node A_inIs V_aso
At some point, the curve l_bIs the input node A_inNo electricity
Place is V_bIt is when it is. Curve C_bIs the horizontal axis
Input node A_inAnd the vertical axis flows through the PMOS 401.
Current-voltage characteristics of the PMOS 401 when the current is
It is a curve. For example, input node A_inIs V_aIn
The current flowing through the PMOS 401 is I_aThen
This current I_aAlso flows to the NMOS 411. NMOS4
11 and 412 constitute a current mirror circuit 410
Therefore, even in the NMOS 412, the current I_aFlows
Will be. Therefore, the characteristic curve l of the NMOS 412 _a
And characteristic curve C of NMOS 402_NaMeans that the current value is I_aWhen
Point P_aMeet at This point P_aIs the input node A_inof
Potential is V_aOutput node A when_out2Operating point
The operating point P_aVoltage value V_outaIs the output node A_out2of
Potential. Similarly, input node A_inIs V_bIn
The current flowing through the PMOS 401 is I_bThen
At this time, the current flowing through the NMOS 412 is also I_bBecomes
The characteristic curve l of the NMOS 412_bAnd NMOS 402
Characteristic curve C_NbMeans that the current value is I_bPoint P_bExchanged in
You. This point P_bIs the input node A_inIs V_bIs
Output node A_out2Operating point, and the voltage value V
_outbIs the output node A_out2Potential. As described above, the level switch in this embodiment is
In the lid 400, the input voltage signal is level-shifted
In addition, the input voltage amplitude V_a-V_bIs amplified and V_outa
-V _outb(> V_a-V_b) Large voltage amplitude
You. The conditions under which the input voltage amplitude is amplified in this way
Indicates that the NMOS 412 is saturated, and the input node
Code A_inIs V_CCNeeds to be close enough. I
However, this is the operating condition of the sense circuit of the present embodiment.
It does not restrict the operation. Next, the output voltage of the conventional level shifter
The amplitude is compared with that of the present embodiment. For example, NM
OS 412 is controlled by the current I_aTo be a constant current source
To achieve. Then, input node A_inIs V_bIs
Output node A_out2Operating point is P_bbAnd the potential is V
_outbbTherefore, the output voltage amplitude is V_outa-V_outbbWhen
Therefore, it is smaller than that of the present embodiment. That is, the present embodiment
, The same input voltage amplitude
Output voltage amplitude greater than
Level shift signal is obtained. (3) Operation of the entire sense circuit and this embodiment
Advantage of First output node A of level shifter 400_out1In the
A voltage output signal obtained by inverting and amplifying the voltage signal of the force signal IN is
This is the PMOS2 in the current-voltage conversion circuit 200.
01 is driven. On the other hand, the level shifter 400
As a result, the voltage signal at the input terminal IN is level-shifted.
And an amplified level shift signal is obtained.
Control of the gate of the PMOS 101 for data line load
Is done. Therefore, the operation of the entire sense circuit is basically
Is the same as that of the fourth embodiment shown in FIG.
Excellent voltage operation, excellent operation stability, and dynamic
A sense circuit with a wide mix range can be obtained. Further, in the present embodiment, compared with the conventional one,
Because a greatly amplified level shift output can be obtained,
4 is more data than that in FIG.
Improved line load characteristicsinputDynamic range
WideLinear (linear) characteristicsThings are obtained.That
Above, the gate of the NMOS 402 constituting the source follower
Positive feedback is applied to the PMOS 4
01 high frequency
Excellent broadband characteristics that do not cause gain deterioration are obtained.
further,In this embodiment, one level shifter 400
Input voltage signal inverted amplification output and level shift output
Therefore, rather than providing an inverting amplifier separately,
The number of elements of the sense circuit can be reduced. Also, in this embodiment,
Level shifter 400 is intended for use in sense circuits only.
Species that are not specified and require amplified level-shifted output
Effective in various fields, such as interface circuits
is there. (Modification) The present invention is not limited to the above embodiment and the like.
However, various modifications are possible. Its variants and
For example, there is the following. (I) In the above embodiments and the like, NMOS is replaced with PMOS.
, PMOS to NMOS, V_CCTo GND, GND to
V_CCHas the same effect as the above embodiment.
One circuit is obtained. (Ii) The current path through which current flows constantly during operation (for example,
For example, in the current-voltage conversion circuit 200,.
Can be reduced in standby mode to reduce power consumption during standby.
You. (Iii) A steady current path during operation (for example,
, And the potential supply terminal V_CC
Between the first switch means and the first switch means is inserted in series,
A second switch between the current path and the potential supply terminal GND;
Means in series form, said first switch means and a second
A third switch means is provided at a connection point between the second switch and the second switch.
And a predetermined potential is supplied to the third switch means.
Potential supply means may be provided. In this way, wait
Power consumption during standby and the desired connection during standby
Whether the points can be precharged to a predetermined potential in advance
Sense circuit that can quickly transition from the standby state to the operating state
Is obtained. Also, the first switch means is, for example, a
The transistor may also serve as a data line load transistor. [0069] As described in detail above, according to the present invention,
IfThe gate is the input terminal and the drain is the second
Connected to the MOS transistor, the amplifier circuit (amplifier)
A first input MOS transistor to be configured and a gate
Is the input terminal and the source is the fourth MOS transistor for the load.
And a second input for the input that constitutes a source follower.
3 MOS transistors, wherein the first MOS transistor
The transistor and the third MOS transistor are connected to each other.
Reverse conduction type (reverse polarity) and the amplifier
In order to make the operating range of the source follower common,
The first MOS transistor is a depletion type,
3rd MOS transistor as enhancement type
I have. Further, a second MOS transistor which is a load of the amplifier is provided.
A transistor and a fourth source loader of the source follower.
A current mirror is constituted by MOS transistors.
Connected. With such a configuration, the loss (b)
Level shift operation (with the same input if necessary)
Larger output voltage swing for signals with force voltage swing
Level shift signal), and a wide input dynamic
A linear (linear) characteristic having cleansing can be obtained.
In addition, a third MOS transistor for inputting the source follower
Positive feedback applied to the gate of the
Of the mirror effect of the first MOS transistor
Therefore, it does not cause gain deterioration even at extremely high frequencies.
Broadband characteristics can be obtained.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a sense circuit showing an embodiment of the present invention. FIG. 2 is a main part circuit diagram of a memory circuit including a conventional sense circuit. FIG. 3 is an input / output characteristic diagram of the circuit 1 and the circuit 2 of FIG. 2; FIG. 4 is a circuit diagram of a sense circuit showing a first reference example of the present invention. FIG. 5 is a circuit diagram of a sense circuit showing a second reference example of the present invention. FIG. 6 is an input / output characteristic diagram of the circuit 1 and the circuit 2 of FIG. 5; FIG. 7 is a circuit diagram of a sense circuit showing a third reference example of the present invention. FIG. 8 is a circuit diagram of a sense circuit showing a fourth reference example of the present invention. FIG. 9 is a characteristic diagram of the data line load circuit 100A of FIG. 10 is an operation characteristic diagram of the level shifter with an amplification function 400 of FIG. [Description of Signs] 100, 100A Data line load circuit 101 PMOS 102 Level shifter 200 Current-voltage conversion circuit 201 PMOS 210 Resistance means 211 NMOS 300, 300A Inverting amplifier 301 Depletion type PMOS 310 Resistance means 311 NMOS 400 Level shifter 401 with amplification function Depletion type PMOS 402 NMOS 410 Current mirror circuit 411, 412 NMOS

Claims (1)

(57) [Claim 1] A source is connected to the first potential supply terminal.
Source connected to the input terminal to which the input voltage is input
A data of a first conductivity type having a gate and a drain.
A first MOS transistor of a compression type and a drain connected to the drain of the first MOS transistor;
Drain to the drain of the first MOS transistor
Connected to the connected gate and the second potential supply terminal.
A second load for a load of the second conductivity type having an isolated source
An amplifying circuit including a MOS transistor; a drain connected to the first potential supply terminal;
The gate connected to the input terminal and the input voltage
Connected to the output terminal that outputs the output voltage
Enhancement consisting of a second conductivity type having a sunk source
Type third MOS transistor, and a gate connected to the source of the third MOS transistor.
Rain, connected to the gate of the second MOS transistor
Connected to the gate and the second potential supply terminal.
And a source connected to the second MOS transistor.
For the load of the second conduction type that constitutes the current mirror
And a source follower including the fourth MOS transistor .