JP3524516B2 - Amplifier circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [0001] TECHNICAL FIELD The present invention relates to a read-only
Memory (hereinafter referred to as ROM), static lander
Access memory (hereinafter referred to as SRAM), die
NAMIC Random Access Memory (hereinafter DRA)
M, etc.) in a memory circuit or the like.
Sing that detects and amplifies the flow and enables high-speed reading
Related to amplifying circuits used in lu-end type sense circuits, etc.
Things. [0002] 2. Description of the Related Art Conventionally, technologies in such a field include:
For example, there is one described in the following literature. Reference 1: Electronics Letters (ELECTRONICS LET)
TERS),twenty three[13] (1987-6-18) (US) C. TEMES,
W. H. KI “FAST CMOS CURRENT AMPLIFIER AND BUFFER
 STAGE ”P.696-697 Reference 2: IEEE Journal of Solid-State
It Circuits (IEEE JOURNAL OF SOLID-STATE CI
RCUITS),26[4] (1991-4) (USA) Evert Seevinck,
etc “Current-Mode Techniques for High-Speed VL
SI Circuits with Application to Current Sense Ampl
ifier for CMOS SRAM^,s "P.525-536 [0003] Reference 1 describes a sense amplifier.
Reference 2 describes more specific applications to memory circuits.
It is described in. [0004] FIG. 2 shows a conventional art described in the above-mentioned documents 1 and 2.
FIG. 4 is a main part circuit diagram of a memory circuit including the sense circuit of FIG. In this memory circuit, a plurality of switch means are provided.
1 is commonly connected to the data line DL, and the data line DL
Is connected to the input terminal IN of the sense circuit 10.
Although not shown, the output terminal OUT of the sense circuit 10
It is connected to the voltage differential amplifier of the stage. The switch means 1 is, for example, a memory circuit.
In the case of a ROM, it is a memory cell itself. Memory circuit
Is a DRAM, the switch means 1 is connected to the data line DL.
Between a second potential supply terminal (for example, ground GND)
N-channel MOS transistors connected in series to
(Hereinafter, referred to as NMOS) 1a and 1b. N
The gate of the MOS 1a is connected to the column selection line CL.
Further, the gate of the NMOS 1b is connected to the bit line BL.
I have. In general, in a DRAM, data
The line DL is a complementary pair line, and is actually a switch.
Means 1, data line DL and sense circuit 10 are another set
And the output terminals OUT of the two sense circuits 10
Connected to a pair of input terminals of the voltage differential amplifier
It is omitted in FIG. 2 for simplification of the description. The sense circuit 10 includes a data line load circuit 11
And a current-voltage conversion circuit 12 and an inverting amplifier 13.
ing. The data line load circuit 11 has a gate connected to GND.
Connected P-channel MOS transistor (hereinafter referred to as PMO
11a, whose source is the first potential
Supply terminal (for example, V_CC), The drain is the input terminal IN
Connected to each other. The current-voltage conversion circuit 12
PMOS connected in series between input terminal IN and GND
12a and an NMOS 12b. PMOS
12a, the source is the input terminal IN and the gate is the node N
2, the drain is connected to the output terminal OUT and the node N1.
Each is connected. The NMOS 12b has a drain and
Gate connected to node N1 and source connected to GND
Have been. The nodes N1 and N2
Input node A_inAnd output node A_{ou t}Are connected
Have been. The inverting amplifier 13 has V_CCAnd between GND and
Composed of column-connected PMOS 13a and NMOS 13b
Have been. The PMOS 13a has a source of V_CCTo the game
And drain are output node A_outConnected to
ing. The NMOS 13b has a drain connected to the output node A.
_outAnd the gate is the input node A_inAnd the source is GND
Each is connected. Next, the operation will be described. Data line load circuit
The PMOS 11a in the device 11 operates in an unsaturated state. That is,
The data line DL is connected to V_CCBiased to a high potential near
The bias voltage is converted to a current-to-voltage via the input terminal IN.
Applied to the circuit 12. For example, one selected switch means 1
Is turned on and the current ΔI flows into the data line DL, the data
Switch means 1 and a current-voltage conversion circuit for the data line DL
12 are connected in parallel with each other,
Bias current flowing into the path 12 is reduced by ΔIa (≒ ΔI)
Less. The decrease in the bias current is determined by the
The voltage is converted to a voltage at 12 and the output voltage is output from the output terminal OUT.
Is output. The current / voltage conversion circuit 12
The exchange is performed as follows. That is, current-voltage conversion
When the bias current flowing through the circuit 12 decreases, the resistance means
The voltage drop of the NMOS 12b acting as
The potential of the node N1, which is also the input of the inverting amplifier 13, drops.
As a result, the node N which is the output of the inverting amplifier 13
2 increases, and the conductance of the PMOS 12a increases.
Become smaller. Therefore, the current flows through the current-voltage conversion circuit 12.
The current is throttled smaller. In other words, the current-voltage conversion circuit
Positive feedback is applied to the path 12, and a large voltage is applied to the output terminal OUT.
The pressure amplitude will be obtained. On the other hand, attention is paid to the data line load circuit 11.
As the current flowing to the data line DL increases,
The current flowing through the current-voltage conversion circuit 12 decreases. That
Therefore, the change in the current flowing through the data line load circuit 11 is small.
And the change in the potential of the data line DL can be reduced.
The Rukoto. As described above, in the conventional memory circuit, the input
Terminals IN and V_CCThe gate was connected to GND
A data line load circuit 11 composed of a PMOS 11a is provided,
A current-to-voltage conversion circuit 12 is connected between the input terminal IN and GND.
And the current-voltage conversion circuit 12 and the data line D
The switch means 1 connected to L is connected in parallel.
It is configured as follows. Therefore, the current-voltage conversion circuit 12
Since a large bias voltage can be applied, the operating voltage can be reduced.
However, sufficient operation margin and operation speed can be obtained (immediately
(Excellent low power supply voltage operation). Moreover, current-voltage conversion
The input of the inverting amplifier 13 that controls the circuit 12 is an output terminal
By obtaining directly from OUT, the entire sense circuit 10 is correct.
Since the feedback is used, the voltage of the input terminal IN
A large gain can be obtained while suppressing the change in position. [0015] In the document 1, the above operation is stable.
To obtain the ratio of the capabilities of the NMOSs 12b and 13b.
And the ratio of the capabilities of the PMOSs 12a and 13a
It is stated that it is necessary to do. [0016] SUMMARY OF THE INVENTION However, the conventional
In the circuit, (a) set each circuit constant to operate stably.
And (b) especially for DRAM
The voltage amplitude of the data line DL is sufficiently small
There was a problem that it was not possible. Below, the problem
Will be described. (A) Determination of circuit constants for stable operation
Difficulty First, it is difficult to obtain a circuit that operates stably.
I will explain the problem. For example, in FIG.
The load circuit 11 and the current / voltage conversion circuit 12
(Hereinafter referred to as circuit 1), and inverting amplifier 13
It is assumed that the circuit 2 is used. The input of the circuit 1 is a node N2 and the output is a node N2.
Considering N1, circuit 1 acts as an inverting amplifier. Immediately
That is, the output of the first inverting amplifier (circuit 1) is
Input to the second inverting amplifier (circuit 2).
The output of 2) is input to the first inverting amplifier (circuit 1)
I have. FIG. 3 determines the stability of such a circuit.
FIG. 3 is an input / output characteristic diagram of a circuit 1 and a circuit 2 for performing the above. In FIG.
Is the input potential V of the circuit 1 on the horizontal axis._I1And the output potential V of the circuit 2
_O2Is taken, and the vertical axis represents the output potential V of the circuit 1._O1And circuit 2
Force potential V_I2Has been taken. Curve C in FIG.₁Is the circuit 1
Input / output characteristic curve, curve C_TwoIs the input / output characteristic curve of circuit 2.
It is. Next, each characteristic will be described.
In order to improve the performance,
Shoulder voltage is V_TN, Enhancement type PMOS
Threshold voltage to V_TP(<0). Also,
In the following description, each transistor is not specifically noted.
Entities should be of the enhancement type. In the circuit 1 in the sense circuit 10, the input
As the potential of the node N2 increases.
The potential of the node N1 decreases. And the input potential
Is V _CC− | V_TP|, Circuit 1 is cut off
You. At this time, the output potential of the circuit 1 is V_TNIt is. one
On the other hand, in the circuit 2, the potential of the input node N1 is low.
As the voltage drops, the potential of the output node N2 rises.
Go. When the potential of this input is V _TNCircuit 2 is cut when
Off, and the output potential at this time is V_CC− | V_TP|.
Therefore, the input / output characteristic curve C₁And C_TwoChanges at the operating point P
Not only that, but also at another point Q. this
As described above, since the conventional circuit has a plurality of operating points P and Q,
At the same time, it enters the holding state as a latch or
And it is difficult to obtain stable operation.
There was a problem. Here, the input / output characteristic curve C₁And C_TwoIs point Q
As a method of avoiding contact with the
13) The source of the PMOS 13a is V_CCInstead of
V_CCSlightly lower potential V_REFMay be applied
It is. However, V_CC-V_{RE F}→ Potential that is 0
It is not easy to generate and stably supply. I
This V_REFAnd V_CCIf the difference is too small, the noise
For example, the circuit may oscillate. On the other hand, V_CC-V_TP= V_REFWill be
Una, relatively V_CCIt is easy to generate a potential with a large difference from
You. However, such a potential V_REFOf the PMOS 13a
When applied to the source, the current-voltage conversion circuit 12 and the inverting
Since the symmetry of the circuit constant with the pump 13 becomes worse,
As described above, the performance ratio of each transistor is described in the above reference 1.
Amplification will not be achieved just by setting
You. In the conventional configuration, the sense circuit 1
To increase the output amplitude of 0, the inverting amplifier 13
Output amplitude also increases, and the positive feedback loop gain increases.
There is also the problem of too much. That is, the output voltage amplitude and
There is a problem that the road gain cannot be adjusted independently,
It was not easy to apply to various fields. (B) Data line when used for DRAM
Difficulty in suppressing voltage amplitude Next, when used in a DRAM, the voltage amplitude of the data line DL
The problem that can not be kept small enough
explain. Generally, in a DRAM, a word line is active.
The voltage amplitude of the bit line pair immediately after
Therefore, the change in the current flowing through the data line DL is extremely small. one
Column address straw in page mode
Word line is activated as in the case of
After a sufficient time has passed since the completion of the
The voltage amplitude is large and flows through the data line DL.
The change in the applied current is large. In other words, DRAM
Requires a sense circuit with a wide dynamic range.
Is required. In the conventional configuration, the data line load circuit 1
1 is a PMOS 11a having a gate connected to GND.
Therefore, there were the following problems. That is, when the voltage amplitude of the bit line pair is small
In order to ensure that reading can be performed, the PMOS 11a
When the capability is determined, the voltage amplitude of the bit line pair is large.
At the time of the read operation, the saturation of the PMOS 11a starts.
As a result, the potential change of the data line DL is unnecessarily large.
Become. For this reason, in the conventional system, the next address is read.
Output is delayed or the operation of the sense circuit 10 becomes unstable.
There is a problem. On the other hand, the above reference 2 discloses a data line load circuit.
For 11, use NMOS connected gate and drain
Examples are also provided. In such a configuration, the load
Since the curve does not bend sharply,
Can be widened. However, such data line load
When the path 11 is used, the current-voltage conversion circuit 12
Voltage is V_CC-V_TNN(However, V_TNNIncludes the substrate effect
The threshold voltage of the NMOS, V_TNN≫V_TN)
Can be applied only up to Therefore, especially low power supply voltage operation
In the V_CC≫V_CC-V_TNNThe operating speed and
There is a major inconvenience in terms of operating margin. [0029] The present invention is directed to the problems of the prior art.
Inverting amplifier 1 that controls the current-voltage conversion circuit 12
3 is obtained from the output terminal OUT of the sense circuit 10.
Therefore, it is difficult to obtain a circuit that operates stably, and the output amplitude
That the size of the circuit and the gain of the circuit cannot be adjusted independently
The data line load circuit 11 has a gate connected to GN.
PMOS 11a connected to D, or drain and gate
Low power supply
Sense circuit with wide dynamic range in voltage operation
Sense that solved the problem that 10 could not be obtained
An amplifier circuit used for a circuit or the like is provided. That is, an object of the present invention is to configure a sense circuit.
Suitable for use in other fields
An amplifier circuit is provided. [0031] [MEANS FOR SOLVING THE PROBLEMS] To achieve the above object
The present inventionThen, the potential of the input terminal is amplified to
In the amplifier circuit that outputs from the output terminal of No. 2,
(Ie, through a series connection or other circuit element, etc.)
A negative resistance circuit connected in series) and a resistance means.
I have. [0032]The source of the negative resistance circuit has a first potential.
Supply terminal (for example, V _CC ) Directly or via switch means
And the drain is connected to the first output terminal and the first output terminal.
A first MOS transistor of a first conductivity type connected to the resistance means;
A transistor and a drain are connected to the first potential supply terminal.
Is connected to the input terminal and the source is connected to the first MOS transistor.
Respectively connected to the gate of the transistor and the second output terminal
A second MOS transistor of the second conductivity type,
Is connected to the source of the second MOS transistor.
Is connected to the drain of the first MOS transistor
Is connected to the second potential supply terminal (eg, GND)
A third MOS transistor of a second conductivity type connected;
have. [0033]The present inventionAccording to the negative resistance circuit and the resistance means
Inverted amplification output with high gain and amplification
And a level-shifted output. [0034] DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS (First Embodiment) FIG.
FIG. 4 is a circuit diagram of a sense circuit showing a first reference example of FIG. this
In the sense circuit, the input terminal IN is connected to the node N11.
The node N11 and a first potential supply terminal (for example, V
_CC) Is connected to the data line load circuit 100.
You. The node N11 and a second potential supply terminal (for example, GN
D), the current-voltage conversion circuit 200 is connected
I have. The current-voltage conversion circuit 200 includes a PMOS 201 and
It is composed of a series circuit of resistance means 210. PMOS
201 has a source at the node N11 and a gate at the node N
12, a drain is connected to one end of the resistance means 210 and an output terminal
OUT, respectively. Of the resistance means 210
The other end is connected to GND. The inverting amplifier 3 is connected to the nodes N11 and N12.
00 input node A_inAnd output node A_outAre each
It is connected. Inverting amplifier 300 is depleted
And a series circuit of a PMOS 301 and a resistor 310.
Has been established. The PMOS 301 has a source of V_CC,
Is the input node A_inThe drain of the resistance means 310
One end and output node A_outAre connected to
You. The other end of the resistance means 310 is connected to GND.
You. Next, the operation will be described. Input terminal IN is V
_CCIs biased to a predetermined level close to. Data line
A constant bias voltage is applied from the load circuit 100 to the input terminal IN.
Style I₁Is flowing (I₁= 0.) or,
From data line load circuit 100 to current-voltage conversion circuit 200
Also has a constant bias current I_TwoIs flowing. This state
Then, the PMOS 201 is designed to be in a saturated state.
I have. For example, the current I flowing out of the input terminal IN
₁Is ΔI₁Only increase. Then, the data line load
The current flowing through the circuit 100 decreases and the input terminal IN (immediately
That is, the level of the node N11) slightly decreases. This is
Amplified by the inverting amplifier 300, the level of the node N12
Bell rises. Therefore, the source voltage of the PMOS 201 is
The gate potential rises and its gate potential rises.
・ Drain voltage is small and conductance is small
It becomes. Since the PMOS 201 is saturated,
The conductance greatly changes, and the current-voltage conversion circuit 20
Current I flowing through 0_TwoIs ΔI_Two(≒ ΔI₁) Only decrease
You. As a result, the potential of the output terminal OUT becomes ΔV = −ΔI_Two
・ R₁₁(However, r₁₁; Only the resistance value of the resistance means 210)
The resistance r₁₁Is appropriately determined and the desired output power
Pressure amplitude can be obtained. On the other hand, the electric current flowing through the data line load circuit 100
Style I_LFor the current I₁Current I_TwoBut
There is no major change as it decreases. Therefore, the input terminal I
The potential of N is kept almost constant. Thus, input
It supports the input current signal while suppressing the voltage amplitude of the terminal IN.
An output signal having a large voltage amplitude can be obtained. The present embodiment has the following advantages. (A) Current-voltage conversion circuit between input terminal IN and GND
Since the path 200 is provided, in a memory circuit or the like,
When a data line is connected to the input terminal IN and used,
Switch means and current-voltage conversion circuit connected to the data line
And 200 are connected in parallel, enough for both
A bias voltage can be applied. Therefore, lower the power supply voltage
However, it is excellent in operation speed and operation margin.
It is excellent in low power supply voltage operation. (B) In the inverting amplifier 300,
Input node A_inMOS transistor connected to
The inversion amplifier 300 is
There is no cutoff, and the bias
Rank V_CCCan be brought close enough. Therefore, the current
The voltage conversion circuit 200 has almost V_CCBias power until full
Voltage and can operate at low power supply voltage.
Can be (C) Controlling the current-voltage conversion circuit 200
Node A of the inverting amplifier 300 _inTimes the signal of
Operation stability because it is obtained directly from the input terminal IN of the road.
Is excellent. Hereinafter, this point will be described in detail. For example, referring to FIG.
100 and the current / voltage conversion circuit 200 as a group.
The path 1 is used, and the inverting amplifier 300 is used as the circuit 2. Circuit 2
Is input to the node N12 and the output is
Mode N11. On the other hand, the input of circuit 2 to circuit 1
Is the node N11, and the output is the node N12. Immediately
That is, the inputs and outputs of the circuits 1 and 2 are cross-connected to each other.
Have been. Here, focusing on the circuit 1, the output of the circuit 1 will be described.
The force (node N11) is applied to its input (node N12).
It has become a source follower. That is, the circuit 1
Since it works as a source follower for Road 2,
The input and output do not become out of phase, and the amplification factor is smaller than 1. Yo
No positive feedback is applied, and the latch
Without the risk of entering or oscillating.
A stable product is obtained. In order to increase the output voltage amplitude,
What is necessary is just to make the value of the resistance means 210 large. sense
In order to increase the gain of the entire circuit, the inverting amplifier 300
Or the current-voltage conversion circuit 200
The bias potential of the gate of the PMOS 201 is properly determined.
Adjustment such as deepening the saturation of the PMOS 201
Just fine. Thus, the magnitude of the output voltage amplitude and the overall circuit
Body gain can be adjusted independently, so desired characteristics can be easily adjusted
Can be obtained. (Second Reference Example) FIG. 5 shows the first reference example shown in FIG.
FIG. 2 is a circuit diagram that further embodies the sense circuit of the reference example of FIG.
Elements common to those in FIG. 1 are denoted by common reference numerals.
You. In this sense circuit, the data line load shown in FIG.
The circuit 100 includes a PMOS1 having a gate connected to GND.
01, and a resistor in the current-voltage conversion circuit 200.
The resistance means 210 is an NMO having a gate and a drain connected to each other.
S211 and the resistance in the inverting amplifier 300
Means 310 is an NMOS in which a gate and a drain are connected.
311. Other configurations are the same as those in FIG.
You. The present embodiment has the following advantages.
You. (1) The resistance means in the inverting amplifier 300 is connected to the gate and the gate.
It is composed of NMOS 311 connected to rain.
The output node A of the inverting amplifier 300_outVoltage amplitude of
Is limited. Therefore, the gain of the entire circuit is small.
However, the dynamic range can be widened. So
The other configuration is basically the same as that of the first reference example.
Thus, as in the first reference example, it has excellent low power supply voltage operation,
It has the advantage of excellent crop stability. (2) This embodiment is the same as the first embodiment.
The magnitude of the output voltage amplitude and the gain of the entire circuit
Can be adjusted vertically. Here, FIG.
This will be specifically described with reference to FIG. First, in FIG. 5, the data line load circuit 1
00 and the current / voltage conversion circuit 200 as a group.
Route 1, its input is node N12, and its output is node
N11. The inverting amplifier 300 is referred to as a circuit 2.
Then, the circuit 1 and the circuit 2 have their inputs and outputs mutually
Cross-connected. FIG. 6 shows the stability of a circuit having such a configuration.
FIG. 9 is an input / output characteristic diagram for determination. The horizontal axis in FIG.
Input potential V of path 1_I1And the output potential V of the circuit 2_O2And
The vertical axis represents the output potential V of the circuit 1._O1And the input potential V of the circuit 2
_I2It is. Curve C₁Is the input / output characteristic curve of the circuit 1
Line C_TwoIs the input / output characteristic curve of the circuit 2. As in the first embodiment, the circuit 1 is connected to the circuit 2
On the other hand, it works as a source follower. Therefore, the characteristic curve
C₁Is the input potential V_I1Rises and the output potential V_O2Also rise
Shape. Circuit 2 is an inverting amplifier 300
And its characteristic curve C_TwoIs the input potential V_I2Appears when
Force potential V_O2Is descending. Therefore, the characteristic curve C
₁And C_TwoIntersect at one operating point P. Thus, dynamic
Since there is only one point P, an extremely stable circuit
can get. (Third Reference Example) FIG. 7 shows a first reference example.
4 shows a third reference example that embodies the sense circuit of FIG.
FIG. 6 is a circuit diagram of a sense circuit, which shares elements with FIGS. 4 and 5.
Common elements are denoted by common reference numerals. This sense circuit is the same as the sense circuit of FIG.
And the same as the sense circuit of FIG.
NMOS 101 for data line load and current-voltage conversion circuit
200 and a configuration difference from the inverting amplifier 300.
Is provided. Inverting amplifier
300A is a depletion type PMOS 301 and NM
It is composed of a series circuit of OS311. PMOS30
1 means the source is V_CCAnd the gate is the input node A_inTo
Rain is output node A_outAre connected to
You. The NMOS 311 has a drain connected to the output node A.
_outAnd the gate is the input node A_inAnd the source is GND
Are connected respectively. Other configurations are the same as in FIG.
It is. In this embodiment, the gate of the NMOS 311 is
Input node A of inverting amplifier 300A _inConnected to
The gain of the inverting amplifier 300A can be increased. Yo
The overall dynamic range of the circuit is rather narrow.
However, the gain of the circuit can be improved. The operation is basically
Are the same as in the first and second reference examples.
Similar advantages are obtained. (Fourth Reference Example) FIG. 8 shows a fourth reference example of the present invention.
FIG. 4 is a circuit diagram of a sense circuit showing a reference example, and includes first to third sense circuits;
Elements common to the elements in FIGS. 4, 5, and 7 showing the embodiment
The primes are assigned common symbols. In this sense circuit, the data shown in FIGS.
Data line load circuit 1 having a different configuration from data line load circuit 100
00A and the same current-voltage conversion circuit 200
And a switching amplifier 300. Data line load circuit 1
00A is the input node L connected to the node N11._inWhen
V_CCAnd an input node between the PMOS 101
Is the input node L_inAnd the output is via node N21.
Level shifter 1 connected to the gate of PMOS 101
02, and Other configurations are the first to third
Since it is the same as the reference example, the basic
The operation is the same. Therefore, the configuration and basic
The description of the operation is omitted, and the following description will be made mainly on the data line load circuit
The characteristics of 00A will be described. FIG. 9 shows the data line load circuit 100A of FIG.
5 is a characteristic diagram showing a load curve of FIG. The horizontal axis in FIG.
De L_inPotential V_LINThe vertical axis represents the data line load circuit 100A.
Current I flowing through PMOS 101 in_LIt is. Solid line song
Line l₁Is a load curve of the data line load circuit 100A.
You. Dashed curve l_TwoAnd l_ThreeWas added for explanation
So the curve l_TwoUses only the PMOS 101 as a load,
Gate potential V_GTo V _G= V_CC-V_SHFWith the load curve
is there. Curve l_ThreeUses only the PMOS 101 as a load,
Gate potential V_GTo V_GIt is a load curve with = 0V.
Voltage V_SHFIs the shift voltage by the level shifter 102
Yes, | V_SHF| ≧ | V_TP| For example, V_LIN= V_CCThen
Is applied to the voltage V by the level shifter 102._SHFOnly
The PMOS 101 through the node N21.
Output to the gate. Therefore, the game of the PMOS 101
Potential V_GIs V_G= V_CC-V_SHFIt becomes. The potential V_LINDecreases, the gate potential
V_GAlso decreases, the current flowing through the PMOS 101
I_LWill increase. Further, the potential V_LINDecreases and V
_LIN<V_SHFThen V_G= 0V and the potential V_LIN
The current I_LBecomes constant. That
Therefore, the load curve l₁Is the potential V_LINIs V_CCIn the area near
Is the curve l_TwoTangent in the unsaturated region at
Characteristic and the potential V _LINDecreases and the curve l_ThreeApproach
Shows a form that saturates. Thus, the data line negative
In the load circuit 100A as a whole, an apparently unsaturated region is formed.
Acts like an extended MOS transistor. Here, the curve l_ThreeIs the conventional data line load
Considering that it is equivalent to the characteristics of the road, the data of this reference example
In the line load circuit 100A, the current value at which the characteristic starts to be saturated is
When they are equal, the equivalent resistance value is larger than the conventional one.
I can do it. That is, the input node L_inVoltage swing
When the maximum allowable width is designed to be equal,
As a result, a minute current signal can be reliably sensed.
On the other hand, the equivalent resistance value of the data line load circuit is made equal.
Then, the characteristics of this reference example are better than those of the conventional one.
The current value at which the saturation starts can be increased. As described above, the present embodiment has the following advantages.
Have a point. (I) The data line load circuit 100A is a PMOS 101
And the level shifter 102,
Has improved linearity and wider dynamic range than before.
A good sense circuit can be obtained. The operation of the level shifter 102
As a result, the potential of the input terminal IN becomes V_CCEven the load
PMOS 101 does not cut off.
Set the bias potential of the child IN to V_CCCan be close to
Therefore, even if the dynamic range is wide,
The advantage of good operation is not impaired. (Ii) The sense circuit of the present embodiment has the first
Instead of the data line load circuit 100 of the reference example,
A data line load circuit 100A is provided.
Identical. Therefore, similarly to the first reference example, the low power supply
Excellent pressure operation, excellent operation stability, and desired characteristics
It has the advantage of being easily obtained. (Iii) Data line load circuit 10 of the present embodiment
The use of 0A is not only for sense circuits, but also for improved linearity.
Various circuit loads that require improved current-voltage characteristics
It is also effective to use it for columns. FIG. 10 shows a fifth embodiment of the present invention.
FIG. 4 is a circuit diagram of a sense circuit showing a reference example of the first to fourth embodiments.
4, 5, 7, and 8 showing reference examples of FIG.
Common elements are denoted by common reference numerals. This sense circuit has the same data lines as those in FIG.
Load PMOS 101 and current-voltage conversion similar to FIG.
It comprises a circuit 200 and an amplifier circuit 400.
The data line load PMOS 101 is connected to the input terminals IN and V
_CCBetween the input terminal IN and GND.
The current-voltage conversion circuit 200 is connected between them. Current
The voltage conversion circuit 200 is connected to the PMOS 201 as in FIG.
It is composed of a series circuit with the resistance means 210,
The connection point is connected to the output terminal OUT. The amplifier circuit 400 has a node connected to the input terminal IN.
Input node A connected via N31_inAnd PMOS
201 connected to the gate of the gate 201 via the node N32.
Output node A of_out1To the gate of the PMOS 101
Output node A connected via node N33_out2When
have. This amplifying circuit 400 has a level shifter shown in FIG.
The lid 102 and the inverting amplifier 300 are realized by one circuit.
Input node A_inWith gate connected to
And the input node A_inNige
The NMOS 402 connected to the gate and the NMOS 411,
412 and a current mirror circuit 410 comprising
Have been. The PMOS 401 has a source of V_CCTo the dress
Is the current input node I of the current mirror circuit 410_in
Are connected respectively. NMOS 402 is a drain
Inn is V_CCThe source is the current mirror circuit 410
Outflow node I_outAnd a second output node A_out2Niso
Each is connected. The current mirror circuit 410 comprises
NMOS 411 and 412 connected to GND
And each gate is connected to the first output node A_out1Connected to
Have been. The drain and gate of the NMOS 411 are
Flow input node I_inIt is connected to the. NMOS 412
The drain is the current output node I_outIt is connected to the. Next, (1) the operation of the amplifier circuit 400 and
(2) Input node A_inAnd the first output node A_out2
(3) Operation of the entire sense circuit and
The advantages of the example will be described. (1) Operation of amplifier circuit 400 Input node A_inAnd output node A_out1Between the PMO
Connected with an inverting amplifier consisting of S401 and NMOS 411
This part is the same as the inverting amplifier 300 of FIG.
It is a structure of. Therefore, output node A_out1Input
Code A_in(That is, the voltage signal at the input terminal IN) is inverted and amplified.
Is output. (2) Input node A_inPotential and the second output
Force node A_out2Relation to potential FIG. 11 shows an output node A of the amplifier circuit 400 of FIG._out2
FIG. 6 is an operation characteristic diagram for explaining the operation of FIG. Vertical of this figure
The axis is current and the horizontal axis is voltage. For example, NMOS 411
And 412 have equal abilities. In FIG. 11, the curve C_NaOutputs the horizontal axis
Node A_out2The vertical axis represents the potential flowing through the NMOS 402.
Given the size of the flow, input node A_inPotential of V_aAnd
4 is a current-voltage characteristic curve of the NMOS 402 at the time. FIG.
As shown in FIG._out2Is V_a-V
_TNNAt lower levels, current begins to flow. Curve C_Nb
Is the input node A_inPotential of V_bNMOS when
402 is a current-voltage characteristic curve of FIG.
Curve C_NaIs the same as In this case, output node A
_out2Is V_b-V_TNNAt lower levels, current will flow
start. Curve l_aAnd l_bIs the output node A on the horizontal axis
_out2And the vertical axis represents the current flowing through the NMOS 412.
Current-voltage characteristic curve of the NMOS 412 when the size is
Line. Curve l_aIs the input node A_inIs V_aso
At some point, the curve l_bIs the input node A_inNo electricity
Place is V_bIt is when it is. Curve C_bIs the horizontal axis
Input node A_inAnd the vertical axis flows through the PMOS 401.
Current-voltage characteristics of the PMOS 401 when the current is
It is a curve. For example, input node A_inIs V_aIn
The current flowing through the PMOS 401 is I_aThen
This current I_aAlso flows to the NMOS 411. NMOS4
11 and 412 constitute a current mirror circuit 410
Therefore, even in the NMOS 412, the current I_aFlows
Will be. Therefore, the characteristic curve l of the NMOS 412 _a
And characteristic curve C of NMOS 402_NaMeans that the current value is I_aWhen
Point P_aMeet at This point P_aIs the input node A_inof
Potential is V_aOutput node A when_out2Operating point
The operating point P_aVoltage value V_outaIs the output node A_out2of
Potential. Similarly, input node A_inIs V_bIn
The current flowing through the PMOS 401 is I_bThen
At this time, the current flowing through the NMOS 412 is also I_bBecomes
The characteristic curve l of the NMOS 412_bAnd NMOS 402
Characteristic curve C_NbMeans that the current value is I_bPoint P_bExchanged in
You. This point P_bIs the input node A_inIs V_bIs
Output node A_out2Operating point, and the voltage value V
_outbIs the output node A_out2Potential. As described above, the amplifying circuit 4 in the present reference example
In 00, only the input voltage signal is level shifted.
Input voltage amplitude V_a-V_bIs amplified and V_outa-V
_outb(> V_a-V_b) Is obtained. The input voltage amplitude is amplified as described above.
Is that the NMOS 412 is saturated,
Input node A_inIs V_CCMust be close enough to
You. However, this is due to the operating conditions of the sense circuit of this reference example.
And does not restrict the operation. Next, the output voltage of the conventional level shifter
The amplitude is compared with that of the present reference example. For example, NMO
S412 corresponds to the current I_aTo be a constant current source
I do. Then, input node A_inIs V_bWhen
Output node A of_out2Operating point is P_bbAnd the potential is V
_outbbTherefore, the output voltage amplitude is V_outa-V_outbbWhen
It is smaller than that of this reference example. That is, the reference example is increased.
In the width circuit 400, signals having the same input voltage amplitude
On the other hand, a laser with a larger output voltage amplitude than the conventional one
A bell shift signal is obtained. (3) Operation of the entire sense circuit and this reference example
Advantage of First output node A of amplifier circuit 400_out1Input signal
The voltage output signal obtained by inverting and amplifying the voltage signal of signal IN is obtained.
This is the PMOS 201 in the current-voltage conversion circuit 200.
Drive the gate. On the other hand, the operation of the amplifier circuit 400
And the voltage signal of the input terminal IN is level-shifted, and
An amplified level-shifted signal is obtained, which
The gate of the PMOS 101 for data line load is controlled.
Therefore, the operation of the entire sense circuit is basically the fourth operation.
8 is the same as that of FIG.
With excellent dynamic stability and dynamic stability.
A wide sense circuit can be obtained. Further, in the present reference example, the size is larger than the conventional one.
Since a highly amplified level shift output is obtained,
In addition to the data line shown in FIG.
Wider dynamic range with improved load characteristics
Things are obtained. In addition, in this reference example, one amplification cycle
The path 400 provides the inverted amplified output and level of the input voltage signal.
A shift output can be obtained, so an inverting amplifier is provided separately
The number of elements of the sense circuit can be smaller than that of the circuit. The application of the amplifier circuit 400 of this embodiment is as follows.
It is not limited to use in sense circuits,
Various fields that require soft output, such as interface
In a power circuit, etc., it is effective to use as a level shifter.
You. (Sixth Reference Example) FIG. 12 shows a sixth embodiment of the present invention.
FIG. 2 is a circuit diagram of a sense circuit showing a reference example of the first embodiment;
Elements common to the elements in FIG.
Have been. In this sense circuit, the same data as in FIG.
FIG. 4 shows a line load circuit 100 and a current-voltage conversion circuit 200;
And an inverting amplifier 300B having a different configuration from
You. The inverting amplifier 300B is connected to the input terminal IN.
Input node A_inConnected to the gate of the PMOS 201
Output node A_outAnd has a resistance to the negative resistance circuit 320.
And an anti-means 310. The negative resistance circuit 320 is connected to the control terminal G and the
1, a second input / output terminal S, D, and the control terminal G
Force node A_inAnd the first input / output terminal S_CCThe second
Input / output terminal D is one terminal of the resistance means 310 and the output
Node A_outAre connected respectively. Resistance means 3
The other terminal of 10 is connected to GND. Negative
The resistance circuit 320 is connected between the first and second input / output terminals S and D.
The connected PMOS 321 and V_CCConnected in series between
And NMOSs 322 and 323 connected to each other.
You. The source of the PMOS 321 is the first input / output
The terminal S has a gate connected to the node N40, and a drain connected to the second node N40.
The input / output terminals D are connected to each other. PMOS3
22 has a drain V_CCThe gate is connected to the control terminal G,
Are connected to the node N40, respectively. NM
The OS 323 has a drain connected to the node N40 and a gate connected to the node N40.
2 is connected to the input / output terminal D and the source is connected to GND.
Have been. The other parts are described in the first reference example.
Is the same as FIG. Next, the sense circuit of this reference example
Will be described with reference to FIGS. Ma
The operation of the inverting amplifier 300B will now be described with reference to FIG.
explain. FIG. 13 shows the output node of the inverting amplifier 300B.
Do A_outFIG. The vertical axis in this figure is
Between the first and second input / output terminals S and D of the negative resistance circuit 320
And the current flowing through the resistance means 310.
The axis is the output node A_outPotential. In FIG. 13, the curve NR_aIs the input no
Do A_inPotential of V_aOf the negative resistance circuit 320
In the current-voltage characteristic curve between the first and second input / output terminals S and D,
is there. Curve NR_bIs the input node A_inPotential of V_bage
The current-voltage characteristic curve of the negative resistance circuit 320 when the
You. Any of these curves NR_a, NR_bAlso the output node
A_outThe current increases once as the potential of
After that, it begins to decrease at some point. Curve l in FIG._RIs the resistance means 310
For example, using an NMOS with a gate and a drain connected
The current-voltage characteristic curve of the resistance means 310
You. Input node A_inIs V_aCircuit behavior when
The score is the curve NR_aAnd the curve l_RIntersection P with_aBecome
Voltage value at the time of_outaIs the output node A_outThe potential of
You. On the other hand, input node A_inIs V_bTimes when
The operating point of the road is represented by curve NR_bAnd the curve l_RIntersection P with_bTona
The voltage value V at that time_outbIs the output node V_outPotential of
It becomes. That is, the input voltage amplitude V_a-V_bOutput power for
Pressure amplitude V_outa-V_{ou tb}Is obtained. Next, the gate of the inverting amplifier 300B of the present embodiment will be described.
4 and FIG. 4 showing the first reference example. For example, the negative resistance circuit 320 shown in FIG.
When switching to depletion type PMOS, the current and voltage
The characteristic is the curve C shown by the broken line in FIG._aaAnd C_bblike
Become. As a result, input node A_inIs V_aIs
Operating point is P_aaAnd the input node A_inPotential of
Is V_b, The operating point of the circuit is P_bbIt becomes. That
Output voltage amplitude is V_aa-V_bb(<V_a-V_b)
Therefore, the size is smaller than that using the negative resistance circuit 320. As described above, in this embodiment, the inverting amplifier 3
00B is composed of the negative resistance circuit 320 and the resistance means 310
As a result, an inverting amplifier having a higher gain can be obtained.
A control terminal is connected to a node N40 of the negative resistance circuit 320.
A threshold voltage V at least higher than the potential of G_TNNMinute
A lower potential is obtained. Therefore, when the input terminal IN is V_CC
Even if the potential is negative, the negative resistance circuit 320 is cut off.
Instead of using a depletion-type PMOS.
A wide dynamic range can be obtained. So, for example
In order to obtain a depletion type MOS transistor,
The potential of the input terminal IN without performing the on-implantation process
To V_CCCan be biased nearby. Therefore, low power supply voltage operation
A sense circuit excellent in the above is obtained. Next, the operation of the inverting amplifier 300B will be described.
The stability of the operation will be described with reference to FIG. FIG.
Explains the stability of the operation of the inverting amplifier 300B in FIG.
FIG. 13 is a circuit diagram for performing the same operation as the element in FIG.
Are denoted by common symbols. Here, NMOS 322 and NMOS 323
Are collectively referred to as a circuit 1, and the input of the circuit 1 is
And the output of the circuit 1 is referred to as a node N40. What
The node N41 is biased to an appropriate potential
Shall be. Further, the PMOS 321 and the resistance means 310 are connected.
Into a circuit 2 whose input is the node N40,
The output is a node N42. In addition, the resistance means 310
It consists of NMOS with gate and drain connected.
And As is clear from FIG. 14, the circuit 1 and the circuit 2
Have their inputs and outputs cross-connected to each other. FIG. 15 shows the stability of the operation of such a circuit.
FIG. 4 is an input / output characteristic diagram of circuits 1 and 2 for determining
You. The vertical axis of FIG. 15 indicates the output potential V of the circuit 1._O1When
Input potential V of circuit 2_I1And the horizontal axis represents the input power of circuit 1.
Rank V_I1And the output potential V of the circuit 2_O2It is. Curve C₁Is a circuit
1 input / output characteristic curve, curve C_TwoIs the input / output characteristic of circuit 2
Line. In the circuit 1, the input (node N42)
Of the output (node N40) as the potential of
Rises and the input potential becomes V_TN, The output potential becomes V_CC
-V _TNNAnd becomes constant. On the other hand, in circuit 2
Rises as the potential of its input (node N40) rises.
The potential of the output (node N42) decreases,
Is V_CC− | V_TP|, The output potential is V_TNOne
It will be fixed. Therefore, each characteristic curve C₁, C_TwoIs shown in FIG.
It crosses at one operating point P as shown. Here, the output of the circuit 1 (node N40) is
V_CC-V_TNNNote the area where At this time, NMO
S322 has a large back bias
And V _TNN> V_TNIt becomes. Therefore, V_TN≒ ｜ V_TP|
If such manufacturing conditions are determined, V_TNN> | V_TP|
Therefore, the input / output characteristic curves do not intersect at a plurality of points. This
These manufacturing conditions are the same as the manufacturing conditions for general CMOS integrated circuits.
It is a very ordinary thing. Therefore, in this reference example,
No special manufacturing process is required and high gain
Inverting amplifier 300B is obtained. Next, the entire sense circuit of this embodiment is described.
The operation and advantages of the present embodiment over the conventional example will be described. In the sense circuit of this embodiment, the first embodiment
Is different from the inverting amplifier 300 of FIG.
An inverting amplifier 300B is provided, and other configurations are the same as those in FIG.
One. Moreover, the inverting amplifier 300B has its input node
Code A_inIs V_CCDoes not cut off even if biased nearby
No. Therefore, as in the first reference example, low power supply voltage operation is excellent.
Thus, a sense circuit having excellent operation stability can be obtained. That
In addition, the amplitude of the output amplitude and the gain of the entire circuit can be adjusted independently.
An adjustable sense circuit is obtained. Further, in this embodiment, in addition to these advantages,
In addition, the following advantages can be obtained. That is, the inverting amplifier 3
00B is constituted by a negative resistance circuit 320 and a resistance means 310.
Therefore, a sensor having a larger gain than that of the first reference example.
Circuit is obtained. Besides, especially depletion type MO
No manufacturing process is required because no S transistor is required
A sense circuit is obtained. (Embodiment) FIG. 1 shows an embodiment of the present invention.
FIG. 14 is a circuit diagram of the sense circuit shown, showing a fifth reference example.
Elements common to the elements in 10 are given the same reference numerals.
You. In this sense circuit, the sense circuit shown in FIG.
Has a configuration different from that of the amplifier circuit 400
The only difference is that an amplifier circuit 400A is provided.
You. The amplifier circuit 400A includes a control terminal G, first and second input terminals.
Negative resistance circuit having output terminals S, D and output terminal X
420 and an NMOS 430 for the resistance means.
I have. The control terminal G of the negative resistance circuit 420 has an amplification circuit.
Input node A of road 400A_inThe output terminal X is connected to the amplification circuit.
Second output node A of path 400A_out2Connected to each
Have been. First input / output terminal S of negative resistance circuit 420
Is V_CCIt is connected to the. The second input / output terminal D is
Gate and drain of MOS 430 and amplifying circuit 400
A first output node A of A_outAnd connected to. NM
The source of the OS 430 is connected to GND. This negative resistance circuit 420 is a sixth reference example.
Similarly to the negative resistance circuit 320 in FIG.
S421 and NMOSs 422 and 423.
The point where the gate of the MOS 421 is connected to the output terminal X
Only the difference from FIG. Next, the operation of the amplifier circuit 400A will be described.
You. First, input node A_inAnd the first output node A_out1of
Focusing only on the relationship, this part shows the sixth reference example
Since the configuration is the same as that of the inverting amplifier 300B of FIG.
It operates similarly to the amplifier 300B. That is, the first output node
Code A_out1At the input node A_inInput voltage change
Is obtained by inversion amplification. Next, the input node A_inThe second output for
Node A_outThe operation of the circuit will be described focusing on the relationship.
To explain this operation, FIG. 10 shows a fifth reference example.
And the depletion type PMOS 401 is
The circuit replaced with the negative resistance circuit 440 as shown in the road
Think. The negative resistance circuit 440 is a diagram showing a sixth reference example.
12 has the same circuit configuration as the negative resistance circuit 320 in FIG.
A control terminal G, and first and second input / output terminals S and D;
It is composed of a PMOS 441 and NMOSs 442 and 443.
ing. First, the negative resistance circuit 440 and the NMOS 41
Paying attention to the portion consisting of 1 and FIG.
It has the same configuration as the pump 300B. Therefore, the second input / output
Terminal D has an input node A_inLarge change in voltage
Obtained width. As described with reference to FIG.
The gain of the amplifier part uses the depletion type PMOS.
It can be larger than what you have. This second input / output terminal D
Since the gate of the NMOS 412 is controlled, FIG.
Circuit 6 is configured using a depletion-type PMOS.
Of the voltage amplitude larger than the amplified circuit 400 of FIG.
It is possible to obtain a shift output. Here, in FIG.
Capability (eg constant gate voltage and drain-source
Ability defined by the drain current that can be flowed by the voltage)
And the capacity of the NMOS 402 are equalized.
Make OS443 capability and NMOS 412 capability equal
Then, the gate potential of the PMOS 441 and the second output node
A_out2Are always equal. In this way, more
A simplified equivalent circuit is obtained. That is, PM in FIG.
OS441 Gate and Second Output Node A_out2The show
And the NMOS 442 and the NMOS 402
And one NMOS 442A.
3 and NMOS 412 replaced by one NMOS 443A
Then, an equivalent circuit as shown in FIG. 17 is obtained. this
The circuit of FIG. 17 is different from the amplifier circuit of the present embodiment.
However, it is the same as that of the amplifier circuit 400A of FIG. As described above, in the present embodiment, the following
Has advantages. (A) In the amplifier circuit 400A of the present embodiment, FIG.
An inverted amplified output having a larger gain than the amplifier circuit 400;
And a width-shifted output. Further
, A negative resistance circuit 420 is connected to the input terminal IN.
Therefore, the input terminal IN is connected to V_CCEven when biased close,
The circuit does not cut off. Therefore, the fifth reference
As in the example shown in FIG.
Excellent stability and wide dynamic range
You. Moreover, it uses a depletion type MOS transistor.
A sense circuit that does not need to be provided is obtained. (B) In the present embodiment, the negative resistance circuit 4
20 from the gate of the PMOS 421 constituting
Shift output, so a sense circuit with a small number of elements can be used.
Obtainable. This is an increase in FIG. 1 of the present embodiment.
Compare the width circuit 400A with the circuits of FIGS.
It is clear if you do. (C) The amplification circuit 400A of the present embodiment
Applications are not limited to sense circuits, but in various fields
Effective as a level shifter or inverting amplifier
You. (Modification) The present invention is not limited to the above embodiment and the like.
However, various modifications are possible. Its variants and
For example, there is the following. (I) In the above embodiment and the like, the NMO
S to PMOS, PMOS to NMOS, V_CCTo GND
And GND to V_CCIs the same as the above embodiment, etc.
A circuit having similar effects can be obtained. (Ii) The current that constantly flows during operation.
In the flow path (for example, the current-voltage conversion circuit 200,...)
If the switch is inserted in series, power consumption during standby can be reduced.
Power can be reduced. (Iii) A steady current path during operation (for example,
, And the potential supply terminal V_CC
Between the first switch means and the first switch means is inserted in series,
A second switch between the current path and the potential supply terminal GND;
Means in series form, said first switch means and a second
A third switch means is provided at a connection point between the second switch and the second switch.
And a predetermined potential is supplied to the third switch means.
Potential supply means may be provided. In this way, wait
Power consumption during standby and the desired connection during standby
Whether the points can be precharged to a predetermined potential in advance
Sense circuit that can quickly transition from the standby state to the operating state
Is obtained. Also, the first switch means is, for example, a
The transistor may also serve as a data line load transistor. [0118] As described in detail above,The present inventionBy
In other words, the amplifier circuit has a negative resistance circuit and resistance means.
Therefore, the amplified output and the amplified
And a level shift output.Furthermore, input
Since a negative resistance circuit is connected to the terminal,
For example, V _CC Circuit cutoff even when biased close
I can't. Therefore, it is excellent in low power supply voltage operation
Excellent stability and wide dynamic range
You.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a circuit diagram of a sense circuit showing an embodiment of the present invention. FIG. 2 is a main part circuit diagram of a memory circuit including a conventional sense circuit. FIG. 3 is an input / output characteristic diagram of the circuit 1 and the circuit 2 of FIG. 2; FIG. 4 is a circuit diagram of a sense circuit showing a first reference example of the present invention. FIG. 5 is a circuit diagram of a sense circuit showing a second reference example of the present invention. FIG. 6 is an input / output characteristic diagram of the circuit 1 and the circuit 2 of FIG. 5; FIG. 7 is a circuit diagram of a sense circuit showing a third reference example of the present invention. FIG. 8 is a circuit diagram of a sense circuit showing a fourth reference example of the present invention. FIG. 9 is a characteristic diagram of the data line load circuit 100A of FIG. FIG. 10 is a circuit diagram of a sense circuit showing a fifth reference example of the present invention. 11 is an operation characteristic diagram of the amplifier circuit 400 of FIG. FIG. 12 is a circuit diagram of a sense circuit showing a sixth reference example of the present invention. 13 is an operation characteristic diagram of the inverting amplifier 300B of FIG. FIG. 14 is an operation explanatory diagram of the inverting amplifier 300B of FIG. 12; 15 is an input / output characteristic diagram of the circuits 1 and 2 of FIG. FIG. 16 is a circuit diagram showing a modified circuit of the amplifier circuit 400 of FIG. 17 is an equivalent circuit diagram of FIG. [Description of Signs] 100, 100A Data line load circuit 101 PMOS 102 Level shifter 200 Current-voltage conversion circuit 201 PMOS 210 Resistance means 211 NMOS 300, 300A, 300B Inverting amplifier 301 Depletion type PMOS 310 Resistance means 311 NMOS 320 Negative resistance circuit 321 PMOS 322, 323 NMOS 400, 400A Amplifying circuit 401 Depletion type PMOS 402 NMOS 410 Current mirror circuit 411, 412 NMOS 420, 440 Negative resistance circuit 421, 441 PMOS 422, 423, 442, 443 NMOS

Continuation of the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G11C 11/40-11/4197 G11C 16/06

Claims (1)

(57) [Claim 1] Amplifying the potential of the input terminal to make the first and second
An amplifier circuit that outputs from the output terminal of the above, comprising a negative resistance circuit and a resistance means connected in series, wherein the negative resistance circuit has a source directly to the first potential supply terminal or a switch means.
And the drain is connected to the first output terminal and the first output terminal.
A first MOS transistor of a first conductivity type connected to the resistance means;
A transistor and a drain are connected to the first potential supply terminal, and a gate is connected to the input terminal.
A source is connected to the source of the first MOS transistor.
And the second output terminal respectively connected to the second output terminal.
A second MOS transistor of a conduction type and a drain connected to the source of the second MOS transistor;
The gate is connected to the drain of the first MOS transistor,
A second source whose source is connected to the second potential supply terminal;
Amplifier circuit and having a third MOS transistor conductivity type.