JP3222235B2 - Sense circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a read only memory (hereinafter referred to as a ROM), a static random
In a memory circuit such as an access memory (hereinafter referred to as an SRAM) or a dynamic random access memory (hereinafter referred to as a DRAM), a single-ended circuit capable of detecting and amplifying a current of a data line or the like to enable high-speed reading. it relates to the sense of times passage for the form, or the like.

[0002]

2. Description of the Related Art Conventionally, techniques in such a field include:
For example, there is one described in the following literature. Reference 1: ELECTRONICS LETTERS, 23 [13] (1987-6-18) (USA) C. TEMES, W.S. H. KI "FAST CMOS CURRENT AM PLIFIER AND BUFFER STAGE" P.696-697 Literature 2; IEEE Journal of Solid-State Circuits (IEEE JOURNAL OF SOLID-STATE CIRCUITS), 26 [4] (1991-4) (U.S.A.) Seevinck, etc. “Current-Mode Techniques for High-Speed VLSI Circuits with Application to Current Sense Amplifier for CMOS SRAM ^, s”, p. Are more specifically described. FIG. 2 is a main part circuit diagram of a memory circuit including a conventional sense circuit described in the above-mentioned references 1 and 2. In this memory circuit, a plurality of switch means 1 are commonly connected to a data line DL, and the input terminal IN of the sense circuit 10 is connected to the data line DL. Although not shown, the output terminal OUT of the sense circuit 10 is connected to the next-stage voltage differential amplifier. The switch means 1 is, for example, a memory circuit having R
In the case of OM, it is the memory cell itself. In the case where the memory circuit is a DRAM, the switch unit 1 includes an N-channel MOS transistor (hereinafter, referred to as an N-channel MOS transistor) connected in series between the data line DL and a second potential supply terminal (for example, ground GND).
(Referred to as NMOS) 1a and 1b. NMO
The gate of S1a is connected to the column selection line CL, and the gate of NMOS 1b is connected to the bit line BL. In general, in a DRAM, the data line DL is a pair line that performs a complementary operation.
Another set of data lines DL and sense circuits 10 exist,
The output terminals OUT of the two sense circuits 10 are connected to a pair of input terminals of the next-stage voltage differential amplifier, but are omitted in FIG. 2 for simplicity of description.

The sense circuit 10 includes a data line load circuit 11
And a current-voltage conversion circuit 12 and an inverting amplifier 13. The data line load circuit 11 includes a P-channel MOS transistor (hereinafter, referred to as PMO) having a gate connected to GND.
S), the source of which is a first potential supply terminal (for example, V _CC ) and the drain of which is an input terminal IN.
Connected to each other. The current-voltage conversion circuit 12
PMOS connected in series between input terminal IN and GND
12a and an NMOS 12b. PMOS
12a, the source is the input terminal IN and the gate is the node N
2, the drain is connected to the output terminal OUT and the node N1, respectively. The NMOS 12b has a drain and a gate connected to the node N1, and a source connected to the GND, respectively.

[0004] nodes N1, N2, the input node A _in and an output node A _out of the inverting amplifier 13 are respectively connected. The inverting amplifier 13 includes a PMOS 13a and an NMOS 13b connected in series between V _CC and GND. The PMOS 13a has a source connected to V _CC , and a gate and a drain connected to the output node A _out . The NMOS 13b has a drain connected to the output node A.
_out , the gate is connected to the input node _Ain , and the source is connected to GND.

Next, the operation will be described. The PMOS 11a in the data line load circuit 11 operates non-saturated. That is,
The data line DL is biased to a high potential near V _CC ,
The bias voltage is applied to the current-voltage conversion circuit 12 via the input terminal IN. For example, when one selected switch means 1 is turned on and a current ΔI flows to the data line DL, the switch means 1 and the current-voltage conversion circuit 12 are connected in parallel to the data line DL. , The bias current flowing into the current-voltage conversion circuit 12 is ΔIa (ａ
ΔI). The decrease in the bias current is converted into a voltage by the current-voltage conversion circuit 12, and an output voltage is output from the output terminal OUT. The current / voltage conversion of the current / voltage conversion circuit 12 is performed as follows. That is, when the bias current flowing through the current-voltage conversion circuit 12 decreases, the voltage drop of the NMOS 12b acting as the resistance means decreases, and the node N1 which is also the input of the inverting amplifier 13
As a result, the potential of the node N2, which is the output of the inverting amplifier 13, rises, and the conductance of the PMOS 12a decreases. Therefore, the current flowing through the current-voltage conversion circuit 12 is reduced to a smaller value. That is, positive feedback is applied to the current-voltage conversion circuit 12, and the output terminal OUT
Has a large voltage amplitude.

On the other hand, paying attention to the data line load circuit 11, the current flowing through the current-voltage conversion circuit 12 decreases as the current flowing to the data line DL increases. Therefore, the change in the current flowing through the data line load circuit 11 is small, and the change in the potential of the data line DL can be reduced. As described above, in the conventional memory circuit, the data line load circuit 11 including the PMOS 11a whose gate is connected to GND is provided between the input terminal IN and V _CC, and the current is supplied between the input terminal IN and GND. A voltage conversion circuit 12 is provided, and the current-voltage conversion circuit 12 and the switch unit 1 connected to the data line DL are connected in parallel. Therefore, the current-voltage conversion circuit 1
Since a large bias voltage is applied to 2, a sufficient operation margin and operation speed can be obtained even if the operation voltage is lowered (that is, excellent in low power supply voltage operation). In addition, since the input of the inverting amplifier 13 for controlling the current-voltage conversion circuit 12 is obtained directly from the output terminal OUT, a positive feedback is applied to the entire sense circuit 10, so that the input terminal IN
Large gain can be obtained while suppressing the potential change of In Reference 1, in order to obtain the above operation stably, the ratio of the capacity of the NMOSs 12b and 13b and the PMOS
It is stated that it is necessary to make the capacity ratio of 12a and 13a equal.

[0007]

However, in the conventional circuit, it is not easy to determine (a) each circuit constant so as to operate stably, and (b) especially when the data line DL is used for a DRAM. Has a problem that the voltage amplitude cannot be suppressed sufficiently small. Hereinafter, the problem will be described. (A) Difficulty in Determining Circuit Constants for Stable Operation First, the problem that it is difficult to obtain a circuit that operates stably will be described. For example, in FIG. 2, the data line load circuit 11 and the current-voltage conversion circuit 12 are regarded as one unit circuit (hereinafter, referred to as a circuit 1), and the inverting amplifier 13 is referred to as a circuit 2. Assuming that the input of the circuit 1 is the node N2 and the output is the node N1, the circuit 1 functions as an inverting amplifier. That is, the output of the first inverting amplifier (circuit 1) is input to the second inverting amplifier (circuit 2), and the output of the second inverting amplifier (circuit 2) is input to the first inverting amplifier (circuit 1). Has been entered.

FIG. 3 is an input / output characteristic diagram of a circuit 1 and a circuit 2 for determining the stability of such a circuit. In FIG. 3, the horizontal axis represents the input potential V _I1 of the circuit ₁ and the output potential V
_O2 is taken, and the vertical axis represents the output potential V _O1 of the circuit ₁ and the input potential V _{I2 of the} circuit 2. The curve C _{1 in} FIG.
And the curve C ₂ is the input / output characteristic curve of the circuit 2. Next, each characteristic will be described. For the sake of simplicity, the threshold voltage of the enhancement NMOS is abbreviated as V _TN and the threshold voltage of the enhancement PMOS is abbreviated as V _TP (<0). In the following description, unless otherwise specified, all transistors are enhancement-type transistors. Sense circuit 10
In the circuit 1, the potential of the output node N1 decreases as the potential of the input node N2 increases. Then, when the input potential reaches V _CC- | V _TP |
Circuit 1 is cut off. At this time, the output potential of the circuit 1 is V _TN . On the other hand, in the circuit 2, as the potential of the input node N1 decreases, the potential of the output node N2 increases. When the potential of this input reaches V _TN , the circuit 2 cuts off and the output potential at this time becomes V _TN.
CC− | V _TP |. Therefore, the input / output characteristic curves C ₁ and C ₂ not only intersect at the operating point P but also at other points Q. As described above, in the conventional circuit, since there are a plurality of operating points P and Q, there is a large possibility that the latch enters a holding state or oscillates, and it is difficult to obtain a stable operation.

Here, the input / output characteristic curves C ₁ and C _{2 correspond} to the point Q
In a way to avoid contact, the PMOS13a source circuit 2 (inverting amplifier 13), in place of V _CC,
It is conceivable to apply a slightly lower potential V _REF from V _CC. However, it is not easy to generate and stably supply a potential such that V _CC -V _REF → 0. Moreover, if the difference between V _REF and V _CC is too small, the circuit may oscillate due to noise or the like. On the other hand, it is easy to generate a potential having a relatively large difference from V _CC such that V _CC -V _TP = V _REF . However, when such a potential V _REF is applied to the source of the PMOS 13a, the symmetry of the circuit constants of the current-voltage conversion circuit 12 and the inverting amplifier 13 deteriorates. If the determination is made only as described in 1, the sufficient amplification cannot be performed. Further, in the conventional configuration, if the output amplitude of the sense circuit 10 is to be increased, the output amplitude of the inverting amplifier 13 also increases, and there is a problem that the loop gain of the positive feedback becomes too high.
In other words, there is a problem that the output voltage amplitude and the circuit gain cannot be adjusted independently, and application to various fields has not been easy.

(B) Difficulty in Suppressing Data Line Voltage Amplitude When Used in DRAM Next, a problem that the voltage amplitude of the data line DL cannot be suppressed sufficiently small when used in a DRAM will be described. Generally, in a DRAM, the voltage amplitude of a bit line pair immediately after a word line is activated is small, and therefore, the change in current flowing through data line DL is extremely small. On the other hand, as in the column address strobe (CAS) access operation in the page mode, the voltage amplitude of the bit line pair is large at the time when a sufficient time has elapsed since the activation of the word line, and the data The change in the current flowing through the line DL becomes large. That is, DRAM
, A sense circuit having a wide dynamic range is required. In the conventional configuration, the data line load circuit 1
1 is composed of the PMOS 11a whose gate is connected to GND, and therefore has the following problem. That is, when the performance of the PMOS 11a is determined so that reading can be performed reliably at the time when the voltage amplitude of the bit line pair is small, the saturation of the PMOS 11a starts at the time of the reading operation in the state where the voltage amplitude of the bit line pair is large. As a result, the potential change of the data line DL becomes unnecessarily large. For this reason, in the related art, there is a problem that the reading of the next address is delayed or the operation of the sense circuit 10 becomes unstable.

On the other hand, the document 2 also discloses an example in which an NMOS having a gate and a drain connected is used as the data line load circuit 11. In such a configuration, the load curve does not sharply bend, so that the dynamic range can be widened. However, when such a data line load circuit 11 is used, the bias voltage is applied to the current-voltage conversion circuit 12 by V _CC −V _TNN (where V _TNN is the threshold voltage of the NMOS including the body effect, and V _TNN ≫ V _TN )
Can be applied only up to For this reason, especially in the low power supply voltage operation, V _CC ≫V _CC -V _TNN , resulting in a large inconvenience in the operation speed and the operation margin. The present invention
The problem with the prior art is that the input of the inverting amplifier 13 for controlling the current-to-voltage
0, it is difficult to obtain a circuit that operates stably, and the magnitude of the output amplitude and the gain of the circuit cannot be adjusted independently. In addition, the gate of the data line load circuit 11 is connected to GND. Connected PMOS
11a, or NMO with drain and gate connected
Due to the construction with S, there is provided a cell Nsu circuits which solves the problem that a wide sense circuit 10 dynamic range is obtained with a low power supply voltage operation. That is, a first object of the present invention is to provide a sense circuit which is excellent in low power supply voltage operation and excellent in operation stability.

A second object is to provide a sense circuit which is excellent in low power supply voltage operation and has a wide dynamic range. The third purpose is excellent in low power supply voltage operation, excellent in operation stability,
Provided is a sense circuit having a wide dynamic range and a small number of elements. A fourth object is to provide a sense circuit having a small number of manufacturing steps, a large gain, and excellent low power supply voltage operation and operation stability. A fifth object is to provide a sense circuit with a small number of manufacturing steps, a large gain, excellent low power supply voltage operation and operation stability, and a wide dynamic range .

[0013]

To achieve the pre-Symbol purposes SUMMARY OF THE INVENTION In the first aspect of the present invention, it is connected the input terminal and the first potential supply terminal (e.g., V _CC) between the Load means, the input terminal and a second potential supply terminal (for example,
GND), and a sense circuit including an inverting amplifier for controlling the current-voltage converting circuit, the inverting amplifier being configured as follows. The current-to-voltage conversion circuit may include a first conductivity type MOS transistor connected between the input terminal and the output terminal and having a gate connected to an output node of the inverting amplifier; And a first resistance means connected between the first and second potential supply terminals.

In the inverting amplifier of the present invention, the first conduction type depletion type MOS transistor and the second resistance means are connected in series (that is, connected in series or connected in series via another circuit element or the like). And the input node is connected to the input terminal. In the second invention
A load means and a current-voltage conversion circuit according to the first invention;
Cell comprising an inverting amplifier for controlling the serial current voltage conversion circuit
In the sense circuit, the following measures are taken. Immediately
That is, the input node of the inverting amplifier is connected to the sense circuit.
Connected to an input terminal, the load means being connected to the first potential
A MOS transistor connected between a supply terminal and the input terminal.
Level of the input terminal of the transistor and the input terminal.
Level shifter for controlling gate of MOS transistor
And According to a third aspect of the present invention, in the sense circuit including the inverting amplifier according to the first aspect of the invention, the following means is taken. Here, the current-to-voltage conversion circuit is connected between the input terminal and the output terminal and has a gate connected to an output node of the inverting amplifier.
A transistor; and first resistance means connected between the output terminal and the second potential supply terminal. In the present invention, an input node of the inverting amplifier is connected to the input terminal. Further, the load means includes a second MOS transistor of a first conductivity type connected between the input terminal and the first potential supply terminal;
A level shifter, an input node of said level shifter being connected to said input terminal, an output node of 該Re Berushifuta is connected to a gate of said second MOS transistor.

In a fourth aspect , a load means connected between an input terminal and a first potential supply terminal, and a current-to-voltage conversion circuit connected between the input terminal and a second potential supply terminal In a sense circuit including an input node and an amplifier circuit having an input node and first and second output nodes and controlling the current-voltage conversion circuit, the following means is provided. Here, the current-to-voltage conversion circuit is connected between the input terminal and the output terminal, and has a gate connected to a first output node of the amplification circuit, a first conductivity type first MOS transistor; A first resistance means connected between the output terminal and the second potential supply terminal.

Further, the load means of the present invention comprises a first conduction type first terminal connected between the input terminal and the first potential supply terminal and having a gate connected to a second output node of the amplifier circuit. It has two MOS transistors. further,
The amplifying circuit has a first conductivity type depletion type MOS transistor having a gate connected to an input node of the amplifying circuit and a drain connected to a first output node of the amplifying circuit, and a gate connected to an input node of the amplifying circuit. And a third MOS transistor of a second conductivity type having a source connected to a second output node of the amplifier circuit, a current input terminal connected to a first output node of the amplifier circuit, and a current output terminal connected to a third output node of the amplifier circuit. A current mirror circuit having a second conductivity type MOS transistor configuration connected to a second output node of the amplifier circuit. Further, an input node of the amplifier circuit is connected to the input terminal. In the fifth invention
Is a load means and a current-voltage conversion circuit according to the fourth invention,
A current node having a power node and first and second output nodes.
A sense circuit including an amplifier circuit for controlling the voltage conversion circuit.
The following measures have been taken. That is, the amplification
The circuit has a resistance value according to the potential of the input node of the amplifier circuit.
And the corresponding power supply current is
Negative resistance circuit to supply to output node 1 and gate
The source connected to the input node of the amplifier circuit
A third of a second conductivity type connected to a second output node of the path.
A MOS transistor and a current input terminal are connected to the amplifier circuit.
A current output terminal connected to a first output node is connected to the amplification circuit.
Second conductivity type MOS transistor connected to the second output node of the path.
A current mirror circuit having a transistor configuration.
An input node of the width circuit is connected to the input terminal.
You. In a sixth aspect based on the sense circuit of the first aspect, the inverting amplifier includes a negative resistance circuit having an input node connected to the input terminal and connected in series, and a second resistance means. ing. Further, the negative resistance circuit includes a control terminal connected to an input node of the inverting amplifier, a first input / output terminal connected to the first potential supply terminal directly or via a switch, It has an output node of the inverting amplifier and a second input / output terminal connected to the second resistance means.

In a seventh aspect, the sense circuit according to the third aspect is provided.
Has taken the following measures. Where
The current-voltage conversion circuit is provided between the input terminal and the output terminal.
And the gate is connected to the first output node of the amplifier circuit.
A first conductivity type MOS transistor connected to the
The connected between the terminal and the second potential supply terminal 1
Resistance means. And the amplification circuit of the present invention.
The path has its input node connected to the input terminal and
A negative resistance circuit and a second resistance means connected in a column configuration;
Have. Further, the negative resistance circuit includes the amplification circuit.
A control terminal connected to the input node of the
Connected directly to the power supply terminal or via switch means
A first input / output terminal and a first output node of the amplifier circuit
And a second input / output terminal connected to the second resistance means
And an output connected to a second output node of the amplifier circuit
And a terminal.

In an eighth aspect, the cell according to the sixth or seventh aspect is provided.
In the negative resistance circuit in the sense circuit, the source is the first resistance.
The drain is connected to the input / output terminal and the drain is connected to the second input / output terminal.
First MOS transistors of the first conductivity type respectively connected
And the drain is connected to the first potential supply terminal and the gate is connected to the front.
The control terminal has a source connected to the first MOS transistor.
And the output terminal of the negative resistance circuit
A second MOS transistor of the second conductivity type, and a drain
Is connected to the source of the second MOS transistor.
Is connected to the second input / output terminal, and the source is connected to the second potential.
A third MO of the second conductivity type respectively connected to the supply terminals;
And an S transistor.

[0019]

According to the first aspect of the present invention, since the sense circuit is configured as described above, the input terminal connected to the input node of the inverting amplifier can be biased, for example, near V _CC , and the current-voltage conversion circuit , A sufficiently large bias voltage can be applied, and the low power supply voltage operation can be improved. Further, the circuit does not have a plurality of operating points, thus not only stabilizing the operation, but also making it possible to independently adjust the magnitude of the output amplitude and the magnitude of the gain, so that desired characteristics can be easily realized.
According to the second invention, the load means includes a MOS transistor and a load.
And level shifter, the linearity of the load characteristics
It is improved and the dynamic range can be expanded. According to the third aspect , the load means includes a load second MOS transistor provided between the input terminal and the first potential supply terminal, and a level shifter connected to the input terminal. The output of the level shifter is connected to the gate of the load second MOS transistor. As a result, the linearity of the characteristics of the load means is improved, and the low power supply voltage operation can be improved and the dynamic range can be expanded. 4th or 5th
According to the invention, the sense circuit includes the load means, the current-voltage conversion circuit, and the amplifier circuit, and the amplifier circuit includes a first conduction type depletion type MOS transistor (or a negative resistance type).
Circuit) , a third MOS transistor of the second conductivity type ,
And a current mirror circuit. Thus, when the bias near the input terminal of the sense circuit, for example, V _CC, the input voltage signal is level-shifted, is amplified by the level shift output is obtained largely. With this level shift output, the linearity of the characteristics of the load means can be improved. or,
Since the input of the amplifier circuit is obtained from the input terminal of the entire sense circuit, the circuit operation is stable, and furthermore, the inverted amplifier output and the level shift output can be obtained by one amplifier circuit, so the number of components of the sense circuit is reduced. it can.

According to the sixth aspect , the sense circuit includes load means, a current-voltage conversion circuit, and an inverting amplifier. An input node of the inverting amplifier is connected to an input terminal of the sense circuit. Have a negative resistance circuit and a second resistance means. As a result, even if the bias potential of the input terminal is set close to, for example, V _CC , the inverting amplifier does not cut off, so that a sufficiently large bias voltage can be applied to the current-voltage conversion circuit, and the operation of the low power supply voltage can be improved. Since the input of the inverting amplifier is obtained from the input terminal of the entire sense circuit, the operation stability can be improved. Further, since the magnitude of the output amplitude and the gain of the circuit can be adjusted independently, desired characteristics can be easily obtained. Also, since a negative resistance circuit is used for the inverting amplifier, the gain can be increased,
Further, the operation of the inverting amplifier can be stabilized, and the number of manufacturing steps can be further reduced.

According to the seventh aspect , the sense circuit includes the load means, the current-voltage conversion circuit, and the amplifier circuit, and the amplifier circuit further includes the negative resistance circuit and the second resistance means. I have. Thus, the input voltage signal is level-shifted and amplified from the second output of the amplifier circuit, and a level-shifted output is obtained. Since the load means is controlled by the level shift output, the characteristics of the load means are improved. Further, similarly to the fourth aspect, the operation stability, the gain can be increased, and the dynamic range in the low power supply voltage operation can be expanded. Further, since the amplifier circuit has the functions of an inverting amplifier and a level shifter, the number of constituent elements of the sense circuit can be reduced and the manufacturing process can be simplified.

According to the eighth aspect , the negative resistance circuit includes the enhancement type first, second, and third MOS transistors, so that the gain is increased, the operation is stabilized, and the manufacturing process is improved. Simplification can be achieved .

[0023]

( First Embodiment ) FIG. 1 is a circuit diagram of a sense circuit showing a first embodiment of the present invention. In this sense circuit, an input terminal IN is connected to a node N11, and a load means (for example, a data line load circuit ) 100 is connected between the node N11 and a first potential supply terminal (for example, V _CC ). I have. The current-voltage conversion circuit 200 is connected between the node N11 and a second potential supply terminal (for example, GND). The current-voltage conversion circuit 200 is configured by a series circuit of a PMOS 201 and a resistor 210. The PMOS 201 has a source connected to the node N11, a gate connected to the node N12, and a drain connected to one end of the resistor 210 and the output terminal OUT. The other end of the resistance means 210 is connected to GND. The input nodes A _in and the output nodes A _out of the inverting amplifier 300 are connected to the nodes N11 and N12, respectively. The inverting amplifier 300 is configured by a series circuit of a depletion type PMOS 301 and a resistor 310. The PMOS 301 has a source connected to V _CC ,
The gate is connected to the input node A _in and the drain is connected to the resistor 310.
, And the output node A _out . The other end of the resistance means 310 is connected to GND.

Next, the operation will be described. Input terminal IN is V
Biased to a predetermined level close to _CC . From the data line load circuit 100 to the input terminal IN, (it may be I ₁ = 0) the constant bias current I ₁ is flowing. or,
From the data line load circuit 100 to the current-voltage conversion circuit 200, and a constant bias current I ₂ flows. In this state, the PMOS 201 is designed to be saturated. For example, the current I ₁ flowing out of the input terminal IN is Δ
And it increased by I _1. Then, the data line load circuit 1
00, the level of the input terminal IN (that is, the node N11) slightly decreases. This is amplified by the inverting amplifier 300, and the level of the node N12 rises. Therefore, the source potential of the PMOS 201 decreases and the gate potential increases, so that the gate-drain voltage decreases and the conductance decreases.
Since the PMOS 201 is saturated, its conductance changes greatly, and the current I ₂ flowing through the current-voltage conversion circuit 200 decreases by ΔI ₂ (≒ ΔI ₁ ). As a result,
The potential of the output terminal OUT is ΔV = −ΔI ₂ · r ₁₁ (where,
r ₁₁ ; the resistance value of the resistance means 210), so that a desired output voltage amplitude can be obtained by appropriately determining the resistance value r ₁₁ . On the other hand, the current I _L flowing through the data line load circuit 100 does not change much because the current I ₂ decreases as the current I ₁ increases. Therefore, the input terminal I
The potential of N is kept almost constant. Thus, an output signal having a large voltage amplitude corresponding to the input current signal can be obtained while suppressing the voltage amplitude of the input terminal IN.

This embodiment has the following advantages. (A) Since the current-voltage conversion circuit 200 is provided between the input terminal IN and GND, when a data line is connected to the input terminal IN in a memory circuit or the like, each of the data lines connected to the data line is used. The switch means and the current / voltage conversion circuit 200 are connected in parallel, and a sufficient bias voltage can be applied to both. Therefore, even when the power supply voltage is lowered, the operation speed and the operation margin are excellent, that is, the operation is excellent at the low power supply voltage operation. (B) In the inverting amplifier 300, the input node A
_{Since the} MOS transistor connected to in is a depletion type, the bias potential of the input terminal IN can be made sufficiently close to V _CC without the inverting amplifier 300 being cut off. Therefore, the current-voltage conversion circuit 2
A bias voltage can be applied to 00 almost to the full V _CC , and a device excellent in low power supply voltage operation can be obtained. (C) Since the signal at the input node A _in of the inverting amplifier 300 that controls the current-voltage conversion circuit 200 is obtained directly from the input terminal IN of the sense circuit, the operation stability is excellent. Hereinafter, this point will be described in detail. For example, in FIG. 1, the data line load circuit 100 and the current / voltage conversion circuit 200 are collectively referred to as a circuit 1, and the inverting amplifier 300 is referred to as a circuit 2
And The input of circuit 1 to circuit 2 is node N12, and the output is node N11. On the other hand, the input of the circuit 2 to the circuit 1 is the node N11, and the output is the node N11.
Twelve. That is, the inputs and outputs of the circuits 1 and 2 are cross-connected to each other. Here, paying attention to the circuit 1, the output (node N11) of the circuit 1 is a source follower with respect to its input (node N12). That is, since the circuit 1 acts as a source follower for the circuit 2, the input and output of the circuit 1 do not become out of phase, and the amplification factor is 1
Less than. Therefore, a stable device can be obtained without positive feedback and without a risk of entering a holding state or oscillating as a latch.

In order to increase the output voltage amplitude,
What is necessary is just to make the value of the resistance means 210 large. In order to increase the gain of the entire sense circuit, the inverting amplifier 300
Or the current-voltage conversion circuit 200
In this case, the bias potential of the gate of the PMOS 201 may be appropriately determined, and adjustment may be performed such that the saturation of the PMOS 201 is increased. As described above, since the magnitude of the output voltage amplitude and the gain of the entire circuit can be independently adjusted, desired characteristics can be easily obtained.

( Second Embodiment ) FIG. 4 is a more specific circuit diagram of the sense circuit of the first embodiment shown in FIG. Is attached.

In this sense circuit, the load means shown in FIG .
Of the data line load circuit 100 is constituted by a PMOS 101 whose gate is connected to GND, the resistance means 210 in the current-voltage conversion circuit 200 is constituted by an NMOS 211 whose gate and drain are connected, and Is constituted by an NMOS 311 having a gate and a drain connected to each other. Other configurations are
It is the same as FIG.

This embodiment has the following advantages. (1) Since the resistance means in the inverting amplifier 300 is constituted by the NMOS 311 having the gate and the drain connected, the voltage amplitude of the output node A _out of the inverting amplifier 300 is limited. Therefore, the gain of the entire circuit is reduced, but the dynamic range can be widened. The rest of the configuration is basically the same as that of the first embodiment, and therefore, as in the first embodiment, there is an advantage that the power supply voltage operation is excellent and the operation stability is excellent.

(2) In this embodiment, as in the first embodiment, the magnitude of the output voltage amplitude and the gain of the entire circuit can be independently adjusted. Here, FIG.
This will be specifically described with reference to FIG. First, in FIG.
The data line load circuit 100 and the current / voltage conversion circuit 200 are collectively referred to as a circuit 1, and the input thereof is connected to a node N12.
And the output is a node N11. The inverting amplifier 30
0 is a circuit 2. Then, the circuit 1 and the circuit 2 have their inputs and outputs cross-connected to each other. FIG. 5 is an input / output characteristic diagram for determining the stability of a circuit having such a configuration. The horizontal axis in FIG. 5 is the input potential V _I1 of the circuit ₁ and the output potential V _O2 of the circuit 2, and the vertical axis is the output potential V _O1 of the circuit ₁ and the input potential V _I2 of the circuit 2. A curve C ₁ is an input / output characteristic curve of the circuit 1, and a curve C ₂ is an input / output characteristic curve of the circuit 2.

As in the first embodiment, circuit 1 acts as a source follower for circuit 2. Therefore, the characteristic curve C ₁ has a shape in which the output potential V _O2 increases as the input potential V _I1 increases. Since the circuit 2 are inverting amplifier 300, the characteristic curve C ₂ becomes an input voltage V _I2 is increased and the output voltage V _O2 is shaped to drop. Therefore, the characteristic curve C
₁ and C ₂ intersect at one operating point P. Thus, since only one operating point P exists, an extremely stable circuit can be obtained.

( Third Embodiment ) FIG. 6 is a circuit diagram of a sense circuit according to a third embodiment which embodies the sense circuit of FIG. 1 according to the first embodiment. Elements common to those in the middle are denoted by common symbols. This sense circuit is obtained by improving the gain of the sense circuit shown in FIG. 4, and has the same data line load NMOS 101 and current-voltage conversion circuit 2 as the sense circuit shown in FIG.
00, and an inverting amplifier 300A having a configuration different from that of the inverting amplifier 300 is provided. Inverting amplifier 3
00A is a depletion type PMOS 301 and NMO
It is composed of the series circuit of S311. PMOS301
_Has a source connected to V _CC , a gate connected to the input node A _in , and a drain connected to the output node A _out .
NMOS311 is to drain the output node A _out, the gate input node A _in, the source GND, are connected. Other configurations are the same as those in FIG.

In this embodiment, since the gate of the NMOS 311 is connected to the input node A _in of the inverting amplifier 300A,
The gain of the inverting amplifier 300A can be increased. Therefore, although the dynamic range of the whole circuit is slightly narrowed, the gain of the circuit can be improved. Since the operation is basically the same as in the first and second embodiments, the same advantages can be obtained.

( Fourth Embodiment ) FIG. 7 is a circuit diagram of a sense circuit showing a fourth embodiment of the present invention. FIGS. 1, 4 and 4 show the first to third embodiments. Elements common to the elements in 6 are denoted by the same reference numerals. In this sense circuit, the load means shown in FIGS.
A data line load circuit 100A having a different configuration from the data line load circuit 100 of FIG.
And an inverting amplifier 300. Data line load circuit 100A includes a PMOS101 connected between the input node L _in the V _CC which is connected to the node N11, the output input node connected to the input node L _in the node N21
And the level shifter 102 connected to the gate of the PMOS 101 through the gate. Other configurations are first to
Since it is the same as the third embodiment, the basic operation as the sense circuit is the same. Therefore, the description of the configuration and the basic operation of the same part is omitted, and the characteristics of the data line load circuit 100A will be mainly described below. FIG. 8 is a characteristic diagram showing a load curve of the data line load circuit 100A of FIG. The horizontal axis of FIG. 8 is the input node L _in the potential V _LIN, the vertical axis is the current I _L flowing through the PMOS101 data line load circuit 100A. The solid curve l ₁ is the load curve of the data line load circuit 100A. Dashed curves l ₂ and l
₃ is added for explanation, and curve l ₂ is a PMOS
101 only as a load, the gate potential V _G V _G = V
It is a load curve with _CC - _VSHF . Curve l ₃ is the PMO
S101 only as a load, the gate potential V _G V _G =
It is a load curve with 0V. The voltage V _SHF is a shift voltage by the level shifter 102, and | V _SHF | ≧ | V _TP
| Is designed.

For example, _assuming that V _LIN = V _CC , this potential is shifted down by the voltage V _SHF by the level shifter 102, and the PMOS 101
Output to the gate. Therefore, the gate potential V _G of the PMOS101 becomes V _G = V _CC -V _SHF. Potential V _LIN
When There decreases, so decreases also the gate potential V _G, the current I _L flowing through the PMOS101 increases.
Further, when the potential V _LIN decreases and becomes V _LIN <V _SHF , V _G = 0 V and becomes constant regardless of the potential V _LIN , so that the current _IL becomes constant. Therefore, the load curve l ₁
Is the area near the potential V _LIN is to V _CC indicates a characteristic as to extend tangents at non-saturation region in the curve l _2, if the potential V _LIN approaches the curve l ₃ decreases, shaped to saturate Is shown. Thus, the entire data line load circuit 100A behaves like a MOS transistor in which the unsaturated region is extended in appearance. Here, considering that the curve l ₃ is equivalent to the characteristic of the conventional data line load circuit,
In the data line load circuit 100A of the present embodiment, when the current value at which the characteristic starts to be saturated is made equal, the equivalent resistance value can be made larger than that of the conventional circuit. That is, when the same design maximum allowable value of the voltage amplitude of the input node L _in, so that the more conventional, can be reliably sense a very small current signals. On the other hand, if the equivalent resistance value of the data line load circuit is made equal, the current value of the embodiment can be larger than that of the conventional one, at which the saturation of the characteristic starts.

As described above, this embodiment has the following advantages. (I) Since the data line load circuit 100A includes the PMOS 101 and the level shifter 102, the linearity of the load characteristics is improved, and a sense circuit having a wider dynamic range than before can be obtained. Further, even if the potential of the input terminal IN is V _CC , the load PMOS 101 is not cut off by the operation of the level shifter 102, so that the bias potential of the input terminal IN can be made sufficiently close to V _CC .
Therefore, even if the dynamic range is widened, the advantage of excellent low power supply voltage operation is not impaired.

(Ii) The sense circuit of this embodiment is provided with a data line load circuit 100A having a different configuration in place of the data line load circuit 100 of the first embodiment, and the other configuration is the same. Therefore, similarly to the first embodiment, there are advantages that the power supply voltage operation is excellent, the operation stability is excellent, and desired characteristics can be easily obtained.

(Iii) Data line load circuit 10 of this embodiment
The use of 0A is effective not only for a sense circuit but also for a load means of various circuits requiring a current-voltage characteristic with improved linearity.

( Fifth Embodiment ) FIG. 9 is a circuit diagram of a sense circuit showing a fifth embodiment of the present invention, and FIGS. 1, 4 and 6 show the first to fourth embodiments. , And elements common to those in FIG. 7 are denoted by common reference numerals. This sense circuit has the same load means as that of FIG.
, A data line load PMOS 101, a current-voltage conversion circuit 200 similar to that of FIG. 1, and an amplifier circuit 400. PMOS101 for data line load is connected in series between the input terminal IN and V _CC, the input terminal I
A current-voltage conversion circuit 200 is connected between N and GND. The current-to-voltage conversion circuit 200, as in FIG.
It is composed of a series circuit of a MOS 201 and a resistance means 210, and a connection point between the two is connected to an output terminal OUT. The amplifier circuit 400 includes an input node A _in connected to the input terminal IN via the node N31, a first output node A _out1 connected to the gate of the PMOS 201 via the node N32, and a node N33 connected to the gate of the PMOS 101.
And a second output node A _out2 connected via This amplifier circuit 400 is provided with the level shifter 10 shown in FIG.
2 and an inverting amplifier 300 which was implemented in a single circuit, the PMOS401 of depletion type whose gate is connected to the input node A _in, and NMOS402 having a gate connected to the input node A _in, NMOS411,412
And a current mirror circuit 410 composed of The PMOS 401 has a source connected to V _CC and a drain connected to the current input node I _in of the current mirror circuit 410. The NMOS 402 has a drain of V
_The source is connected to the current output node I _out and the second output node A _out2 of the current mirror circuit 410, respectively, to _CC .

In the current mirror circuit 410, each source of the NMOSs 411 and 412 constituting the current mirror circuit 410 is connected to GND, and each gate is connected to the first output node A _out1 . Drain and gate of the NMOS411 is connected to the current input node I _in. The drain of the NMOS412 is connected to the current output node I _out.

Next, (1) the operation of the amplifier circuit 400 and
(2) The potential of the input node A _in and the first output node A _out2
And (3) the operation of the entire sense circuit and the advantages of the present embodiment will be described. (1) Operation of the amplifier circuit 400 A PMO is provided between the input node A _in and the output node A _out1.
An inverting amplifier including S401 and NMOS 411 is connected, and this part has the same configuration as the inverting amplifier 300 in FIG. Therefore, the voltage signal of the input node A _in (that is, the input terminal IN) is inverted and amplified and output to the output node A _out1 .

[0042] (2) relationship diagram 10 between the potential of the input node A _in the second output node A _out2, the operating characteristic diagram for explaining the operation of the output node A _out2 of the amplifying circuit 400 of FIG. 9 It is. In this figure, the vertical axis represents current, and the horizontal axis represents voltage. For example, assume that the capabilities of the NMOSs 411 and 412 are equal. 10, the curve C _Na is the potential of the output node A _out2 the horizontal axis, the current vertical axis through the NMOS402 size Satoshi, the current-voltage characteristic curve of the NMOS402 when the potential of the input node A _in and the V _a It is. FIG.
As shown in the _figure , the potential of the output node A _out2 is V _a −V _TNN
At lower levels, current begins to flow. The curve C _Nb is
NMOS40 when the potential of the input node A _in was V _b
2 is a current-voltage characteristic curve, and the definition of the vertical axis and the horizontal axis is the same as that of the curve _CNa . In this case, output node A _out2
When the potential of _Vb becomes lower than _Vb - _VTNN , a current starts to flow. Curve l _a and l _b, the horizontal axis is the potential of the output node A _out2, the vertical axis is a current-voltage characteristic curve of the NMOS412 when the magnitude of the current flowing through the NMOS412. The curve l _a is obtained when the potential of the input node A _in is V _a , and the curve l _b is obtained when the potential of the input node A _in is V a
This is when _b . Curve C _b, the horizontal axis is the potential of the input node A _in the vertical axis is a current-voltage characteristic curve of the PMOS 401 when the current through PMOS 401. For example, when the potential of the input node A _in is V _a, when the current flowing through the PMOS401 and I _a, the current I _a flows to NMOS411. NMOS 411
And 412 because it constitutes a current mirror circuit 410, so that the flow is also the current I _a in NMOS412. Therefore, NMOS412 characteristic curve l _a and N
The MOS402 characteristic curve C _Na, intersect at a point P _a for the current value becomes I _a. This point P _a is the potential of the input node A _in is an operating point of output node A _out2 when a V _a, the voltage value V _outa of the operating point P _a is the potential of the output node A _out2. Similarly, when the potential of the input node A _in is V _b, when the current through the PMOS401 and I _b, at this time, is also an I _b the current through the NMOS412,
The characteristic curve C _Nb characteristic curve l _b and NMOS402 of the NMOS412, intersect at a point P _b where the current value becomes I _b.
The potential of the point P _b is the input node A _in is the operating point of output node A _out2 when a V _b, the voltage value V _outb is the potential of the output node A _out2. Thus, the amplifier circuit 400 in the present embodiment, not only the input voltage signal is level-shifted, amplified input voltage amplitude V _a -V _b and _{V outa -V outb (> V a} -V b) An extremely large voltage amplitude is obtained.

The condition under which the input voltage amplitude is amplified is that the NMOS 412 is saturated.
It is necessary that the potential of the input node A _in is sufficiently close to V _CC . However, this is only the use condition of the sense circuit of the present embodiment, and does not restrict the operation. next,
The output voltage amplitude of the conventional level shifter is compared with that of the present embodiment. For example, the NMOS 412 is connected to the current I
_It is configured to be a constant current source for flowing a. Then, when the potential of the input node A _in is _Vb , the output node A _out2
The operating point is P _bb and the potential is V _outbb, and the output voltage amplitude is V _outa −V _outbb , which is smaller than that of the present embodiment. That is, in the amplifier circuit 400 of the present embodiment, a level shift signal having a larger output voltage amplitude than the conventional one is obtained for a signal having the same input voltage amplitude.

(3) Operation of the entire sense circuit and advantages of the present embodiment A voltage output signal obtained by inverting and amplifying the voltage signal of the input signal IN is obtained at the first output node A _out1 of the amplifier circuit 400. PMOS 201 in current-voltage conversion circuit 200
Drive the gate. On the other hand, the voltage signal of the input terminal IN is level-shifted by the operation of the amplifier circuit 400, and an amplified level-shifted signal is obtained, whereby the gate of the PMOS 101 for data line load is controlled.
Therefore, the operation of the entire sense circuit is basically the same as that of the fourth embodiment shown in FIG. 7, and is excellent in low power supply voltage operation, excellent in operation stability, and has a wide dynamic range. Is obtained.

Further, in this embodiment, a level-shifted output which is larger than the conventional one can be obtained.
7, the data line load characteristic is further improved and a wider dynamic range is obtained. In addition, in this embodiment, since one amplifier circuit 400 can obtain an inverted amplified output and a level shift output of the input voltage signal, the number of elements of the sense circuit can be reduced as compared with a case where an inverted amplifier is separately provided. Further, the application of the amplifier circuit 400 of the present embodiment is not limited to the use in the sense circuit, but in various fields requiring the amplified level shift output, for example, in an interface circuit or the like.
It is effective as a level shifter.

( Sixth Embodiment ) FIG. 11 is a circuit diagram of a sense circuit showing a sixth embodiment of the present invention. The elements common to the elements in FIG. 1 showing the first embodiment are shown in FIG. Common symbols are assigned. In this sense circuit, a data line load circuit 10 which is the same load means as in FIG.
1 and a current / voltage conversion circuit 200, and an inverting amplifier 300B having a configuration different from that of FIG. The inverting amplifier 300B includes an input node A _in connected to the input terminal IN.
And an output node A connected to the gate of the PMOS 201
_out , and comprises a negative resistance circuit 320 and a resistance means 310. The negative resistance circuit 320 includes a control terminal G
And the first and second input / output terminals S and D, the control terminal G is connected to the input node A _in , the first input / output terminal S is connected to V _CC ,
The second input / output terminal D is connected to one terminal of the resistor 310 and the output node A _out . The other terminal of the resistance means 310 is connected to GND.
The negative resistance circuit 320 includes first and second input / output terminals S and D
It is composed of a PMOS 321 connected between them, and NMOSs 322 and 323 connected in series between V _CC and GND.

The PMOS 321 has a source connected to the first input / output terminal S, a gate connected to the node N40, and a drain connected to the second input / output terminal D. PMOS3
Reference numeral 22 has a drain connected to V _CC , a gate connected to the control terminal G, and a source connected to the node N40. NM
The OS 323 has a drain connected to the node N40, a gate connected to the second input / output terminal D, and a source connected to GND.

The other parts are the same as in FIG. 1 showing the first embodiment. Next, the operation of the sense circuit of this embodiment will be described with reference to FIGS. First, the operation of the inverting amplifier 300B will be described with reference to FIG. FIG. 12 is an operation characteristic diagram at the output node A _out of the inverting amplifier 300B. The vertical axis of this figure is the current flowing between the first and second input / output terminals S and D of the negative resistance circuit 320 and the current flowing through the resistance means 310, and the horizontal axis is the potential of the output node A _out . is there.

[0049] In FIG. 12, curve NR _a, the first and second input terminals S of the negative resistance circuit 320 when the potential of the input node A _in and the V _a, in the current-voltage characteristic curve between the D is there. A curve NR _b is a current-voltage characteristic curve of the negative resistance circuit 320 when the potential of the input node A _in is _Vb . In each of these curves NR _a and NR _b , the current increases once as the potential of the output node A _out decreases, and then begins to decrease at a certain point. Curve l in FIG.
_R is the resistance means 310 when, for example, an NMOS having a gate and a drain connected is used as the resistance means 310.
5 is a current-voltage characteristic curve of FIG. When the potential of the input node A _in is V
the operating point of the circuit when it is _a is a curve NR _a and the curve l _R
Intersection P _a becomes the voltage value V _outa at that time becomes the potential of the output node A _out. On the other hand, the operating point of the circuit when the potential of the input node A _in is V _b, the intersection point P _b becomes the curve NR _b and the curve l _R, the potential of the voltage value V _outb output node V _out at that time Become. That is, the input voltage amplitude V _a
The output voltage amplitude V _outa −V _outb with respect to −V _b is obtained.

Next, the gain of the inverting amplifier 300B of the present embodiment is compared with that of FIG. 1 showing the first embodiment.
For example, when the negative resistance circuit 320 of FIG. 11 is replaced with a depletion-type PMOS, the current-voltage characteristics are as shown in FIG.
The curves C _aa and C _bb indicated by the broken lines in FIG. As a result, the operating point of the circuit is next P _aa when the potential of the input node A _in is V _a, the operating point of the circuit when the potential of the input node A _in is V _b becomes P _bb. Therefore, the output voltage amplitude is less than those using _{V aa -V bb (<V a} -V b) , and the negative resistance circuit 320.

As described above, in this embodiment, the inverting amplifier 3
Since 00B is constituted by the negative resistance circuit 320 and the resistance means 310, an inverting amplifier having a higher gain can be obtained.
Further, a potential lower than the potential of the control terminal G by at least the threshold voltage V _TNN is obtained at the node N40 of the negative resistance circuit 320. Therefore, the input terminal IN is connected to V _CC
Even if the potential is negative, the negative resistance circuit 320 is not cut off, and a wide dynamic range can be obtained as in the case of using a depletion-type PMOS. Therefore, for example, the potential of the input terminal IN can be biased near V _CC without performing an ion implantation step for obtaining a depletion type MOS transistor. Therefore, a sense circuit excellent in low power supply voltage operation can be obtained.

Next, the stability of the operation of the inverting amplifier 300B will be described with reference to FIG. FIG.
FIG. 13 is a circuit diagram for explaining the stability of the operation of the inverting amplifier 300B in FIG. 11, and components common to the components in FIG. 11 are denoted by the same reference numerals. Here, NMOS 32
2 and the NMOS 323 are collectively referred to as a circuit 1. The input of the circuit 1 is referred to as a node N42, and the output of the circuit 1 is referred to as a node N40. Note that the node N41 is biased to an appropriate potential. In addition, the PMOS 321 and the resistor 310 are collectively referred to as a circuit 2, the input of which is a node N40, and the output of which is a node N42. The resistance means 310 is an NMO having a gate and a drain connected.
S is assumed. As is clear from FIG. 13, the input and output of the circuit 1 and the circuit 2 are cross-connected to each other. FIG. 14 is an input / output characteristic diagram of the circuits 1 and 2 for determining the stability of the operation of such a circuit. 14, the vertical axis represents the output potential V _O1 of the circuit ₁ and the input potential V _I1 of the circuit 2, and the horizontal axis represents the input potential V _I1 of the circuit ₁ and the output potential V _O2 of the circuit 2. A curve C ₁ is an input / output characteristic curve of the circuit 1, and a curve C ₂ is an input / output characteristic curve of the circuit 2. In the circuit 1, as the potential of the input (node N42) decreases, the potential of the output (node N40) increases. When the input potential becomes V _TN , the output potential becomes V _CC −V
It becomes constant up to _TNN . On the other hand, in the circuit 2, as the potential of the input (node N40) increases, the potential of the output (node N42) decreases, and the input potential becomes V _CC −
When | V _TP |, the output potential reaches V _TN and becomes constant. Accordingly, the characteristic curves C ₁ and C ₂ intersect at one operating point P as shown in FIG. Here, attention is paid to a region where the output of the circuit 1 (node N40) becomes V _CC −V _TNN . At this time, since a large back bias is applied to the NMOS 322, V _TNN > V _TN . Therefore,
If the manufacturing conditions satisfying V _TN ≒ | V _TP |
_{Since TNN} > | V _TP |, the input / output characteristic curves do not intersect at a plurality of points. These manufacturing conditions are based on general CMO
This is an ordinary condition for manufacturing an S integrated circuit. Therefore, in this embodiment, the inverting amplifier 300B having a high gain can be obtained without any special manufacturing process.

Next, the operation of the entire sensing circuit in this embodiment and the advantages of this embodiment over the conventional example will be described. In the sense circuit of the present embodiment, an inverting amplifier 30 having a different configuration is used instead of the inverting amplifier 300 of FIG. 1 showing the first embodiment.
0B, and the other configuration is the same as that of FIG. Moreover, the inverting amplifier 300B has an input node A _in whose V _CC
Does not cut off even if biased nearby. Therefore, as in the first embodiment, a sense circuit excellent in low power supply voltage operation and excellent in operation stability can be obtained. In addition, a sense circuit capable of independently adjusting the magnitude of the output amplitude and the gain of the entire circuit can be obtained. Further, in this embodiment, the following advantages are obtained in addition to these advantages. That is, since the inverting amplifier 300B is constituted by the negative resistance circuit 320 and the resistance means 310, a sense circuit having a larger gain than that of the first embodiment can be obtained. In addition, since a depletion type MOS transistor is not particularly required, a sense circuit with a small number of manufacturing steps can be obtained.

( Seventh Embodiment ) FIG. 15 is a circuit diagram of a sense circuit showing a seventh embodiment of the present invention. Elements common to the elements in FIG. 9 showing the fifth embodiment are shown in FIG. Common symbols are assigned. This sense circuit is different from the sense circuit of FIG. 9 only in that an amplifier circuit 400A having a different configuration from that of the amplifier circuit 400 is provided. The amplifier circuit 400A includes a control terminal G, first and second input / output terminals S and D, and an output terminal X.
Resistance circuit 420 having resistance and NMOS 4 for resistance means
30. The control terminal G of the negative resistance circuit 420 is connected to the input node A _in of the amplifier circuit 400A, and the output terminal X is connected to the second output node A of the amplifier circuit 400A.
_out2 is connected to each. Negative resistance circuit 420
Is connected to V _CC . Second
Is connected to the gate and drain of the NMOS 430 and the first output node A _out of the amplifier circuit 400A. The source of the NMOS 430 is connected to GND.

This negative resistance circuit 420 is similar to the negative resistance circuit 320 shown in FIG.
S421 and NMOSs 422 and 423.
It differs from FIG. 11 only in that the gate of the MOS 421 is connected to the output terminal X. Next, the operation of the amplifier circuit 400A will be described. First, paying attention only to the relationship between the input node A _in and the first output node A _out1 , since this portion has the same configuration as the inverting amplifier 300B of FIG. 11 showing the sixth embodiment, it is similar to the inverting amplifier 300B. Operate. That is, at the first output node A _out1 , a change in the input voltage of the input node Ain is obtained by inverting and amplifying. Then, by focusing on the relationship of the second output node A _out to the input node A _in explaining the operation of the circuit. For explanation of this operation, the fifth
FIG. 9 shows an embodiment of the present invention.
Consider a circuit in which 401 is replaced with a negative resistance circuit 440 as shown in the modified circuit of FIG. Negative resistance circuit 440
Is a negative resistance circuit 320 shown in FIG. 11 showing the sixth embodiment.
And the control terminal G, the first and second
It has input / output terminals S and D, a PMOS 441 and an NMOS
442, 443. First, paying attention to a portion composed of the negative resistance circuit 440 and the NMOS 411,
This is the same configuration as the inverting amplifier 300B of FIG.
Therefore, the second input-output terminal D, the voltage change of the input node A _in is obtained is significantly inverted and amplified. As described with reference to FIG. 11, the gain of the inverting amplifier can be made larger than that using the depletion type PMOS. Since the second input / output terminal D controls the gate of the NMOS 412, the circuit of FIG.
It is possible to obtain a level shift output having a larger voltage amplitude than the amplifier circuit 400 of FIG. 9 configured using MOS.

Here, in FIG. 16, the capability of the NMOS 442 (for example, the capability defined by the drain current that can be supplied by a constant gate voltage and a drain-source voltage).
And the capability of the NMOS 402 are equalized.
When the capability of the OS 443 and the capability of the NMOS 412 are made equal, the gate potential of the PMOS 441 and the potential of the second output node A _out2 always become equal. In this way, a more simplified equivalent circuit is obtained. That is, PM in FIG.
The gate of the OS 441 and the second output node A _out2 are short-circuited, and the NMOS 442 and the NMOS 402 are connected to 1
And one NMOS 442A.
When the NMOS 3 and the NMOS 412 are replaced with one NMOS 443A, an equivalent circuit as shown in FIG. 17 is obtained. The circuit of FIG. 17 is the same as that of the amplifier circuit 400A of FIG. 15 except for the amplifier circuit of the present embodiment.

As described above, this embodiment has the following advantages. (A) In the amplifier circuit 400A of the present embodiment, an inverted amplified output having a larger gain than the amplifier circuit 400 of FIG. 9 and an amplified level shift output can be obtained. further,
Since the negative resistance circuit 420 is connected to the input terminal IN, even if the input terminal IN is biased close to V _CC , the circuit will not be cut off. Therefore, as in the case of FIG. 9 showing the fifth embodiment, excellent low power supply voltage operation, excellent operation stability, and a wide dynamic range can be obtained.
Moreover, a sense circuit that does not require the use of a depletion type MOS transistor can be obtained. (B) In this embodiment, since the level shift output is obtained from the gate of the PMOS 421 constituting the negative resistance circuit 420, a sense circuit with a small number of elements can be obtained. This means that the amplifier circuit 400A of FIG.
It is clear from the comparison between the circuit of FIG. 16 and the circuits of FIGS. (C) The application of the amplifier circuit 400A of the present embodiment is not limited to the sense circuit, and is effective when used as a level shifter or an inverting amplifier in various fields.

( Modifications ) The present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (I) In the above embodiment, NMOS is replaced with PMOS,
PMOS to NMOS, V _CC to GND, GND to V _CC
, A circuit having the same effect as the above embodiment can be obtained. (Ii) If the switch means is inserted in a current path (for example, current-to-voltage conversion circuit 200,...) In a steady state during operation, power consumption during standby can be reduced. (Iii) A first switch is inserted in series between a steady current path during operation (for example, the current-voltage conversion circuit 200,...) And the potential supply terminal V _CC, and the current path is connected to the potential A second switch is inserted in series with the supply terminal GND, and a third switch is provided at a connection point between the first switch and the second switch. A potential supply means for supplying a predetermined potential to the switch means may be provided. With this configuration, power consumption during standby can be reduced, and a desired connection point can be precharged to a predetermined potential during standby, so that a sense circuit that can quickly shift from the standby state to the operation state can be obtained. .
Further, the first switch means may also serve as, for example, a transistor for a data line load.

[0059]

As described above in detail, according to the first aspect, the load means is connected between the input terminal and the first potential supply terminal, and the input terminal is connected to the second potential supply terminal. And a current-to-voltage conversion circuit, and an input node of an inverting amplifier for controlling the current-to-voltage conversion circuit is directly connected to an input terminal of the sense circuit. Therefore, a sense circuit having excellent operation stability can be obtained, and a sense circuit capable of independently adjusting the magnitude of the output amplitude and the gain of the circuit can be obtained.
In addition, since the inverting amplifier is configured to include the depletion type MOS transistor, the input terminal can be biased to, for example, near V _CC , and a device excellent in low power supply voltage operation can be obtained. According to the second invention, the load means is a MOS transistor.
Since it is equipped with a star and a level shifter,
The linearity is improved and the dynamic range can be expanded.

According to the third aspect , since the load means includes the level shifter and the second MOS transistor controlled by the level shifter, the load means is excellent in the low power supply voltage operation which is the effect of the first aspect, and The characteristics of the load means can be improved without impairing effects such as excellent operation stability, and a sense circuit having a wide dynamic range can be obtained. Further, the load means of the present invention is effective even when used as a load circuit in another field requiring similar characteristics other than the sense circuit. According to the fourth or fifth aspect , the sense circuit includes a second MOS transistor serving as a load unit, a current-voltage conversion circuit, a level shift output for controlling the second MOS transistor for the load unit, and a current voltage. And an amplifier circuit for outputting an inverted amplified signal for controlling the conversion circuit. An input node of the amplifier circuit is connected to an input terminal of the sense circuit. Further, the amplification circuit has a first conductivity type depletion type M having a gate connected to the input node.
An OS transistor (or a negative resistance circuit) , a third MOS transistor of the second conductivity type, and a current mirror circuit including the second conductivity type MOS transistor are provided.

Therefore, the input voltage signal is
Is level-shifted, and a greatly amplified level-shifted output is obtained, so that a sense circuit having a wider dynamic range can be obtained. In addition, the level shift output and the inverted amplified output can be obtained by one amplifier circuit, so that the number of elements can be reduced. Furthermore, since the sense circuit is configured using the amplifier circuit, the input terminal of the sense circuit can be biased to, for example, near V _CC , as in the first invention, and is excellent in low power supply voltage operation and operation stability. In addition, the output voltage amplitude and the circuit gain can be adjusted independently.
Also, the application of the amplifier circuit of the present invention is not limited to the sense circuit,
It is effective when used as a level shifter in various other fields.

According to the sixth aspect, the sense circuit comprises a load
Means, a current-voltage conversion circuit, and the current-voltage conversion circuit.
And an inverting amplifier for controlling the input node of the inverting amplifier.
Connected directly to the input terminal of the sense circuit.
The inverting amplifier is composed of a negative resistance circuit, a second resistance means, and the like.
Has formed. Therefore, the gain of the inverting amplifier can be increased.
Thus, a sense circuit having a large gain can be obtained. And negative
Resistive circuit uses depletion type MOS transistor
Because it can be configured without any need, the sense
A circuit is obtained. In addition, the sense amplifier is
The sense circuit, as in the first invention.
Input terminal can be biased to near V _CC, for example ,
Excellent voltage operation, excellent operation stability, and output voltage
Amplitude and circuit gain can be adjusted independently. In addition, the present invention
The application of the inverting amplifier is not limited to the sense circuit,
Useful as an inverting amplifier in the field.

According to the seventh and eighth aspects , the sense circuit
Controls the load means, the current-voltage conversion circuit, and the load means
Level shift output and current-voltage conversion circuit
An amplification circuit that outputs an inverted amplification signal.
Input node of the circuit directly to the input terminal of the sense circuit.
ing. Further, the amplifier circuit is connected to a negative resistance circuit and a second resistance circuit.
In the negative resistance circuit.
And a first MOS provided between the first and second input / output terminals.
Level shift output is obtained from the gate of the transistor.
I'm trying. With this configuration,
With the inverted output amplified well,
A bell shift output is obtained, the gain is large,
A sense circuit with a wide mix range can be obtained. And this
Configuration uses a depletion type MOS transistor.
No sense circuit can be obtained with fewer manufacturing processes
It is. Furthermore, a sense circuit was configured using an amplifier circuit.
Therefore, similarly to the first invention, the input terminal of the sense circuit is
For example, because it can be biased near V _CC , low power supply voltage operation
Excellent in operation stability, output voltage amplitude and circuit gain
As a result, a sense circuit capable of independently adjusting the input and output can be obtained.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a sense circuit showing a first embodiment of the present invention.

FIG. 2 is a main part circuit diagram of a memory circuit including a conventional sense circuit.

FIG. 3 is an input / output characteristic diagram of the circuits 1 and 2 of FIG. 2;

FIG. 4 is a circuit diagram of a sense circuit according to a second embodiment of the present invention.

5 is an input / output characteristic diagram of the circuits 1 and 2 of FIG.

FIG. 6 is a circuit diagram of a sense circuit showing a third embodiment of the present invention.

FIG. 7 is a circuit diagram of a sense circuit showing a fourth embodiment of the present invention.

8 is a characteristic diagram of the data line load circuit 100A of FIG.

FIG. 9 is a circuit diagram of a sense circuit according to a fifth embodiment of the present invention.

FIG. 10 is an operation characteristic diagram of the amplifier circuit 400 of FIG. 9;

FIG. 11 is a circuit diagram of a sense circuit according to a sixth embodiment of the present invention.

12 is an operation characteristic diagram of the inverting amplifier 300B of FIG.

FIG. 13 is an operation explanatory diagram of the inverting amplifier 300B of FIG. 11;

14 is an input / output characteristic diagram of the circuits 1 and 2 of FIG.

FIG. 15 is a circuit diagram of a sense circuit according to a seventh embodiment of the present invention.

FIG. 16 is a circuit diagram showing a modified circuit of the amplifier circuit 400 of FIG.

17 is an equivalent circuit diagram of FIG.

[Explanation of symbols]

100, 100A Data line load circuit 101 PMOS 102 Level shifter 200 Current-voltage conversion circuit 201 PMOS 210 Resistance means 211 NMOS 300, 300A, 300B Inverting amplifier 301 Depletion type PMOS 310 Resistance means 311 NMOS 320 Negative resistance circuit 321 PMOS 322, 323 NMOS 400, 400A Amplification circuit 401 Depletion type PMOS 402 NMOS 410 Current mirror circuit 411, 412 NMOS 420, 440 Negative resistance circuit 421, 441 PMOS 422, 423, 442, 443 NMOS

──────────────────────────────────────────────────の Continued on the front page (58) Fields surveyed (Int. Cl. ⁷ , DB name) G11C ⁷ /00-8/04 G11C 11/00 G11C 16/00-17/00 G11C 29/00 H01L 27 / 10 H03K 5/02 EPAT (QUESTEL)

Claims (8)

(57) [Claims] A load means connected between an input terminal and a first potential supply terminal; a current-voltage conversion circuit connected between the input terminal and a second potential supply terminal; An inverting amplifier for controlling a voltage converting circuit, wherein the current-voltage converting circuit is connected between the input terminal and the output terminal and has a gate connected to an output node of the inverting amplifier. And a first terminal connected between the output terminal and the second potential supply terminal.
Wherein the inverting amplifier includes a first conductivity type depletion type MOS transistor and a second resistive means connected in series, and an input node of the inverting amplifier is connected to the sense node. A sense circuit, which is connected to an input terminal of the circuit. 2. The method according to claim 1, wherein the input terminal is connected to the first potential supply terminal.
Connected load means, the input terminal and a second potential supply
A current-voltage conversion circuit connected between the terminal and the terminal;
An inverting amplifier for controlling a voltage conversion circuit, wherein the current-to-voltage conversion circuit is connected between the input terminal and the output terminal.
And the gate is connected to the output node of the inverting amplifier.
A first conductivity type MOS transistor connected to the
A first terminal connected between the terminal and the second potential supply terminal;
A resistance means, the input node of the inverting amplifier being connected to the input of the sense circuit.
Terminal, wherein the load means includes a first potential supply terminal and the input terminal.
A MOS transistor connected between the input terminal and the input terminal;
The MOS transistor
And a level shifter for controlling the gate of the device
Sense circuit. 3. Between an input terminal and a first potential supply terminal.
Connected load means, the input terminal and a second potential supply
A current-voltage conversion circuit connected between the terminal and the terminal;
An inverting amplifier for controlling a voltage conversion circuit, wherein the current-to-voltage conversion circuit is connected between the input terminal and the output terminal.
The gate is connected to the output node of the inverting amplifier.
A first MOS transistor of the first conductivity type continued
Connected between the output terminal and the second potential supply terminal.
And a first resistor means, wherein the inverting amplifier has an input node connected to the input terminal of the sense circuit.
Connected to an input terminal, wherein the load means includes the input terminal and the first potential supply terminal.
Second MOS transistor of the first conductivity type connected between
A level shifter and a level shifter.
A power node connected to the input terminal;
Output node is the gate of the second MOS transistor
A sense circuit characterized by being connected to. 4. Between an input terminal and a first potential supply terminal.
Connected load means, the input terminal and a second potential supply
A current-voltage conversion circuit connected between the
Current-to-voltage converter having a first output node and first and second output nodes.
An amplifier circuit for controlling a circuit, wherein the current-to-voltage conversion circuit
And a gate connected between the first and second output nodes of the amplifier circuit.
First MOS transistor of the first conductivity type connected to
Between the output terminal and the second potential supply terminal.
And a first resistance means connected to the sense circuit.
Te, said load means, the said input terminal a first potential supply terminal
And a gate connected to the second output of the amplifier circuit.
Second MOS transistor of first conductivity type connected to node
The amplifier circuit has a gate connected to an input node of the amplifier circuit.
Connected to a first output node of the amplifier circuit.
Connected first conduction type depletion type MOS transistor
And a gate connected to the input node of the amplifier circuit.
Source is connected to a second output node of the amplifier circuit.
A third MOS transistor of the second conductivity type and a current input
A terminal connected to a first output node of the amplifier circuit;
An output terminal connected to a second output node of the amplifier circuit;
Mirror of second conductivity type MOS transistor configuration
And an input node of the amplifier circuit is connected to the input terminal.
A sense circuit. 5. Between an input terminal and a first potential supply terminal.
Connected load means, the input terminal and a second potential supply
A current-voltage conversion circuit connected between the
Current-to-voltage converter having a first output node and first and second output nodes.
An amplifier circuit for controlling a circuit, wherein the current-to-voltage conversion circuit
And a gate connected between the first and second output nodes of the amplifier circuit.
First MOS transistor of the first conductivity type connected to
Between the output terminal and the second potential supply terminal.
And a first resistance means connected to the sense circuit.
Te, said load means, the said input terminal a first potential supply terminal
And a gate connected to the second output of the amplifier circuit.
Second MOS transistor of first conductivity type connected to node
Amplifying circuit , wherein the amplifying circuit has a
The resistance value changes and the corresponding power supply current is amplified
A negative resistance circuit for supplying a first output node of the circuit;
Source is connected to the input node of the amplifier circuit and the source is
A second conductivity type connected to a second output node of the amplifier circuit
The third MOS transistor and the current input terminal
Current output terminal connected to the first output node of the width circuit
A second conductivity type connected to a second output node of the amplifier circuit
MOS transistor configuration current mirror circuit
And an input node of the amplifier circuit is connected to the input terminal.
A sense circuit. 6. A circuit between an input terminal and a first potential supply terminal.
Connected load means, the input terminal and a second potential supply
A current-voltage conversion circuit connected between the terminal and the terminal;
An inverting amplifier for controlling a voltage conversion circuit, wherein the current-to-voltage conversion circuit is connected between the input terminal and the output terminal.
And the gate is connected to the output node of the inverting amplifier.
A first conductivity type MOS transistor connected to the
A first terminal connected between the terminal and the second potential supply terminal;
The inverting amplifier has an input node connected to the input terminal.
A negative resistance circuit connected in series and in series
Resistance means, wherein the negative resistance circuit is connected to an input node of the inverting amplifier.
Connected directly to the connected control terminal and the first potential supply terminal.
Is a first input / output terminal connected via switch means
An output node of the inverting amplifier and the second resistor
And a second input / output terminal connected to the stage.
Sense circuit 7. Between an input terminal and a first potential supply terminal.
Connected load means, the input terminal and a second potential supply
A current-voltage conversion circuit connected between the
Current-to-voltage converter having a first output node and first and second output nodes.
An amplifier circuit for controlling a circuit, wherein the current-to-voltage conversion circuit
And a gate connected between the first and second output nodes of the amplifier circuit.
A first conductivity type MOS transistor connected to
Connected between an output terminal and the second potential supply terminal
A first resistance means, wherein the amplifier circuit has an input node connected to the input terminal.
And a second resistor connected in series and connected in series.
And the negative resistance circuit is connected to an input node of the amplification circuit.
Control terminal and the first potential supply terminal directly or
A first input / output terminal connected via switch means;
A first output node of the amplifier circuit and the second resistor
A second input / output terminal connected to the stage, and a second
And an output terminal connected to the second output node.
A sense circuit. 8. The negative resistance circuit has a source connected to the first input / output terminal and a drain connected to the second input / output terminal.
Of the first conductivity type respectively connected to the input / output terminals of
A MOS transistor; a drain connected to the first potential supply terminal;
The control terminal has a source connected to the gate of the first MOS transistor.
And the output terminal of the negative resistance circuit, respectively.
A second MOS transistor of the second conductivity type and a drain connected to a source of the second MOS transistor,
A gate is connected to the second input / output terminal, and a source is connected to the second input / output terminal.
A third of a second conductivity type respectively connected to a potential supply terminal;
8. The sense circuit according to claim 6 , further comprising a MOS transistor.
Road.