JP4340918B2 - Digital protection controller - Google Patents

Description

  The present invention relates to a digital protection control device, and more particularly to a digital protection control device suitable for improving the expandability of components constituting the digital protection control device and simplifying a monitoring mechanism.

For example, as described in Non-Patent Document 1, a conventional digital protection control device includes, as constituent elements, an analog input unit, a digital arithmetic processing unit including a human interface unit, an input / output unit,
An accident detection unit and a communication interface such as PCM communication are provided. A similar digital protection control device is described in Patent Document 1.

  In these digital protection control devices, an analog input unit and a PCM communication interface unit are connected in parallel to a parallel system bus to which a digital arithmetic processing unit is connected, and an input / output unit is connected to an I / O bus. Connected in parallel. In these parallel buses, the digital arithmetic processing unit serves as a bus master to perform bus control and transfer data between the components.

JP 2004-64892 A Development of New Digital Relay (EDR + Series), Lecture Number 215, IEEJ Power and Energy Division Conference

  However, the conventional digital protection control apparatus has a problem that the number of signal lines increases because a parallel bus is used for data transfer between the components. Further, the number of interface circuits increases, and there is a problem that heat generation due to resistance for signal termination is large. Furthermore, when a failure occurs in each component, the arithmetic processing unit that is a bus master reads and checks the data, and finally outputs an abnormality to the output unit. Therefore, there is a restriction that each component cannot output its own abnormality spontaneously. Also, in order to expand the functions of the digital protection control device, it is necessary to connect each printed circuit board of the components related to the expansion to the parallel bus, and it is difficult to expand beyond the unit size, so it is configured as a separate unit. It was necessary and the flexibility of system expansion was limited.

  Therefore, it is conceivable to use a parallel bus as a serial bus. However, in the case of a serial bus, a signal line indicating abnormality or soundness must be provided specially, and wiring saving cannot be achieved. In addition, if the serial bus itself is abnormal, failure information cannot be issued to the outside even if an abnormality is detected by the arithmetic processing unit. Therefore, even if a fatal abnormality occurs on the digital protection control device side. However, there is a problem that it does not behave as normal to the outside, and malfunctions due to a grid fault.

  On the other hand, a dedicated microprocessor monitoring means such as a watchdog timer or a free-run timer can be provided in the bus master, and the monitoring result can be sent to the I / O unit side via a dedicated signal line. There is a problem that cannot cope with wiring saving. Another problem is that the soundness of the serial bus itself is not taken into consideration.

It is an object of the present invention to improve the expandability of the digital protection control device and to make it possible to report abnormality of each arithmetic unit using a serial bus without providing a dedicated signal line , simplify the monitoring mechanism, and improve the reliability. And

  In order to solve the above-described problems, the present invention includes a CPU calculation unit that takes in an electric quantity of a power system and executes a protection control calculation by digital calculation, and a communication control unit that controls data transfer between other units. A digital I / O unit for inputting / outputting digital information to / from an external device including a system protection device and a communication control unit for controlling data transfer with other units A digital protection control device including a / O unit and a system bus connected to a communication control unit provided in each unit is an object.

In particular, the system bus is formed by a serial bus, and the communication control unit of each arithmetic unit includes a global memory having a storage area corresponding to each unit accessible by the CPU arithmetic unit, the communication control unit provided in the unit, via said global memory run for each setting cycle data transfer between the other units, the CPU arithmetic unit of the respective arithmetic unit, the digital I / O The transfer data to be transferred to the unit is appended with a signal indicating the presence / absence of its own abnormality and stored in the global memory, and the digital I / O unit externally receives a signal indicating the presence / absence of the abnormality for a set time. An abnormality detecting means for outputting an alarm is provided.

  In other words, a serial bus is adopted as a system bus, and data transfer with other units is executed in a predetermined order via a global memory, thereby reducing wiring and expanding functions. Can be satisfied. In particular, there is an effect that the degree of freedom of the combination of the unit units constituting the digital protection control device is increased. For example, a human interface unit for transmitting / receiving data to / from the outside of the system or a PCM communication unit can be easily added.

  In addition, by updating all storage areas of the global memory at each set cycle defined by the protection control computation cycle of the computation unit, data is guaranteed without impairing the digital protection control function and reliability is improved. Can be improved.

Also, the transfer data transferred from each arithmetic unit to the digital I / O unit is output with a signal indicating the presence or absence of its own abnormality, and the signal indicating the presence or absence of abnormality is received by the digital I / O unit for a set time. Since the abnormality is detected when not performed, the abnormality of each arithmetic unit can be reported using the serial bus without providing a dedicated signal line. Thereby, wiring saving and a monitoring mechanism can be simplified, and reliability can be ensured.

  In the case of the present invention, the signal indicating the presence or absence of an abnormality may be an alternating signal that repeats 0 or 1 alternately, and the abnormality detecting means may output an alarm when the alternating signal is not input for a set time or more. Further, it is preferable that the CPU calculation unit adds the alternate signal to the transfer data of the task processing result having the lowest priority.

Further, the present invention is external when pressurized forte to the above abnormality detecting means, the communication control unit of the digital I / O unit, the communication abnormality in the frequency of the serial data received via the serial bus exceeds the set frequency The second abnormality detecting means for outputting an alarm can be provided. As a result, the soundness of the CPU operation function including the soundness of the serial bus communication mechanism can be easily confirmed without providing a dedicated signal line, so that wiring saving and high reliability can be achieved.

  According to the present invention, even if a serial bus is used as the system bus of the digital protection control device, it is possible to improve the expandability of functions, simplify the monitoring mechanism, and improve the reliability.

  Hereinafter, a digital protection control device of the present invention will be described based on examples.

  FIG. 1 shows a block diagram of an embodiment of the digital protection control apparatus of the present invention. As shown in the figure, the digital protection control device of this embodiment includes a main relay arithmetic unit 1, an accident detection arithmetic unit 2, and a plurality of digital input / output units 3i (i = 1,...) For the main relay arithmetic unit 1. N), a digital input / output unit 4 for the accident detection arithmetic unit 2, a human interface unit 5, and a PCM communication unit 6, each of which is mutually real-time via a real-time serial bus 7. It is configured to be able to transfer data.

  The main relay calculation unit 1 takes in state quantities such as voltage and current from the input converter 8 and executes main detection calculation according to a predetermined calculation process. The main relay arithmetic unit 1 receives contact information of a protective device such as an external circuit breaker and a status signal of an external device such as a display related to the digital protection control device from the digital input / output unit 3i, An operation signal is output to an external device or the like.

  The accident detection calculation unit 2 takes in the state quantity of the electric power system from the input converter 8 and executes a fail-safe accident detection calculation according to a predetermined calculation process. In addition, the accident detection arithmetic unit 2 takes in contact information of a protective device such as an external circuit breaker via the digital input / output unit 4 and outputs an operation signal to the protective device.

  The human interface unit 5 is connected to and communicates with a portable human interface 11 via a communication hub (HUB) 9 and an external network 10, and takes in operation information from an operation panel 12. The PCM communication unit 6 is connected via an optical module 13 to a PCM communication network (not shown) that is a communication network dedicated to protection.

A global memory (shared memory) 14 is provided in each unit 1, 2, 5, 6. Further, the digital input / output units 3 and 4 are provided with a shared I / O unit 15 and a watchdog timer 16 composed of an analog or digital circuit, respectively.

  Here, the basic operation of the digital protection control apparatus shown in FIG. 1 will be described. First, the main relay arithmetic unit 1 and the accident detection arithmetic unit 2 take in analog state quantity data at a constant electrical angle (for example, 7.5 °) via the input converter 8 and perform analog-digital conversion. The filtering process is performed, and the protection calculation process and the protection sequence process are periodically performed at intervals of a constant electrical angle (for example, 30 °) using the filtered state quantity data.

  As a result of computation by the main relay computation unit 1, when it is detected that an accident has occurred in the system, a shutdown command and an operation signal to an external device are output to the digital input / output unit 3i via the serial bus 7. To do. Similarly, the accident detection calculation unit 2 outputs a shut-off command and an operation signal to an external device to the digital input / output unit 4 via the serial bus 7. The interruption commands output from the main relay arithmetic unit 1 and the accident detection arithmetic unit 2 are ANDed by the power relay 17 and output to the circuit breaker as a final interruption instruction.

  As described above, according to the present embodiment, data and signals can be transmitted and received via the serial bus 7, so that significant wiring saving can be achieved. In addition, in order to expand the function of the digital protection control device, each printed circuit board of the components (units) related to the expansion can be easily connected to the serial bus 7, so that the degree of expansion is greatly improved. .

  A configuration related to communication control according to the present embodiment will be described with reference to FIG. As shown in FIG. 2, the hardware configurations of the units 1, 2, 5, and 6 are formed substantially the same. That is, each unit includes a CPU calculation unit 21, a global memory 14, a communication mechanism 22, and a pulse transformer 23. The global memory 14 is divided into areas corresponding to each unit. That is, the M-RY area for the main relay arithmetic unit 1, the FD-RY area for the accident detection arithmetic unit 2, the HI area for the human interface unit 5, the PCM communication area for the PCM communication unit 6, and the digital input / output unit 3 An M-I / O area is set.

  The CPU computing unit 21 can read / write the area of the global memory 14 and the MI / O area corresponding to itself, and can only read the other areas. The entire area of the global memory 14 can be written and read by the communication mechanism 22. In other words, each area of the global memory 14 can be accessed from each unit, but for the write operation, only the area defined for the own station can be written to guarantee the write data. In addition, each communication mechanism 22 can arbitrarily read data in the M-I / O area of the global memory 14. However, with respect to writing, only the CPU calculation unit 21 for the main relay calculation unit 1 can write to the MI / O area of the main relay calculation unit 1, and the MI / O area of the accident detection calculation unit 2 can be written. Only the CPU calculation unit 21 for the accident detection calculation unit 2 can be written. This is because the main relay arithmetic unit 1 and the accident detection arithmetic unit 2 are configured on separate boards, and the digital input / output unit 3i and the digital input / output unit 4 are separated from each other, so that it is not necessary for a single component failure. This is to prevent the operation from occurring.

  The communication mechanism 22 is connected to the serial bus 7 via the pulse transformer 23, stores transmission data input from the serial bus 7 in a specified area of the global memory 14, and stores the specified area of the global memory 14. Data is output to the serial bus 7. Each communication mechanism 22 operates to access each global memory 14 at a predetermined cycle and sequentially update data. The pulse transformer 23 is provided to electrically insulate each unit and the digital input / output units 3n and 4 from each other. Thereby, even if the communication mechanism 22 fails, the signal of the serial bus 7 is not affected. The communication mechanism 22 is provided with time management means 24.

  2, the digital input / output units 3i and 4 include a communication mechanism 22 having a time management unit 24, a pulse transformer 23, and a plurality of watchdog timers 16i (i = 1,... N), an OR circuit 26, auxiliary relay drivers 27 and 29, auxiliary relays 28 and 30, and an insulation input unit 31. An operation command or the like output from the main relay arithmetic unit 1 or the accident detection arithmetic unit 2 to an external device is fetched from the serial bus 7 via the pulse transformer 23 and the communication mechanism 24, and via the auxiliary relay driver 29 and the auxiliary relay 30. Output to the corresponding external device. A state signal from the outside is taken in via the insulation input unit 31.

  The plurality of watchdog timers 16i are constituted by so-called free-run timers, and are provided corresponding to the units 1, 2, 5, 6, etc., respectively. The watchdog timer 16i is retriggered (retriggered) in response to a binary signal (hereinafter referred to as a “sound signal”) indicating soundness input from each unit 1, 2, 5, 6 or the like via the communication mechanism 22. It has become so. That is, the sound signal is an alternating signal that is alternately switched from H to L, or from L to H, and an abnormal signal (timeout signal) when the alternating signal applied to the watchdog timer 16i does not change for a predetermined time or more. ) Is output. When an abnormal signal is output from any of the watchdog timers 16i, an alarm is output from the auxiliary relay 28 via the OR circuit 26 and the auxiliary relay driver 27 to the outside.

  Here, the configuration of the serial bus 7 of the present embodiment and the mechanism of data transmission between the units 1 to 6 will be described. The serial bus 7 is operated under conditions that guarantee the maximum delay time of the transmission time. This maximum delay time refers to the maximum delay time determined by the transmission speed and the number of components (units) connected to the serial bus 7. In general, Ethernet (registered trademark) communication is used as a communication means and TCP / IP is used as a protocol. However, although collision of data on communication is allowed, the maximum delay time is not guaranteed. In this embodiment, the time for occupying the serial bus 7 is assigned to each of the units 1 to 6 in order, and data is transmitted so that there is no data collision on the transmission line of the serial bus 7. .

  By the way, it is not a good idea to provide a dedicated signal line for transmitting a signal indicating the soundness or abnormality of each unit in the reduced serial bus 7. Therefore, in this embodiment, a mechanism is employed in which the soundness of the serial bus 7 itself and each unit can be easily confirmed while maintaining wiring saving.

  First, for the real-time serial bus 7, between the units within an electrical angle (for example, 30 ° = 1.38 ms or 1.66 ms) required for real-time processing of the main relay arithmetic unit 1 and the accident detection arithmetic unit 2. If data transfer is possible, the performance of the digital protection control device of this embodiment will not be impaired.

  Further, the fact that each unit is healthy is transmitted to the shared I / O unit 15 of the digital input / output units 3 and 4 via the serial bus 7. Specifically, specific information bits are provided in advance in the format of transmission data to be transmitted between the units, and the bit information is alternately rewritten to H or L every time each unit is operated. The shared I / O unit 15 extracts the bit information from the communication data, and retriggers a previously provided watchdog timer 16i in accordance with the content of the extracted bit information. The watchdog timer 16i counts up when not triggered and operates to output an abnormal signal when a predetermined set time has elapsed. The auxiliary relay provided in the shared I / O unit 15 is driven by this abnormal signal, and an alarm is issued to the outside.

  Therefore, even if a dedicated signal line is not provided, when units such as the main relay arithmetic unit 1 and the accident detection arithmetic unit 2 become abnormal and no sound signal is output, the watch dog timer 16 of the shared I / O unit 15 naturally Since the time is up, it can be easily recognized that an abnormality has occurred. Similarly, when an abnormality occurs in the serial bus 7, the watchdog timer 16 is also timed up, so that it can be easily recognized that the system is abnormal.

As shown in FIG. 3, the communication control of each communication mechanism 22 is performed for each communication mechanism 22 of units 1, 2, 5, 6 connected to the global memory 14. The right to access the serial bus 7 in every cycle T _{LAN in} order is given. The communication mechanism 22 given the access right to the serial bus 7 accesses the serial bus 7 and writes data to the global memory 14. The communication mechanism 22 having no access right to the serial bus 7 waits for the access right to come around. When the operation of one communication mechanism 22 is completed, the right to access the serial bus 7 is passed to the next communication mechanism 22. The accessible communication mechanism 22 accesses the serial bus 7 and writes data to the global memory 14. Such operations are performed in order, and the access right is passed to the communication mechanism 22 again. These series of operations are performed in a fixed time for each time T _CPU to guarantee real-time performance. That is, the maximum delay time for data transfer is guaranteed.

FIG. 4 shows a time chart of the detailed operation of the real-time communication control of the serial bus 7. This figure shows the operation procedure among the CPU calculation unit 21, the global memory 14, the communication mechanism 22, and the serial bus 7 side of each unit in time series. First, each CPU calculation unit 21 writes its own station data composed of an information part and a data part to the global memory 14 at every fixed period T _CPU period (for example, every 30 electrical degrees). In this written signal, 1 bit of sound signal indicating soundness is secured, and if the content of sound signal is normal, it changes from the current H (or L) state to the opposite state L (or H). And send it out.

  The communication mechanism 22 performs a transmission operation while sequentially rotating tokens, which are the right to access at regular intervals, with other communication mechanisms 22. The communication mechanism 22 detects a token addressed to the local station, transmits the local station data in the global memory 14 to the serial bus 7 side, waits for a response signal, sends a transmission end information after confirming the response signal.

Thereafter, the token is passed to the next station, and the series of cycles is completed. As a matter of course, this series of cycles is set to a sufficiently short interval since real-time performance cannot be guaranteed unless it is shorter than the T _CPU cycle. Moreover, the transfer operation time of all stations is also made shorter than the T _CPU cycle.

  In this way, information can be sent and received in real time via the serial bus 7. Of course, since it is a serial signal, it is possible to detect communication failure and correct data by adding a redundant code, and it goes without saying that high reliability can be achieved.

The operation timing of the present embodiment will be described with reference to FIGS. In FIG. 5, CPU calculating section an interrupt signal is input every period T _OP, interrupt process corresponding to the interrupt signal, for example, a digital filter operation as a real-time processing, protection processing is executed and the sequence processing.

  Next, task processing with priority registered as task processing of the real-time OS is executed. In this embodiment, description will be made assuming that the priority is in order from task 1. When the interrupt process is completed, the task process 2 is activated, and then the task 1 having a higher priority is activated, and the process shifts to the task 1. An interrupt occurs during task 1 processing, and interrupt processing with higher priority than task processing is executed.

  When the interrupt process is completed, task 1 executes the subsequent process. After the task 1 process ends, the process of task 2 that was being processed is resumed and processed. Thereafter, the process of task 3 is executed. In the process of task 3, a sound signal for clearing the watchdog timer (WDT) 16i is written. For example, 1 (= H) is first written. When the process of the next task 3 is executed, 0 (= L) for clearing the WDT 16i is written. In this way, the WDT 16i operates so as to alternately write 1 and 0 within the time up time.

  The digital input / output units 3i and 4 receive data every communication cycle, but execute a WDT clear process when a WDT clear sound signal is received. The free run timer of the WDT 16i operates to increase at a constant cycle as shown in FIG. In this case, since the sound signal is normally received, no failure output is issued.

  FIG. 6 is a timing example of an abnormal case in which the CPU calculation unit 21 has stopped from the normal state shown in FIG. In the figure, the CPU is stopped when task 3 is activated. At first, the WDT clear was successfully performed by the sound signal, but the next sound signal could not be received. Therefore, the free run timer of the WDT16i continued to increase and when the time-up level was exceeded, the WDT timed out and the failure output was reported. To do. In this way, according to the present embodiment, by applying the CPU abnormality as a signal of the serial bus 7, it can be realized without having a special monitoring signal.

  FIG. 7 shows an example of timing when the CPU arithmetic unit 21 is normal but the serial bus 7 becomes abnormal. Since the CPU calculation unit 21 can operate normally, interrupt processing and task processing can be executed. However, since the serial bus 7 becomes abnormal and the sound signal is not input to the digital input / output units 3 and 4, the free run timer of the WDT 16i cannot be recleared. Accordingly, the free run timer of the WDT 16i continues to increase, and when the time-up level is exceeded, a WDT time-out occurs and a fault output is issued.

  According to this embodiment, since it is not necessary to provide a special monitoring signal line on the serial bus 7, a configuration very suitable for the serial bus 7 can be taken, and high reliability can be achieved.

  Here, an example of the internal configuration of the main relay arithmetic unit 1 (or the accident detection arithmetic unit 2) of this embodiment is shown in FIG. 8, and an internal configuration example of the human interface 5 is shown in FIG. As shown in FIG. 8, the main relay arithmetic unit 1 takes in a plurality of state quantities voltage-converted by the input converter 8 from the power system, and filters them by the analog filter 31 in order to prevent aliasing errors due to sampling. The output signal of the analog filter 31 is sequentially switched by the multiplexer 32, converted into a digital signal by the A / D converter 33, and stored in the memory 34. The microcontroller 35 takes in the state quantity converted into a digital signal from the memory 34 via the local bus 36, performs a digital filter process for removing low-order harmonic components generated at the time of a system fault, and also performs a protection operation and a sequence process. Execute. The microcontroller 35 is provided with a CPU core for executing calculations, a floating point calculation mechanism FPU, a ROM and calculation RAM for storing filter calculation programs and communication processing programs in advance, and peripheral circuits and an interrupt control mechanism. It has been. The timing control circuit 37 manages a communication cycle for each fixed cycle, and issues an interrupt signal to the CPU every 30 electrical degrees, a channel switching signal to the multiplexer 32, and an A / D converter 33. Signals such as an A / D conversion timing command and a write signal to the memory 34 are output. The communication mechanism 22 has a global memory 14 inside, and the communication mechanism 22 is connected to the serial bus 7 via a pulse transformer 23. The communication mechanism 22 operates to accumulate data written from the microcontroller 35 in the global memory 14 and distribute this data to each unit at regular intervals.

  On the other hand, the human interface 5 corresponds to two communication networks of the serial bus 7 and the Ethernet (registered trademark) 41 as shown in FIG. In the figure, the human interface 5 includes a microcontroller 42 and a controller bus 43. The controller bus 43 has a work RAM 44 for calculation and processing, a data saving memory 45, a communication mechanism 22, and a global memory built in the communication mechanism 22. 14 and the LAN communication mechanism 46 are tightly coupled. The controller 42 has the same function as the microcontroller 35 of FIG. 8, but the stored program is different. The LAN communication mechanism 46 outputs to the external network 41 via the pulse transformer 47 and takes in a signal from the external network 41. That is, the LAN communication mechanism 46 is connected to the external Ethernet (registered trademark) work 10 via the communication hub 9 shown in FIG. 1 and remotely communicates with the portable human interface 12 to exchange information. It is planned. The communication mechanism 22 is connected to the serial bus 7 via the pulse transformer 23 in the same manner as the communication mechanism 22 shown in FIG.

  FIG. 10 is a block diagram showing another embodiment of the main part of the digital protection control apparatus of the present invention. This embodiment differs from the first embodiment in that the configuration of the digital input / output units 3i and 4 is different. That is, as shown in FIG. 10, the digital input / output units 3i and 4 of this embodiment are provided with a CRC (Cyclic Redundancy Check) test circuit 54 in the communication mechanism 22, and when a CRC error is detected, an abnormality detection signal 48 is generated. The data is output to the CRC abnormality frequency detection unit 49.

  Here, the CRC test method is a generally known test method. Data (redundant data) generated by a polynomial determined in advance for CRC test is obtained for transmission data on the transmission side, and this redundancy is obtained. Data is added to the transmission data and transmitted.

As the generator polynomial, CRC-CCITT, such as P (X) = X ¹⁶ + X ¹² + X ⁵ +1, is known, and is adopted in the HDLC protocol belonging to the high level procedure. The transmission data is divided by the above generator polynomial, and the remainder of the division result is a check code. In general, it is not a division but an XOR operation with no carry.

  On the receiving side, the received data including redundant data is divided by the generator polynomial to check whether there is a remainder. When the remainder is 0, it is determined that there is no error, and when it is not 0, it is determined that there is an error. Since this determination is performed for each message, it can be checked for each communication. For example, a transmission abnormality that occurs due to a temporary loss of data may be recovered at the next transmission timing. For this reason, frequency monitoring is performed, and if transient data loss frequently occurs, it is regarded as a prior phenomenon of permanent failure, and failure is determined early.

  That is, the CRC abnormality frequency detection unit 49 detects the frequency of the CRC abnormality detection signal 48, and when the frequency exceeds the set value, an alarm of an abnormal state is externally given via the auxiliary relay driver 51 and the auxiliary relay 52. It is designed to output. For example, an alarm signal is output when the CRC abnormality detection signal 48 is generated twice or more while the 10s timer 50 counts for 10 seconds. The 10s timer 50 outputs a clear signal 53 for erasing the stored contents of the CRC abnormality frequency detection unit 49 for every 10s count signal.

  That is, a general communication LSI has a function of detecting a CRC abnormality, but the abnormality information cannot be read out without a host controller. In this embodiment, an abnormal signal is positively output without a host controller.

  In particular, in the case of the first embodiment, in the case where some communication abnormality does not return to normal, the WDT 16i is not cleared, so that a device failure signal is finally output to the outside. If the communication abnormality is transient, there is a concern that the communication quality is poor. Specifically, transmission in the protection relay unit may be affected by disturbance noise or a phenomenon that the communication IC is being broken. In such a situation, even in an unstable period of operation until an abnormality is determined by WDT, a failure can be detected by frequency monitoring, and an external alarm can be issued. That is, since the CRC test can determine whether each communication is normal or abnormal, it is possible to eliminate the blind spot of monitoring when a transient abnormality continues for a long time. Therefore, if the CRC abnormality signal is monitored, it is possible to grasp the quality of the communication quality in the digital protection control apparatus, and the communication mechanism can be monitored from the monitoring result.

  FIG. 11 shows a timing example of the operation of the embodiment shown in FIG. As shown in the figure, if the CRC check is normal, an abnormal signal is not output, so that no abnormal output is output to the outside. In addition, when a CRC abnormality is detected, the digital input / output units 3 and 4 configured as described above can report a continuous communication abnormality state to the outside without mounting a controller.

  That is, in the system with reduced wiring as in the present embodiment, the status monitoring of serial communication becomes very important, and by implementing such means, a highly reliable system can be constructed.

  In addition, according to the present invention, since data transmitted / received between a plurality of components of the digital protection control device can be transmitted via a serial bus, the CPU calculation unit, the input unit, and the output unit are not in the same unit, but are separated. Can be configured even if installed in a different position. As a result, it can also be applied to I / O device control applications that are distributed.

It is a block block diagram of Example 1 of the digital protection control apparatus of the present invention. FIG. 3 is a block configuration diagram illustrating a detailed configuration of a characteristic part of the first embodiment. It is a figure explaining the operation | movement outline | summary of the communication control of Example 1. FIG. 3 is a timing chart illustrating an operation of communication control according to the first exemplary embodiment. It is a detailed block diagram of the main relay arithmetic unit or the accident detection arithmetic unit of Example 1. FIG. 2 is a detailed configuration diagram of a human interface unit according to the first embodiment. It is a figure which shows an example of the operation timing in the normal time of the arithmetic unit etc. of Example 1. FIG. It is a figure which shows an example of the operation timing at the time of abnormality of the arithmetic unit of Example 1, etc. FIG. 6 is a diagram illustrating an example of operation timing when the communication system according to the first embodiment is abnormal. It is a block block diagram which shows the detailed structure of the characteristic part of Example 2 of the digital protection control apparatus of this invention. FIG. 10 is a diagram illustrating an example of operation timing when the communication system according to the second embodiment is abnormal.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Main relay arithmetic unit 2 Accident detection arithmetic unit 3i Digital input / output unit 4 Digital input / output unit 5 Human interface unit 6 PCM communication unit 7 Serial bus 14 Global memory 15 Shared I / O part 16 Watchdog timer 22 Communication mechanism

Claims (5)

Includes a CPU operation unit that captures the amount of electricity in the power system and executes a protection control operation by digital operation and a plurality of operation units including a communication control unit that controls data transfer between other units, and a system protection device A digital I / O unit having an I / O unit for inputting / outputting digital information to / from an external device and a communication control unit for controlling data transfer with other units, and provided in each of the units In a digital protection control device comprising a system bus connected to a communication control unit,
The system bus is formed by a serial bus,
The communication control unit of each arithmetic unit includes a global memory having a storage area corresponding to each unit accessible by the CPU arithmetic unit,
The communication control unit provided in each unit executes data transfer with other units via the global memory for each set period,
The CPU arithmetic unit of each arithmetic unit attaches a signal indicating the presence or absence of its own abnormality to transfer data to be transferred to the digital I / O unit and stores it in the global memory,
The digital protection control device, wherein the digital I / O unit has an abnormality detecting means for outputting an alarm to the outside when the signal indicating the presence / absence of the abnormality is not received for a set time. In claim 1,
The signal indicating the presence or absence of abnormality is an alternating signal that repeats 0 or 1 alternately,
The digital protection control device according to claim 1, wherein the abnormality detection means outputs an alarm when the alternating signal is not input for a set time or longer. In claim 2,
The CPU operation unit adds the alternate signal to transfer data of a task processing result having the lowest priority. In claim 1,
The communication control unit of the digital I / O unit has second abnormality detection means for outputting an alarm to the outside when the frequency of communication abnormality of serial data received via the serial bus exceeds a set frequency. A digital protection control device. In claim 2,
The abnormality detection means is provided corresponding to each arithmetic unit, and is re-triggered when the alternating signal is input, and outputs a plurality of watches when the alternating signal is not input for the set time or more. A digital protection control device comprising a dog timer and outputting an alarm by an OR circuit output of an abnormality signal of the plurality of watchdog timers.

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