JP4715040B2 - Semiconductor device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a power semiconductor module applied to a converter, an inverter and the like such as a switching power supply device.
[0002]
[Prior art]
In recent years, demand for high-capacity products in the 40kW to 1MW class in power converters such as industrial inverters has increased, and power devices used in these devices are required to be further downsized, highly reliable, and easy to use. It has been. In such a power device, the current to be controlled is several hundred A or more, and the generated loss (heat) in the semiconductor element is several hundred W or more. Therefore, the power module is required to have a thermal design that takes heat dissipation and Joule heat into consideration.
[0003]
A cross-sectional structure of a general IGBT module is shown in FIG. Here, heat generated in the semiconductor element (chip 1) moves in the order of insulating substrate 2 → heat sink (Cu base 3) → cooling body (heat radiation fin not shown), and is radiated to the outside. Power modules are designed to save space and increase capacity. For this reason, the thermal resistance of the package increases, and there is a concern that the chip junction temperature (Tj) will increase during actual use. In order to keep Tj below the guaranteed temperature of 125 ° C, it is necessary to reduce the loss of the chip and to properly design the package. However, in order to increase the capacity, it is common to use a plurality of chips having the same characteristics connected in parallel. In order to turn on and off at the same timing when these chips are connected in parallel, they are on a straight line. It was arranged.
[0004]
[Problems to be solved by the invention]
When multiple chips are connected in parallel in order to increase the capacity of the power module, these multiple chips are switched on and off at the same time, resulting in an inevitable increase in temperature at the location of the chips. The problem of interference arises, and it is conceivable that the characteristics are deteriorated due to a thermal failure.
An object of the present invention is to provide a structure that efficiently diffuses heat generated in a chip within a package and suppresses an increase in Tj (ΔTj).
[0005]
[Means for Solving the Problems]
To achieve the above object, according to the present invention, in which a plurality of transistors chips form one switching element is connected in parallel on the insulating substrate, the transistor chips are arranged in a zigzag pattern on an insulating substrate Suppose that It is preferable that a plurality of the switching elements are formed to serve as switching elements for each arm of the inverter circuit. Also, a diode chip is connected in parallel to the transistor chip. And it is good to interpose the connection body for resistance reduction in the connection part of the emitter of the transistor chip on an insulating substrate. In this case, the junction between the emitter of the transistor chip and the connection body is a bonding wire. Assume that the semiconductor device has a rating of 300 A / 1200 V or 450 A / 1200 V.
[0006]
DETAILED DESCRIPTION OF THE INVENTION
The chip layout was examined by the finite element method analysis using the simple model shown in FIG. 1 is a chip, 2 is an insulating substrate with copper patterns formed on both sides, 3 is a Cu base, and 4 is a cooling body. From the analysis results shown in FIG. 3, it can be seen that by providing an offset amount to the two chips 1 and arranging them diagonally on the package, thermal interference can be reduced and ΔTj can be suppressed in the same manner as when the chip interval is increased. . Tj is the temperature of the chip center. In addition, this diagonal arrangement allows AlN (λ = 170 W / mW), which has a high thermal conductivity, which has been used for large rated modules, even for an insulating substrate made of Al ₂ O ₃ (λ = 20 W / mK). It can be seen that ΔTj equivalent to that using mK) can be realized.
2 and 3, it can be seen that Tj is affected by the chip arrangement. Therefore, in order to suppress the rise of Tj, the IGBT chips are arranged diagonally (staggered) as shown in FIG. 4, and Al ₂ O ₃ is used for the insulating substrate 2. The large chip 1a is an IGBT chip, and the small chip 1b is a diode chip. In this case, three IGBT chips 1a are connected in parallel to form one switching element, and six sets of this switching element are arranged to form each arm of the inverter. The diode chip 1b is for freewheeling. In this case, one diode chip 1b is provided for one IGBT chip. However, one or two diode chips 1b may be provided for three IGBT chips 1a connected in parallel. Reference numeral 9 denotes a through hole formed in the Cu base 3 for reducing the stress of the Cu base 3 being applied to the insulating substrate 2. What is important here is to arrange the IGBT chips 1a in a staggered manner. In order to confirm the effect of chip placement, heat conduction analysis and temperature measurement experiments were conducted. The analysis target was a 300A / 1,200V rated package, the heat generation was about 70W / chip, the cooling conditions were ambient temperature Ta = 25 ℃, forced air cooling (v = 3.5m / s). FIG. 5 is a temperature distribution diagram by thermal analysis, and FIG. 6 is a temperature distribution diagram in an experiment by thermography. Both the simulation results of FIG. 5 and the actual measurement results of FIG. 6 do not cause only a specific chip of the plurality of IGBT chips to become high temperature, and it can be confirmed that the heat generated in the chips is efficiently diffused in the package. This is a result of the IGBT chip being arranged in a staggered manner to suppress thermal interference and effectively use the entire package for heat conduction to the cooling body.
Fig. 7 shows the simulation results assuming that the 450A / 1,200V rated package is operated at fc = 1kHz and 100% load. In actual operation, both IGBT and diode (Free Wheeling Diode) chips generate heat, but in this case as well, it can be confirmed from the temperature distribution diagram that only a specific chip in each phase does not become hot due to thermal interference. .
[0007]
FIG. 1 shows a part of the internal wiring model, where (a) is a plan view with the lid removed, and (b) is a partial cross-sectional view of the side. In the thin package which is the feature of this embodiment, conventional aerial wiring with a copper bar is difficult, and it is necessary to keep the height of the connection wiring between the terminal and the insulating substrate and between the insulating substrate and the insulating substrate low. The challenge is to design the wire heat generation temperature by flowing a large current of up to 450A (1,200V system) through a thin aluminum wire below the heat resistance temperature of the sealing silicone gel.
[0008]
DC450A was allowed to flow from the IN part (electrode), passed through the aluminum wire and copper wiring, and flowed out from the OUT part (the end of the copper wiring), and the energization conditions were analyzed at 450A (t = 60sec) as the inverter operating conditions. For the sake of analysis, the wire shape was a prism, but a structural model was created so that it was equal to the cross-sectional area of the actual wire. The analysis software was SOLIDIS3D (manufactured by ISE, Switzerland), and the current density distribution and temperature distribution after 60 seconds were calculated in transient analysis mode.
When the relationship between the wire temperature and the wire position at 450 A (t = 60 sec) energization by analysis and measurement (thermography) was observed, it was confirmed that the analysis result almost coincided with the actual measurement value. In the heat generation state, it was clarified that the current intensively flows through the wire with the shortest current path (temperature 148 ° C) and exceeds the heat resistance temperature of the sealing gel. As measures to improve current concentration, (1) R was added to the corner of the copper wiring on the insulating substrate, and (2) R attachment and thickening of the aluminum wire were verified. As a result of analyzing the improvement measures (1) and (2), the current unbalance was improved by adding R to the copper wiring corner portion of the current path, and the temperature distribution according to the wire position became gentle. Furthermore, we found that thickening the aluminum wire lowered the resistance and lowered the entire wire temperature to 94 ° C.
Looking at the results of wire position and current density analyzed in improvement measure (2), by attaching R, the current density difference between wires becomes smaller than before improvement, and the value of current density itself is lowered by thickening. ing. From the above, it was shown that the R wiring at the corner of the copper wiring and the thickening of the wire are effective in improving the current imbalance and reducing the rise in the wire temperature, and were able to be kept within the target temperature.
[0009]
In the product example shown in FIG. 1, switching elements are divided into six insulating substrates 2 and mounted side by side on a Cu base 3. The Cu base 3 has a plate thickness of 4 mm and an outer size of 122 mm in length. The width is 162 mm. On the other hand, each insulating substrate 2 is a ceramic in which a copper pattern is bonded on both sides to an alumina plate having a plate thickness of 0.32 mm, and its outer size is 38 mm long and 41.9 mm wide. The Cu base 3 and each insulating substrate 2 are soldered with Sn—Pb solder, and the thickness of the soldering layer is 0.15 mm. On each insulating substrate 2, three IGBT chips 1a are arranged in a staggered manner and are electrically connected in parallel. Three diode chips 1b are arranged so as to correspond to the IGBT chip 1a so that the diode and the IGBT are adjacent to each other at a position where the IGBT chip 1a is not mounted. Providing the diode chip 1b adjacent to the IGBT chip 1a in this way facilitates stitch bonding for connecting the emitter of the transistor and the anode of the diode, and thus has an advantage of easy manufacture. Reference numeral 5 denotes a main terminal through which a main current flows, and reference numeral 6 denotes a control terminal for giving a control signal. In this example, the main terminal on the left side is in the order of the collector of the upper arm and the emitter of the lower arm from the bottom, and the main terminal on the right side is the intermediate output terminals of U, V, and W. Further, a copper plate connector 7 having a width of 4 mm and a plate thickness of 1.5 mm is interposed on a copper pattern to which the emitter of the IGBT chip on the upper arm side is connected by a wire. The connection body 7 may be connected simultaneously when die bonding of the chip. With this connection body 7, the resistance at the main terminal can be reduced from 2 mΩ to 1 mΩ, and the heat generation of the entire package is reduced and the voltage drop is reduced. In addition, the copper pattern to be wire bonded in the portion where the main current flows is likely to cause current concentration, and heat is easily generated by the copper pattern. Although it is preferable, it may not be a straight line due to the layout layout, and may be formed in an L shape. When such an L-shape is used, the width of the copper pattern at the part to be wire bonded may be made wider than the width of the other part to prevent current concentration.
[0010]
In the above embodiment, the arrangement of the switching element for the inverter has been described. However, the present invention connects at least two transistor chips (bipolar, MOS, IGBT, etc.) in parallel to increase the capacity, As long as the switching element is turned off, the present invention can be applied to a switching element of an ignition circuit for an internal combustion engine of an automobile, for example, provided with only one switching element including a plurality of parallel transistor chips.
[0011]
【The invention's effect】
As described above, when the chips of the main switching element are connected in parallel on the insulating substrate, the heat sharing is important for improving the reliability of power devices that are increasing in capacity and size by arranging them in a staggered manner. Or reduction.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a power semiconductor module product having six insulating substrates according to the present invention, where (a) is a plan view and (b) is a side sectional view. FIG. 2 is a perspective view of a simplified model of the present invention. 3 is a state diagram of the analysis result of the simple model of FIG. 2. FIG. 4 is a plan view for analysis of the present invention. FIG. 5 is a temperature distribution diagram by thermal analysis of the configuration of FIG. [Fig.7] Temperature distribution diagram of simulation results assuming that 450A / 1,200V rated package is operated at fc = 1kHz, 100% load [Fig.8] Cross-sectional view of conventional IGBT module [Explanation of symbols]
1 chip 1a IGBT chip 1b diode chip 2 insulating substrate 2a copper pattern 3 Cu base 4 cooling body 5 main terminal 6 control terminal 7 connection body

Claims (6)

A semiconductor device comprising a plurality of transistor chips connected in parallel on an insulating substrate to form one switching element, wherein the transistor chips are arranged in a staggered manner on the insulating substrate. 2. The semiconductor device according to claim 1, wherein a plurality of the switching elements are formed to be switching elements of each arm of the inverter circuit. 3. The semiconductor device according to claim 2, wherein a diode chip is connected in parallel to the transistor chip. 3. The semiconductor device according to claim 2, wherein a connection body for reducing resistance is interposed at a connection portion of the emitter of the transistor chip on the insulating substrate. 5. The semiconductor device according to claim 4, wherein the junction between the emitter of the transistor chip and the connection body is a bonding wire. 3. The semiconductor device according to claim 2, wherein the semiconductor device has a rating of 300 A / 1200 V or 450 A / 1200 V.

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