JP7661827B2 - DAB bidirectional isolated DC/DC converter and control method thereof - Google Patents

Description

The present invention relates to voltage balance control in a series connection of bidirectional isolated DC/DC converters using a dual active bridge (DAB) system, in which DC power is converted to AC power by an inverter, isolated using a transformer, and converted back to DC by another inverter.

Non-patent document 1 and patent documents 1 to 3 are methods for controlling the balance of capacitor voltages using an auxiliary converter. By using an auxiliary converter, it is possible to keep the deviation of the capacitor voltage very small under any conditions.

Non-Patent Document 1 and Patent Document 1 use a DAB converter as the auxiliary converter, Patent Document 2 uses a chopper, and Patent Document 3 uses a resonant circuit and a voltage doubler rectifier circuit. The auxiliary converter in Patent Document 3 is composed only of passive elements, so the capacitor voltage can be balanced without using a separate control means.

Patent document 4 shows a configuration in which a bridge cell is connected to one end of a DAB unit, and the cascade connection of the bridge cells is connected to a power supply. In the cascade connection of the bridge cells, a method for controlling the balance of the capacitor voltage has been established, and the power supply can also be used with AC. When the power supply is DC only, the number of semiconductor elements can be reduced by replacing the bridge cell with a chopper cell. A switch is connected to the other end of the DAB unit, and the number of DAB units in parallel can be freely switched according to the number and capacity of the load.

International Publication WO2017/163508 JP 2017-017868 A JP 2017-017869 A JP 2019-213424 A

Takuji Ishibashi, Hiroshi Jido, Osamu Mori, "Circuit configuration and control method of high-voltage large-capacity DC/DC converter for DC transmission and distribution system of large-scale offshore wind power generation", Transactions on Electrical Engineering of Japan, Vol. 138, No. 1, 2018, pp. 58-66

However, in the configurations of Non-Patent Document 1 and Patent Documents 1 to 3, the number of parts, cost, and device volume increase by the amount of the added auxiliary converter. In Patent Document 1, M-1 auxiliary converters are required for an M series configuration.

In Non-Patent Document 1, two auxiliary converters are required for a configuration of three inputs in series and three in parallel and nine outputs in series. In addition, the capacity design of the auxiliary converters is also an issue.

For example, Non-Patent Document 1 describes a design example that takes into account the variation in semiconductor losses and the variation in reactors. However, it cannot deal with other issues, such as an increase in leakage current due to aging of DC capacitors, making it impossible to maintain balance. Designing the capacity with a margin increases the cost and device volume. Furthermore, the configurations in Non-Patent Document 1 and Patent Documents 1 and 2 require a separate control means for the auxiliary circuit, which increases the cost by the amount of the detector and control board.

The configuration of Patent Document 3 does not require a control means. However, designing the regulated voltage is difficult. If the regulated voltage is excessive, even if the capacitor voltages are balanced, current continues to circulate through the upper and lower DAB units via the auxiliary converter, increasing losses. If the regulated voltage is insufficient, the balance of the capacitor voltages is significantly disrupted before current begins to flow through the auxiliary converter, causing the deviation in the capacitor voltages to increase.

In Patent Document 4, the number of parts, cost, and device volume increase by the number of bridge cells and chopper cells connected to one end. In addition, a switching device is required at the other end, which also increases the number of parts, cost, and device volume. In particular, the switching device requires M x M switches for M units and M loads, significantly increasing the number of parts. If the switches are made of mechanical contacts, their lifespan becomes an issue, and circuit breakers compatible with direct current are large and expensive. If semiconductor switches are used, increased losses due to voltage drop become an issue.

Since the input and output sides of a DAB converter are insulated, multiple units can be connected in series and parallel. In addition to converting and isolating high-current DC power by connecting them in parallel, two-way conversion from high-voltage power to low-voltage, high-current power can also be performed by connecting one end in series. Furthermore, if one DAB unit is designed and mass-produced, multiple units can be connected in series and parallel to handle high-voltage, high-power conversion.

The problem in this case is the capacitor voltage balance at one end of the series connection. If the voltage balance is lost, the voltage burden will be concentrated on a specific DAB unit, causing problems such as unit overheating, element destruction due to switching surges, and component destruction due to overvoltage. If the other end is connected in parallel, the charge of the DC capacitor can be transferred to another unit via the parallel side, and the series capacitor voltage balance can be maintained.

However, when both ends are connected in series, charge movement is limited to within the same unit, making it difficult to maintain balance.

As described above, the challenge in a DAB bidirectional isolated DC/DC converter with both ends connected in series is to achieve equal capacitor voltage balance.

The present invention has been devised in view of the above-mentioned problems in the related art, and one aspect thereof is a DAB-type bidirectional isolated DC/DC converter including a primary side DC power supply, a secondary side DC power supply, and a first unit to an m-th unit (m: an integer of 2 or more) connected between the primary side DC power supply and the secondary side DC power supply, the first unit to the m-th unit being connected in series between the positive and negative poles of the primary side DC power supply, the secondary side DC capacitors of the first unit to the m-th unit being connected in series between the positive and negative poles of the secondary side DC power supply, and the first inverters of the first unit to the m-th unit being connected to the primary side DC capacitors of the first unit to the m-th unit, respectively. the first to m units, second inverters connected to the secondary DC capacitors of the first to m units, transformers of the first to m units, each of which has a primary winding connected to the AC side of the first inverter of the first to m units and a secondary winding connected to the AC side of the second inverter of the first to m units, and a control unit that generates gate signals for the first and second inverters, wherein the control unit controls the phase difference between the AC voltages output by the first inverter and the second inverter of each unit so that the DC capacitor voltages on the upstream side of the power transmission of each unit are equal.

In one embodiment, the control unit includes a first subtractor that subtracts a primary DC capacitor voltage average value from the sum of the primary DC capacitor voltage of the kth unit (k = an integer from 1 to m) and the unbalance voltage command value of the kth unit to calculate a primary voltage deviation of the kth unit, a second subtractor that subtracts a secondary DC capacitor voltage average value from the sum of the secondary DC capacitor voltage of the kth unit and the unbalance voltage command value of the kth unit to calculate a secondary voltage deviation of the kth unit, and a third subtractor that multiplies the secondary voltage deviation by -1/n when the turns ratio of the transformer is primary winding:secondary winding = 1:n, or multiplies the secondary voltage deviation by -1 and calculates the 1:n voltage deviation. The k-th unit is equipped with a turns ratio multiplier that multiplies the secondary voltage deviation by n, a first amplifier that amplifies the primary voltage deviation when the power command value is greater than a first threshold, amplifies the secondary voltage deviation when the power command value is less than a second threshold, and amplifies either the primary voltage deviation or the secondary voltage deviation, or the sum of both, when the power command value is greater than or equal to the second threshold and less than the first threshold, or outputs 0 as the phase of the k-th unit, and a second adder that adds a phase command value to the phase of the k-th unit and outputs the result as a phase difference command value, and controls the first inverter and the second inverter of the k-th unit based on the phase difference command value.

In one aspect, the unbalance voltage command value for the kth unit is set to 0.

In another aspect, the control unit controls the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit (k=an integer from 1 to m) so that the DC capacitor voltage upstream of the power transmission of the kth unit is reduced when the total energy value stored in the primary DC capacitor and the secondary DC capacitor of the kth unit is larger than that of the other units, and controls the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit so that the DC capacitor voltage upstream of the power transmission of the kth unit is increased when the total energy value stored in the primary DC capacitor and the secondary DC capacitor of the kth unit is smaller than that of the other units.

In another aspect, the control unit controls the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit (k = an integer from 1 to m) so that the DC capacitor voltage on the upstream side of the power transmission of the kth unit is smaller when the DC capacitor voltage on the downstream side of the power transmission of the kth unit is larger than that of the other units, and controls the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit so that the DC capacitor voltage on the upstream side of the power transmission of the kth unit is larger when the DC capacitor voltage on the downstream side of the power transmission of the kth unit is smaller than that of the other units.

In another aspect, the control unit is characterized by including a seventh subtractor that calculates a first energy deviation between the total energy value stored in the primary side DC capacitor and the secondary side DC capacitor of the kth unit and the average value of all units of the total energy values stored in the primary side DC capacitor and the secondary side DC capacitor, and a second amplifier that amplifies the first energy deviation and outputs it as the unbalanced voltage command value of the kth unit.

In another aspect, the control unit reduces the operating power factor of a unit other than the unit whose total energy stored in the primary side DC capacitor and the secondary side DC capacitor is the smallest among all units.

In another aspect, the control unit reduces the operating power factor of a unit other than the unit with the lowest DC capacitor voltage downstream of the power transmission.

In another aspect, the control unit includes a ninth subtractor that calculates a second energy deviation, which is the deviation between the total energy value stored in the primary side DC capacitor and the secondary side DC capacitor of the kth unit and the minimum total energy value stored in the primary side DC capacitor and the secondary side DC capacitor of all units, a third amplifier that amplifies the second energy deviation, a seventh adder that adds the output of the third amplifier to the smaller of the primary side pulse width command value of the kth unit and the secondary side pulse width command value of the kth unit, and a seventh adder that limits the output of the seventh adder to within an upper limit value and a lower limit value. a first limiter, a tenth subtractor that calculates a difference between an input value and an output value of the first limiter, an eleventh subtractor that subtracts a difference between an input value and an output value of the first limiter from the larger of the primary pulse width command value of the kth unit and the secondary pulse width command value of the kth unit, a second limiter that limits an output of the eleventh subtractor to within an upper limit value and a lower limit value, a fourth switch that outputs an output of the second limiter when the primary pulse width command value of the kth unit is larger than the secondary pulse width command value of the kth unit, and outputs an output of the first limiter otherwise, a fifth switch which outputs the output of the first limiter when a primary pulse width command value is greater than the secondary pulse width command value of the kth unit, and otherwise outputs the output of the second limiter; a first multiplier which multiplies a primary AC current detection value of the kth unit by 1/n or multiplies a secondary AC current detection value of the kth unit by n when a turn ratio of the transformer is primary winding:secondary winding=1:n; a third adder which adds an amplified value of a DC component of the primary AC current detection value of the kth unit to an output of the fourth switch, and outputs the result as a primary positive pulse width command value of the kth unit; a fifth subtractor that subtracts the amplified DC component of the primary side AC current detection value of the kth unit from the output of the fifth switch and outputs the result as a negative side pulse width command value for the primary side of the kth unit; a fourth adder that adds the amplified DC component of the secondary side AC current detection value of the kth unit to the output of the fifth switch and outputs the result as a positive side pulse width command value for the secondary side of the kth unit; and a sixth subtractor that subtracts the amplified DC component of the secondary side AC current detection value of the kth unit from the output of the fifth switch and outputs the result as a negative side pulse width command value for the secondary side of the kth unit.

In another aspect, the control unit is characterized in that it increases the DC component of the current output by a unit other than the unit whose total energy stored in the primary side DC capacitor and the secondary side DC capacitor is the smallest among all units.

In another aspect, the control unit is characterized in that it increases the DC component of the current output by a unit other than the unit with the lowest DC capacitor voltage downstream of the power transmission.

In another aspect, the present invention includes a ninth subtractor that calculates a second energy deviation, which is the deviation between the total energy value stored in the primary side DC capacitor and the secondary side DC capacitor of the kth unit and the minimum total energy value stored in the primary side DC capacitor and the secondary side DC capacitor of all units, a third amplifier that amplifies the second energy deviation, a seventh adder that adds the output of the third amplifier to the smaller of the primary side pulse width command value of the kth unit and the secondary side pulse width command value of the kth unit, a first limiter that limits the output of the seventh adder to within an upper limit value and a lower limit value, and a second limiter that calculates the difference between the input value and the output value of the first limiter. a tenth subtractor for subtracting a difference between an input value and an output value of the first limiter from the larger of the primary side pulse width command value of the kth unit and the secondary side pulse width command value of the kth unit; a second limiter for limiting an output of the eleventh subtractor to within an upper limit value and a lower limit value; a twelfth subtractor for calculating a difference between an input value and an output value of the second limiter; a fourth switch for outputting an output of the second limiter when the primary side pulse width command value of the kth unit is larger than the secondary side pulse width command value of the kth unit, and for outputting an output of the first limiter otherwise; a fifth switch which outputs the output of the first limiter if the kth unit is greater than a pulse width command value, and otherwise outputs the output of the second limiter; a first multiplier which multiplies the primary side AC current detection value of the kth unit by 1/n or multiplies the secondary side AC current detection value of the kth unit by n when the turns ratio of the transformer is primary winding:secondary winding=1:n; a third subtractor which subtracts a DC component of the primary side AC current detection value of the kth unit from a difference between an input value and an output value of the second limiter; a fourth subtractor which subtracts a DC component of the secondary side AC current detection value of the kth unit from a value obtained by inverting the sign of the difference between the input value and the output value of the second limiter; The kth unit is characterized by having a third adder that adds the amplified value of the output of the third subtractor to the kth unit and outputs the result as a positive side pulse width command value on the primary side of the kth unit, a fifth subtractor that subtracts the amplified value of the output of the third subtractor from the output of the fourth switch and outputs the result as a negative side pulse width command value on the primary side of the kth unit, a fourth adder that adds the amplified value of the output of the fourth subtractor to the output of the fifth switch and outputs the result as a positive side pulse width command value on the secondary side of the kth unit, and a sixth subtractor that subtracts the amplified value of the output of the fourth subtractor from the output of the fifth switch and outputs the result as a negative side pulse width command value on the secondary side of the kth unit.

According to the present invention, it is possible to equalize the capacitor voltage balance in a DAB type bidirectional isolated DC/DC converter with both ends connected in series.

FIG. 2 is a diagram showing a main circuit configuration of a DAB bidirectional isolated DC/DC converter according to the first to fourth embodiments. FIG. 11 is a block diagram showing a phase difference command value calculation unit according to the first to fourth embodiments. FIG. 4 is a block diagram showing a pulse width command value calculation unit according to the first and second embodiments. FIG. 1 is a block diagram showing a gate signal generating unit according to first to fourth embodiments. 13 is a diagram showing an example of a primary AC voltage V1k of the kth unit, a secondary AC voltage V2k of the kth unit, and gate signals T2k1, T2k2, T2k3, and T2k4. FIG. 11 is a diagram showing the influence of a primary side DC capacitor voltage when power is transmitted from the primary side to the secondary side. 13 is a diagram showing the influence of a primary side DC capacitor voltage when power is transmitted from the secondary side to the primary side. FIG. 11 is a block diagram showing an unbalance voltage command value calculation unit according to a second embodiment. FIG. 11 is a block diagram showing a pulse width command value calculation unit according to a third embodiment. FIG. 13 is a block diagram showing a pulse width command value calculation unit according to a fourth embodiment.

Below, the first to fourth embodiments of the DAB bidirectional isolated DC/DC converter of the present invention will be described in detail with reference to Figs. 1 to 10.

[Embodiment 1]
The present invention is premised on being applied to the circuit shown in Fig. 1. The left side is the primary side, and the right side is the secondary side, with m DAB units connected in series on both sides. The first to m-th units are connected between the primary side DC power supply DC1 and the secondary side DC power supply DC2.

The primary side DC capacitors C1 of the first to mth units are connected in series between both ends of the primary side DC power supply DC1. The first and second switching elements S1 and S2 are connected in series between both ends of the primary side DC capacitor C1 of each unit. In addition, the third and fourth switching elements S3 and S4 are connected in series between both ends of the primary side DC capacitor C1 of each unit. The first to fourth switching elements S1 to S4 form a first inverter.

The secondary DC capacitors C2 of the first to mth units are connected in series between both ends of the secondary DC power supply DC2. The fifth and sixth switching elements S5 and S6 are connected in series between both ends of the secondary DC capacitor C2 of each unit. In addition, the seventh and eighth switching elements S7 and S8 are connected in series between both ends of the secondary DC capacitor C2 of each unit. The fifth to eighth switching elements S5 to S8 form a second inverter.

In FIG. 1, capacitors are connected in parallel to the first to eighth switching elements, but these capacitors can be omitted.

One end of reactor L1 is connected to the connection point of the first and second switching elements S1 and S2. One end of reactor L2 is connected to the connection point of the third and fourth switching elements S3 and S4. One end of reactor L3 is connected to the connection point of the fifth and sixth switching elements S5 and S6. One end of reactor L4 is connected to the connection point of the seventh and eighth switching elements S7 and S8.

The primary winding of the transformer Tr is connected between the other end of the reactor L1 and the other end of the reactor L2. The secondary winding of the transformer Tr is connected between the other end of the reactor L3 and the other end of the reactor L4. The first inverter, the second inverter, and the transformer Tr form one unit. In this embodiment 1, the system is provided with first to mth units (m: an integer of 2 or more).

In FIG. 1, reactors L1 to L4 are connected in series between the first inverter, the second inverter and the transformer Tr, but the leakage inductance of the transformer Tr may be used instead of the reactors L1 to L4. Also, both the reactors L1 to L4 and the leakage inductance of the transformer Tr may be used.

The voltage of the primary DC power supply DC1 is Vdc1, the voltage of the secondary DC power supply DC2 is Vdc2, the primary DC capacitor voltages of the primary DC capacitor C1 of the 1st to mth units are Vdc11 to Vdc1m, the secondary DC capacitor voltages of the secondary DC capacitor C2 of the 1st to mth units are Vdc21 to Vdc2m, the primary AC voltage of the kth unit is V1k, the secondary AC voltage of the kth unit is V2k, the primary AC current of the kth unit is i1k, and the secondary AC current of the kth unit is i2k. Here, k is an integer from 1 to m.

Figures 2 to 4 show block diagrams of the control unit of the kth unit in the circuit configuration of Figure 1 in this embodiment 1. The control unit generates gate signals for the first and second inverters. Figure 2 is a block diagram of the phase difference command value (θk) calculation unit of the kth unit.

The first low-pass filter LPF1 removes ripples and noise with a frequency twice that of the fundamental wave from the primary side DC capacitor voltage Vdc1k of the kth unit.

The primary side DC capacitor voltage average value Vdc1avg is either the sum of the primary side DC capacitor voltages Vdc11 to Vdc1m or the primary side DC voltage Vdc1 divided by the number of units m.

The first subtractor 1 subtracts the primary DC capacitor voltage average value Vdc1avg from the sum of the primary DC capacitor voltage Vdc1k of the kth unit to which the first low-pass filter LPF1 is applied and the unbalanced voltage command value Vdck* of the kth unit to obtain the primary voltage deviation of the kth unit. In this embodiment 1, Vdck* = 0.

The second low-pass filter LPF2 removes ripples and noise with a frequency twice that of the fundamental wave from the secondary DC capacitor voltage Vdc2k of the kth unit. The secondary DC capacitor voltage average value Vdc2avg is the sum of the secondary DC capacitor voltages Vdc21 to Vdc2m or the secondary DC voltage Vdc2 divided by the number of units m.

The second subtractor 2 subtracts the secondary DC capacitor voltage average value Vdc2avg from the sum of the secondary DC capacitor voltage Vdc2k of the kth unit to which the second low-pass filter LPF2 is applied and the unbalance voltage command value Vdck* of the kth unit to obtain the secondary voltage deviation of the kth unit.

P* in Figure 2 is the power command value transmitted between the primary side and the secondary side. If the power command value P* is positive, power is transmitted from the primary side to the secondary side, and if it is negative, power is transmitted from the secondary side to the primary side. The power command value P* may be given from the outside, or it may be obtained by voltage control or current control of either the primary side DC voltage Vdc1 or the secondary side DC voltage Vdc2.

The first comparator 3 determines whether the power command value P* is positive or not. The turns ratio calculator 4 multiplies the output of the second subtractor 2 (secondary voltage deviation) by a value obtained by multiplying the inverse of the turns ratio of the transformer Tr by -1. The turns ratio calculator 4 may also multiply the output of the second subtractor 2 (secondary voltage deviation) by -1, and multiply the output of the first subtractor 1 (primary voltage deviation) by the turns ratio n of the transformer Tr. Here, the turns ratio of the transformer Tr is primary side:secondary side = 1:n.

The first switch SW1 outputs the primary voltage deviation of the kth unit if the power command value P* is positive, and outputs the output of the turns ratio calculator 4 if the power command value P* is zero or negative.

To prevent frequent switching of the first switch SW1, if the power command value P* is near zero, the previous switch state may be maintained to provide a hysteresis characteristic. Also, if the power command value P* is zero, the average value of the primary voltage deviation of the kth unit and the secondary voltage deviation of the kth unit may be output.

The first amplifier 5 amplifies the output of the first switch SW1 and outputs the phase θkb of the kth unit. In this example, the following two are used in combination.

The proportional amplifier P1 outputs a value proportional to the output of the first switch SW1. The first-order lag filter 5a with gain amplifies the low-frequency components of the output of the first switch SW1.

The first adder 6 adds the above two amplifier outputs and outputs the phase θkb. The second adder 7 adds a separately provided phase command value θ* to the phase θkb and outputs the phase difference command value θk for the kth unit.

The phase command value θ* may be given by feedback control of the DC side current or voltage. It may also be calculated from the power command value P*, the primary side DC capacitor voltage Vdc1k of the kth unit, and the secondary side DC capacitor voltage Vdc2k of the kth unit.

Here, when the phase θkb, phase command value θ*, and phase difference command value θk of the kth unit are positive, the phase of the primary side AC voltage V1k of the kth unit leads with respect to the secondary side AC voltage V2k of the kth unit, and power is transmitted from the primary side to the secondary side. Figure 3 shows a block diagram of the pulse width command value (W1kp, W1km, W2kp, W2km) calculation unit.

The third low-pass filter LPF3 extracts the DC component of the primary side AC current detection value i1k of the kth unit.

The first multiplier 8 multiplies the secondary side AC current detection value i2k of the kth unit by the turns ratio n. The fourth low-pass filter LPF4 extracts the DC component from the output (n x i2k) of the first multiplier 8.

In FIG. 3, the secondary AC current detection value i2k of the kth unit is multiplied by the turns ratio n of the transformer Tr, but the primary AC current detection value i1k of the kth unit may be multiplied by the inverse of the turns ratio n (1/n). Here, the turns ratio of the transformer Tr is primary side:secondary side=1:n.

The third subtractor 9 subtracts the output of the third low-pass filter LPF3 from the DC component command value to obtain the deviation. The fourth subtractor 10 subtracts the output of the fourth low-pass filter LPF4 from the DC component command value to obtain the deviation. In embodiments 1, 2, and 3, the DC component command value is zero.

The PI amplifier 11 amplifies the deviation calculated by the third subtractor 9. The PI amplifier 12 amplifies the deviation calculated by the fourth subtractor 10.

The third adder 13 adds the output of the PI amplifier 11, which receives the primary side pulse width command value W1k of the kth unit and the primary side AC current detection value i1k of the kth unit as input, and outputs the positive side pulse width command value W1kp of the primary side of the kth unit.

The fifth subtractor 14 subtracts the output of the PI amplifier 11, which receives the primary AC current detection value i1k of the kth unit as input, from the primary pulse width command value W1k of the kth unit, and outputs the negative pulse width command value W1km of the primary side of the kth unit.

The fourth adder 15 adds the output of the PI amplifier 12, which receives the kth unit's secondary side pulse width command value W2k and the kth unit's secondary side AC current detection value i2k as input, and outputs the kth unit's secondary side positive side pulse width command value W2kp.

The sixth subtractor 16 subtracts the output of the PI amplifier 12, which receives the secondary AC current detection value i2k of the kth unit as input, from the secondary pulse width command value W2k of the kth unit, and outputs the negative side pulse width command value W2km of the secondary side of the kth unit.

Figure 4 shows a block diagram of the gate signal generation section.

The second multiplier 17 multiplies the phase difference command value θk of the kth unit by 0.5. The third multiplier 18 multiplies the output of the second multiplier 17 (0.5θk) by -1 and inverts the sign.

The gate generator 19 inputs the output (0.5θk) of the second multiplier 17, the positive side pulse width command value W1kp of the primary side of the kth unit, and the negative side pulse width command value W1km of the primary side of the kth unit, adds dead time, and outputs gate signals T1k1, T1k2, T1k3, and T1k4. The gate signal T1k1 controls the first switching element S1, the gate signal T1k2 controls the second switching element S2, the gate signal T1k3 controls the third switching element S3, and the gate signal T1k4 controls the fourth switching element S4.

The gate generator 20 inputs the output (-0.5θk) of the third multiplier 18, the positive side pulse width command value W2kp of the secondary side of the kth unit, and the negative side pulse width command value W2km of the secondary side of the kth unit, adds dead time, and outputs gate signals T2k1, T2k2, T2k3, and T2k4. The gate signal T2k1 controls the fifth switching element S5, the gate signal T2k2 controls the sixth switching element S6, the gate signal T2k3 controls the seventh switching element S7, and the gate signal T2k4 controls the eighth switching element S8.

Figure 5 shows an example of the primary AC voltage V1k of the kth unit, the secondary AC voltage V2k of the kth unit, and the gate signals T2k1, T2k2, T2k3, and T2k4. In this example, the phase difference command value θk of the kth unit is positive, the phase of the primary AC voltage V1k of the kth unit leads the phase of the secondary AC voltage V2k of the kth unit, and power is transmitted from the primary side to the secondary side.

In this embodiment 1, we will show how to control the balance of the capacitor voltage under conditions where a certain amount of power is being transmitted. The balance control policy will be explained using Figures 6 and 7.

Figure 6 shows only the primary side extracted from Figure 1. Power is transmitted from the primary side to the secondary side, and the transmitted power of each unit is equal. Consider the case where the primary side DC capacitor voltage Vdc1k of the kth unit is in excess of the primary side DC capacitor voltage average value Vdc1avg, and the primary side DC capacitor voltage Vdc1m of the mth unit is insufficient compared to the primary side DC capacitor voltage average value Vdc1avg.

Since the DAB units are connected in series, the DC current flowing through each unit is constant. The primary side DC capacitor voltage Vdc1k of the kth unit is greater than the primary side DC capacitor voltages of the other units, so the power input to the kth unit also increases. However, since the power transmitted to the secondary side by the kth unit is equal to that of the other units, the input power becomes excessive and is charged to the primary side DC capacitor C1, causing the primary side DC capacitor voltage Vdc1k of the kth unit to increase further.

The primary DC capacitor voltage Vdc1m of the mth unit is smaller than the primary DC capacitor voltages of the other units, and the power input to the mth unit decreases. To transmit the same amount of power as the other units, the primary DC capacitor C1 of the mth unit must be discharged, and the primary DC capacitor voltage Vdc1m of the mth unit will decrease further.

As a result of the above, when power is transferred from the primary side to the secondary side, the voltage balance of the primary side DC capacitor C1 is unstable and requires control.

On the other hand, consider the case where power is transmitted from the secondary side to the primary side as shown in Figure 7. Figure 7 shows only the primary side extracted from Figure 1. The primary side DC capacitor voltage Vdc1k of the kth unit is larger than the primary side DC capacitor voltages of the other units, and the power output by the kth unit also increases. However, since the power that the kth unit receives from the secondary side is equal to that of the other units, the input power is insufficient compared to the output power, and this amount is made up by the discharge of the primary side DC capacitor C1 of the kth unit. As a result, the primary side DC capacitor voltage Vdc1k of the kth unit decreases.

The primary side DC capacitor voltage Vdc1m of the mth unit is smaller than the primary side DC capacitor voltages of the other units, and the power output by the mth unit also decreases. Since the power that the mth unit receives from the secondary side is equal to that of the other units, the power that the mth unit receives from the secondary side is excessive compared to the output, and the excess is charged to the primary side DC capacitor C1 of the mth unit, causing the primary side DC capacitor voltage Vdc1m of the mth unit to increase.

From the above, when power is transmitted from the secondary side to the primary side, the voltage balance of the primary side DC capacitor C1 is stable, and although a certain degree of deviation occurs, the balance is achieved spontaneously without the need for control. This balancing effect increases as the transmitted power increases, but if the transmitted power is small, it becomes more difficult to achieve balance and the deviation increases. If the transmitted power is zero, the balancing effect disappears and the system becomes unstable.

In the first embodiment, when the power command value P* is positive and power is transmitted from the primary side to the secondary side, the primary side DC capacitor voltage is balanced. As shown in FIG. 2, when the power command value P* is positive, the first switch SW1 switches to the upper side, and the deviation between the primary side DC capacitor voltage Vdc1k of the kth unit and the primary side DC capacitor voltage average value Vdc1avg is input to the first amplifier 5.

If the primary side DC capacitor voltage Vdc1k of the kth unit is excessive, the deviation is positive, and the phase θkb amplified by the first amplifier 5 is also positive. As a result, the phase of the primary side AC voltage V1k of the kth unit leads the secondary side AC voltage V2k of the kth unit, and the phase difference is larger than in the other units. In the kth unit, more power is transmitted from the primary side to the secondary side than in the other units, and the primary side DC capacitor voltage Vdc1k of the kth unit decreases, reducing the deviation.

If the primary side DC capacitor voltage Vdc1k of the kth unit is insufficient, the deviation will be negative. The power that the kth unit transmits from the primary side to the secondary side will be smaller than that of the other units, and the primary side DC capacitor voltage Vdc1k of the kth unit will increase.

The above operation balances the primary side capacitor voltage. On the other hand, the charge required to balance the primary side capacitor voltage is supplied from the secondary side capacitor, so the secondary side capacitor voltage balance deteriorates.

However, as mentioned above, the secondary capacitor voltage balance is stable. Therefore, although some deviation occurs, the secondary capacitor voltage converges to a point where the power transmitted from the unit and the power output are balanced.

When the power command value P* is zero or negative and power is transmitted from the secondary side to the primary side, the secondary side capacitor voltage is balanced. When the power command value P* is negative, the first switch SW1 switches to the lower side, and the deviation between the secondary side DC capacitor voltage Vdc2k of the kth unit and the secondary side DC capacitor voltage average value Vdc2avg is input to the first amplifier 5.

If the secondary DC capacitor voltage Vdc2k of the kth unit is excessive, the deviation becomes negative and the phase θkb amplified by the first amplifier 5 also becomes negative. The phase of the primary AC voltage V1k of the kth unit lags behind the secondary AC voltage V2k of the kth unit, and the phase difference becomes larger than in the other units. In the kth unit, more power is transmitted from the secondary side to the primary side than in the other units, and the secondary DC capacitor voltage Vdc2k of the kth unit decreases.

If the secondary side DC capacitor voltage Vdc2k of the kth unit is insufficient, the deviation will be positive. The power that the kth unit transmits from the primary side to the secondary side will be smaller than that of the other units, and the secondary side DC capacitor voltage Vdc2k of the kth unit will increase.

The voltage balance of the primary side DC capacitor C1 is not controlled but becomes stable spontaneously.

The first amplifier 5 in Figure 2 does not use an integrator. The reason for this is explained below. An integrator has the characteristic that the DC gain is infinite, and the DC deviation is made zero, making the capacitor voltage, which is the object of control, equal to the command value.

However, in Figure 1, which is the control object in this case, the sum of the unit capacitor voltages (Vdc1 on the primary side) is determined by external factors such as the connected voltage source and a separately prepared constant DC current control. Therefore, once the voltage of m-1 unit capacitors is determined, the voltage of the remaining capacitor is inevitably determined. The controlled object has m-1 degrees of freedom, but if it is controlled by m controllers, the degrees of freedom will be insufficient and the control will become unstable.

In particular, if there is an error in the detector, the integrating amplifier of one unit will increase its output in an attempt to reduce the deviation, including the error, to zero, which will increase the deviation of another unit, causing the integrating amplifier of that unit to increase its output, and so on, with the amplifier output increasing without limit.

As a countermeasure, the DC gain is limited and control is performed using a proportional amplifier P1 and a first-order lag filter with gain 5a to allow for the slight remaining deviation. As another countermeasure, balance control can be performed in m-1 units by replacing the amplifiers in Figure 2 with PI amplifiers, and the remaining units (for example, the first unit) can fix the phase θ1b at zero without performing the balance control in Figure 2.

In FIG. 2, when the power command value P* is zero, the secondary DC capacitor voltage is balanced, but the primary DC capacitor voltage may also be balanced. When the power command value P* is close to zero and the sign changes frequently, such as in a no-load standby state, the first switch SW1 may be given a hysteresis characteristic in switching to prevent frequent sudden changes in the phase θkb.

In this embodiment 1, the phase difference between the AC voltages output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages upstream of the power transmission of each unit are equal.

The average value of the primary side voltage deviation and the secondary side voltage deviation may be input to the first amplifier 5 for control. That is, the first amplifier 5 amplifies the primary side voltage deviation when the power command value P* is greater than the first threshold, amplifies the secondary side voltage deviation when the power command value P* is less than the second threshold, and amplifies either the primary side voltage deviation or the secondary side voltage deviation, or the sum of both (average values) when the power command value P* is greater than or equal to the second threshold and less than the first threshold, or outputs 0 as the phase θkb of the kth unit.

However, this embodiment 1 alone cannot balance the capacitor voltages when the power command value P* = 0. To address this issue, it is necessary to combine it with the embodiment 3 described below.

In this embodiment 1, if the absolute value of the transmitted power is sufficiently large, the balance deviation of the capacitor voltage on the non-controlled side can be kept sufficiently small. However, there is a problem in that the deviation becomes large when the load becomes lighter and the absolute value of the transmitted power becomes smaller.

As described above, according to this embodiment 1, it is possible to maintain a balance between the DC capacitor voltages on both the primary and secondary sides when the transmission power is relatively large.

It also prevents the concentration of voltage load on a specific unit, preventing overheating and damage to components due to overvoltage, and damage to switching elements due to surges.

In addition, there is no need to increase the voltage resistance of the components, which reduces costs. Also, compared to conventional technology, there is no need for auxiliary circuits, which not only reduces costs but also allows the device to be made more compact.

[Embodiment 2]
FIG. 8 shows a block diagram of an unbalance voltage command value (Vdck*) calculation unit of the kth unit in the second embodiment.

The fifth low-pass filter LPF5 extracts the DC component by removing ripples and noise with a frequency twice the fundamental wave of the primary DC capacitor voltage Vdc1k of the kth unit. The sixth low-pass filter LPF6 extracts the DC component of the secondary DC capacitor voltage Vdc2k of the kth unit.

The fourth multiplier 21 calculates the square of the primary side DC capacitor voltage Vdc1k of the kth unit to which the fifth low-pass filter LPF5 is applied. The fifth multiplier 22 calculates the square of the secondary side DC capacitor voltage Vdc2k of the kth unit to which the sixth low-pass filter LPF6 is applied.

The sixth multiplier 23 multiplies the output of the fourth multiplier 21 by the value obtained by dividing the primary side capacitor capacitance C1 by 2. The seventh multiplier 24 multiplies the output of the fifth multiplier 22 by the value obtained by dividing the secondary side capacitor capacitance C2 by 2.

The fifth adder 25 adds the outputs of the sixth and seventh multipliers 23 and 24 to obtain the total energy value Ek stored in the primary side DC capacitor C1 and the secondary side DC capacitor C2 connected on both sides of the kth unit.

The seventh subtractor 26 calculates a first energy deviation, which is the deviation between the total energy value Ek and the average value Eavg of the total energy values stored in the primary side DC capacitor C1 and the secondary side DC capacitor C2 of all units.

The second amplifier 27 amplifies the output of the seventh subtractor 26 by multiplying it by a gain G2. The gain G2 may be a fixed value, or as shown in FIG. 8, the gain adjuster 28 may change the value based on the power command value P*, such as decreasing the gain G2 when the power command value P* is near zero. The output of the second amplifier 27 becomes the unbalanced voltage command value Vdck*.

In this second embodiment, we explain a method to reduce the deviation during light loads, which is one of the problems with the first embodiment.

In this second embodiment, first, the total energy value Ek stored in the primary side DC capacitor C1 and the secondary side DC capacitor C2 of the kth unit is calculated. Next, the deviation between the average value Eavg of the total energy values of each unit calculated in the same manner and the total energy value Ek is calculated. This is amplified by a gain G2, and the obtained value is set as the unbalanced voltage command value Vdck* of the kth unit.

The operation of the second embodiment will be described. As an example, the primary side DC capacitor voltage is the object of control when P*>0. At this time, Vdc11 to Vdc1m have approximately equal values due to the control of the first embodiment, so the stored energy of the primary side DC capacitors is approximately equal.

The total energy value Ek reflects the magnitude of the secondary DC capacitor voltage Vdc2k of the kth unit. If the secondary DC capacitor voltage Vdc2k of the kth unit is greater than the secondary DC capacitor voltage average value Vdc2avg, the total energy value Ek also becomes greater than the average energy total value Eavg, and the unbalance voltage command value Vdck* becomes positive.

This unbalanced voltage command value Vdck* is input to the first and second subtractors 1 and 2 in FIG. 2. The first subtractor 1 subtracts the primary DC capacitor voltage average value Vdc1avg from the sum of the primary DC capacitor voltage Vdc1k of the kth unit to which the first low-pass filter LPF1 is applied and the unbalanced voltage command value Vdck* of the kth unit to obtain the primary voltage deviation of the kth unit.

The second subtractor 2 subtracts the secondary DC capacitor voltage average value Vdc2avg from the sum of the secondary DC capacitor voltage Vdc2k of the kth unit to which the second low-pass filter LPF2 is applied and the unbalance voltage command value Vdck* of the kth unit to obtain the secondary voltage deviation of the kth unit.

As a result, the balance control command value (Vdc1avg-Vdck*) decreases and the primary DC capacitor voltage Vdc1k of the kth unit also decreases. Because the DC current flowing through each unit is constant, the power that the kth unit receives from the primary DC voltage Vdc1 decreases. Because the primary DC capacitor voltage Vdc1k of the kth unit is the object of control, the decrease in the received power is reflected in the magnitude of the secondary DC capacitor voltage Vdc2k of the kth unit, and the secondary DC capacitor voltage Vdc2k of the kth unit decreases and can approach the secondary DC capacitor voltage average value Vdc2avg.

When P*<0 and the secondary capacitor voltage is the control target of embodiment 1, the magnitude of the primary DC capacitor voltage Vdc1k of the kth unit is reflected in the total energy value Ek. If the primary DC capacitor voltage Vdc1k of the kth unit is smaller than the primary DC capacitor voltage average value Vdc1avg, the total energy value Ek will also be smaller than the average energy total value Eavg, and the unbalanced voltage command value Vdck* will be negative.

This unbalance voltage command value Vdck* is input to the first and second subtractors 1 and 2 in Figure 2, and the calculation is performed as described above. As a result, the balance control command value (Vdc2avg-Vdck*) increases, and the secondary DC capacitor voltage Vdc2k of the kth unit also increases. The power that the kth unit receives from the secondary DC voltage Vdc2 increases, and the primary DC capacitor voltage Vdc1k of the kth unit increases, making it possible to approach the primary DC capacitor voltage average value Vdc1avg.

In this second embodiment, a small amount of capacitor voltage balance deviation is intentionally generated on the primary side when P*>0 and on the secondary side when P*<0, i.e., on the upstream side of the power transmission. This makes it possible to improve the capacitor voltage balance deviation on the secondary side when P*>0 and on the primary side when P*<0, i.e., on the downstream side.

In this embodiment 2, when the total energy value Ek stored in the primary side DC capacitor and secondary side DC capacitor of the kth unit (k = an integer from 1 to m) is larger than that of the other units, the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit is controlled so that the DC capacitor voltage on the upstream side of the power transmission of the kth unit is reduced, and when the total energy value Ek stored in the primary side DC capacitor and secondary side DC capacitor of the kth unit is smaller than that of the other units, the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit is controlled so that the DC capacitor voltage on the upstream side of the power transmission of the kth unit is increased.

In this second embodiment, the input of the second amplifier 27 is not the downstream capacitor voltage of the power transmission, but the total energy stored in the primary side DC capacitor C1 and the secondary side DC capacitor C2 of the unit. The reason for this will be explained below. When P*>0, it is also possible to set the input of the second amplifier 27 to Vdc2k-Vdc2avg.

However, for example, if the secondary DC capacitor voltage Vdc2k of the kth unit is large, the power received by the secondary DC capacitor C2 of the kth unit can be reduced by reducing the primary DC capacitor voltage Vdc1k of the kth unit. However, to lower the primary DC capacitor voltage Vdc1k of the kth unit, the primary DC capacitor C1 of the kth unit must be discharged. The discharged charge moves to the secondary DC capacitor C2 of the kth unit via the DAB converter, causing the secondary DC capacitor voltage Vdc2k of the kth unit to increase further.

Then, the above-mentioned operation will attempt to further reduce the primary side DC capacitor voltage Vdc1k of the kth unit. This will make the control system more likely to become unstable, and it will be impossible to set a large value for the gain G2, resulting in a very small effect.

On the other hand, the total energy value Ek stored in the primary side DC capacitor C1 and the secondary side DC capacitor C2 is constant even when the charge is moved, unlike the capacitor voltage, so the control system is easy to stabilize and a high gain can be set, achieving sufficient effectiveness.

As described above, it is preferable to set the input of the second amplifier 27 to the total energy value Ek, but the input of the second amplifier 27 may be the downstream DC capacitor voltage. In this case, when the DC capacitor voltage downstream of the power transmission of the kth unit is larger than that of the other units, the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit is controlled so that the DC capacitor voltage upstream of the power transmission of the kth unit is reduced, and when the DC capacitor voltage downstream of the power transmission of the kth unit is smaller than that of the other units, the phase difference between the AC voltages output by the first inverter and the second inverter of the kth unit is controlled so that the DC capacitor voltage upstream of the power transmission of the kth unit is increased.

In this embodiment 2, the effect can be obtained if there is a load, but if there is no load, even if the capacitor voltage on the upstream side of the power transmission is changed, the received power is zero and no difference occurs, so no effect can be obtained. Therefore, when the power command value P* is near zero, the gain G2 can be set to zero to prevent unnecessary deviations from occurring.

By combining this embodiment 2 with embodiment 1, it is possible to keep the balance deviation of the capacitor voltage sufficiently small even when the absolute value of the transmitted power is small. However, there is a problem in that in the case of no load, the control means is lost and the deviation becomes large.

By combining embodiment 1 and embodiment 2, it is possible to maintain the voltage balance of the DC capacitors on both the primary and secondary sides even when the transmission power is small.

Compared to the first embodiment, the balance on the side where the balance was evenly achieved becomes slightly worse, but in the first embodiment, the voltage balance on the side where the deviation occurred can be improved.

This allows the withstand voltage of the components to be lower than in embodiment 1. Compared to the case where embodiment 3 is used alone or in combination with embodiment 1, it is possible to reduce losses under conditions where the transmission power is low.

[Embodiment 3]
9 shows a block diagram of a pulse width command value (W1kp, W1km, W2kp, W2km) calculation unit according to the third embodiment. FIG. 9 differs from FIG. 3 in the following respects.

In this embodiment 3, it is assumed that the primary pulse width command value W1k of the kth unit and the secondary pulse width command value W2k of the kth unit are calculated as follows:

The primary DC voltage Vdc1 is compared with the secondary DC voltage Vdc2/n taking into account the winding ratio, and the pulse width command value for the smaller voltage is set to a fixed value close to 1, for example, around 0.7 to 1. Alternatively, it may be set to a variable value with an upper limit of around 0.7 to 1 that is small when the power command value P* is close to zero and increases as the power command value P* moves away from zero.

The pulse width command value for the larger voltage is _W1 in the following equation (1). _W2 in equation (1) is the pulse width command value for the smaller voltage. θ in equation (1) is the deviation between the power command value P* and the product of the secondary DC voltage Vdc2 and the secondary DC current Idc2, with noise removed using a low-pass filter, amplified by a PI amplifier.

The eighth subtractor 29 subtracts the secondary pulse width command value W2k of the kth unit from the primary pulse width command value W1k of the kth unit. The second comparator 30 inputs the output of the eighth subtractor 29 and determines whether W1k>W2k. The second comparator 30 may have a hysteresis characteristic to avoid frequent switching of the switch described below.

The second switch SW2 inputs the primary pulse width command value W1k of the kth unit and the secondary pulse width command value W2k of the kth unit, and outputs W2k if W1k>W2k, or W1k if W1k≦W2k, i.e., the smaller of W1k and W2k. The third switch SW3 inputs the primary pulse width command value W1k of the kth unit and the secondary pulse width command value W2k of the kth unit, and outputs W1k if W1k>W2k, or W2k if W1k≦W2k, i.e., the larger of W1k and W2k.

The ninth subtractor 31 calculates a second energy deviation, which is the deviation between the total energy value Ek stored in the primary side DC capacitor and the secondary side DC capacitor of the kth unit and the minimum value Emin among all units among the total energy values stored in the primary side DC capacitor and the secondary side DC capacitor of each unit.

The third amplifier 32 that amplifies the second energy deviation uses the following two amplifiers in combination in this example. The proportional amplifier P2 outputs a value proportional to the second energy deviation calculated by the ninth subtractor 31. The first-order lag filter with gain 32a amplifies the low-frequency components of the second energy deviation calculated by the ninth subtractor 31. The sixth adder 33 adds the output of the proportional amplifier P2 and the output of the first-order lag filter with gain 32a.

The seventh adder 34 adds the output of the third amplifier 32 and the output of the second switch SW2. The first limiter 35 limits the output of the seventh adder 34. The upper limit of the first limiter 35 is usually 1, and the lower limit is a value greater than zero, such as 0.2. The upper limit may be a value slightly smaller than 1.

The tenth subtractor 36 finds the difference between the input and output of the first limiter 35, and outputs the value that exceeds the first limiter 35. The eleventh subtractor 37 subtracts the output of the tenth subtractor 36 from the output of the third switch SW3. The second limiter 38 limits the output of the eleventh subtractor 37. The upper and lower limits of the second limiter 38 are set in the same way as the first limiter 35.

The fourth switch SW4 inputs the outputs of both the first limiter 35 and the second limiter 38, and outputs the output of the second limiter 38 if W1k>W2k, and outputs the output of the first limiter 35 otherwise.

The value output by the fourth switch SW4 is the sum of the amplifier output and the primary pulse width command value W1k of the kth unit, regardless of the magnitude relationship between the primary pulse width command value W1k of the kth unit and the secondary pulse width command value W2k of the kth unit.

The fifth switch SW5 inputs the outputs of both the first limiter 35 and the second limiter 38, and outputs the output of the first limiter 35 if W1k>W2k, and outputs the output of the second limiter 38 otherwise.

The value output by the fifth switch SW5 is the value obtained by subtracting the amplifier output from the secondary pulse width command value W2k of the kth unit, regardless of the magnitude relationship between the primary pulse width command value W1k of the kth unit and the secondary pulse width command value W2k of the kth unit.

The third adder 13 adds the value obtained by amplifying the DC component of the primary side AC current detection value i1k of the kth unit by the PI amplifier 11 to the output of the fourth switch SW4, and outputs the result as the primary side positive side pulse width command value W1kp. The fifth subtractor 14 subtracts the value obtained by amplifying the DC component of the primary side AC current detection value i1k of the kth unit by the PI amplifier 11 from the output of the fourth switch SW4, and outputs the result as the primary side negative side pulse width command value W1km.

The fourth adder 15 adds the value obtained by amplifying the DC component of the secondary AC current detection value i2k of the kth unit by the PI amplifier 12 to the output of the fifth switch SW5, and outputs the result as the secondary side positive side pulse width command value W2kp. The sixth subtractor 16 subtracts the value obtained by amplifying the DC component of the secondary AC current detection value i2k of the kth unit by the PI amplifier 12 from the output of the fifth switch SW5, and outputs the result as the secondary side negative side pulse width command value W2km.

In this third embodiment, we will explain a method to reduce the balance deviation of the capacitor voltage when no load is applied, which was a problem in the first and second embodiments.

The operation of this embodiment 3 will be described. First, as in embodiment 2, the total energy value Ek stored in the primary side DC capacitor and secondary side DC capacitor of the kth unit is calculated and input. In addition, the minimum value Emin among all units is found from the total energy values stored in the primary side DC capacitor and secondary side DC capacitor of each unit, and a second energy deviation, which is the deviation from the total energy value Ek of the kth unit, is input to the third amplifier 32.

The pulse widths of the primary AC voltage V1k of the kth unit and the secondary AC voltage V2k of the kth unit are manipulated based on the output of the third amplifier 32. The manipulation is to first widen the narrower pulse width, and when the limiter is exceeded, narrow the wider pulse width.

The operation of this embodiment 3 will be explained using as an example a case where the secondary DC voltage Vdc2 is small, the secondary pulse width command value W2k = 0.7 to 1, the primary DC voltage Vdc1 is large, the primary pulse width command value W1k = (1), and the total DC capacitor stored energy value Ek of the kth unit is not minimum. In this case, the pulse width of the secondary inverter output voltage of the kth unit is set wide and the AC side operates at a power factor of 1. The pulse width of the primary inverter output voltage is set narrow and all reactive power supplied to the transformer and reactor is shared.

This reduces the primary side AC current detection value i1k and the secondary side AC current detection value i2k, thereby reducing copper loss and conduction loss. Here, by widening the pulse width of the primary side inverter output voltage of the kth unit, which has a narrow pulse width, the reactive power supplied to the AC side becomes excessive, and the secondary side inverter of the kth unit operates with a leading power factor.

The occurrence of unnecessary reactive power exchange increases the amplitude of the primary side AC current detection value i1k and the secondary side AC current detection value i2k, which in turn increases copper loss and conduction loss, facilitating the discharge of the capacitor voltage.

If the capacitor voltage is not sufficiently discharged even when the pulse width of the primary inverter output voltage of the kth unit is widened to 1, the pulse width of the secondary inverter output voltage of the kth unit is narrowed. This makes it possible to further increase the reactive power supplied to the AC side and further reduce the capacitor voltage.

For units with the smallest capacitor stored energy, the pulse width is not changed, and the operation is the same as when the secondary pulse width command value W2k = 0.7 to 1 and the primary pulse width command value W1k = (1), reducing losses and suppressing capacitor discharge. The above operation improves the balance of the capacitor voltage.

In this embodiment 3, for units other than those with the smallest total energy value Ek stored in the primary side DC capacitor and the secondary side DC capacitor, the smaller pulse width of the primary side pulse width command value W1k and the secondary side pulse width command value W2k is widened, or the larger pulse width is narrowed, or both are done, so that the reactive power output by the unit is increased (so that the operating power factor is reduced), and the primary side pulse width command value W1k and the secondary side pulse width command value W2k are corrected and output as the primary side positive side pulse width command value W1kp, the primary side negative side pulse width command value W1km, the secondary side positive side pulse width command value W2kp, and the secondary side negative side pulse width command value W2km.

In addition, in units other than the kth unit with the lowest DC capacitor voltage downstream of the power transmission, the smaller of the primary pulse width command value W1k and the secondary pulse width command value W2k may be widened or the larger pulse width may be narrowed, or both may be done, to correct the primary pulse width command value W1k and the secondary pulse width command value W2k so that the reactive power output by the unit is increased (so that the operating power factor is reduced), and the primary pulse width command value W1k and the secondary pulse width command value W2k may be output as the primary side positive pulse width command value W1kp, the primary side negative pulse width command value W1km, the secondary side positive pulse width command value W2kp, and the secondary side negative pulse width command value W2km.

In this third embodiment, the first and second limiters 35, 38 are set to the pulse width. The upper limits of the first and second limiters 35, 38 are usually 1, but may be set to approximately 0.7 to 0.95. If the lower limits of the first and second limiters 35, 38 are set to 0, no AC voltage is output, power transmission becomes impossible, and control becomes impossible. For this reason, they are set to a value greater than 0, for example, approximately 0.2.

In this embodiment 3, priority is given to widening the narrower pulse width, but priority may be given to narrowing the wider pulse width instead. Also, both may be manipulated equally.

The gains P2 and G2 of the third amplifier 32 in this embodiment 3 are constant. However, in the case of a load state according to the first and second embodiments, the capacitor voltages can be balanced without applying the third embodiment. Therefore, if the power command value P* is not 0, the gain may be switched to 0, and losses can be suppressed. The gain may be set to 0 under relatively large conditions, such as when the absolute value of the power command value P* is 0.1 or more, and even under light loads, intentionally generating losses can reduce the deviation in the capacitor voltage balance, although the efficiency will decrease slightly. The gain switching may have a hysteresis characteristic, and the gain may be changed based on the absolute value of the power command value P*.

In embodiment 3, losses are intentionally generated, so the thermal burden of the units naturally increases. However, embodiment 3 is applied assuming no load or light load, in which case copper loss, conduction loss, and switching loss are very small, with no-load losses such as iron loss accounting for the majority of the losses. The losses of the other units are simply adjusted to match the unit with the largest no-load loss, and the increase in loss is small.

For example, unless extreme increases in loss occur due to abnormalities such as a crack in the transformer Tr iron core increasing the magnetic flux density at the relevant location and increasing hysteresis loss, or the insulation of the laminated steel plate being damaged by impact and increasing eddy current loss, or deterioration over time increasing the leakage current of a capacitor, there is no need to enlarge the cooling mechanism.

According to this embodiment 3, even when the transmission power is zero, the voltage balance of the DC capacitors on both the primary and secondary sides can be maintained and operation can be continued. A converter with this configuration can also be used in applications where standby situations with no load occur frequently.

By using this in combination with embodiment 1 or 2, the loss increases under certain conditions of transmission power, but the deviation in the voltage balance of the DC capacitor can be reduced.

In addition, under conditions where the transmission power is relatively large, the control gain of this embodiment 3 can be reduced to disable this embodiment 3 and prevent a decrease in efficiency. Also, unlike the fourth embodiment described below, the ripple generated on the DC side is twice the fundamental frequency, so it can be removed with a small filter.

[Embodiment 4]
Fig. 10 shows a block diagram of a pulse width command value (W1kp, W1km, W2kp, W2km) calculation unit according to the fourth embodiment. Fig. 10 differs from Fig. 9 in the following respects.

In this fourth embodiment, a twelfth subtractor 39 is added. The twelfth subtractor 39 calculates the difference between the input and output of the second limiter 38, and outputs the value that exceeds the second limiter 38.

The output of the twelfth subtractor 39 is used as the DC component command value of the primary AC current of the kth unit by the third subtractor 9. The signal with the sign of the output of the twelfth subtractor 39 inverted is used as the DC component command value of the secondary AC current of the kth unit by the fourth subtractor 10.

The third subtractor 9 subtracts the output of the third low-pass filter LPF3 from the output of the twelfth subtractor 39. The fourth subtractor 10 subtracts the output of the fourth low-pass filter LPF4 from the value obtained by inverting the sign of the output of the twelfth subtractor 39.

In the third embodiment, the pulse width is changed to intentionally increase the loss and reduce the balance deviation of the capacitor voltage when no load is applied. However, there is a limit to the pulse width that can be changed, and it is not possible to deal with the case where a capacitor voltage balance disturbance that exceeds this limit occurs as described above.

This embodiment 4 describes a method for reducing the balance deviation of the capacitor voltage even when a larger balance disturbance occurs at no load.

In the third embodiment, an operation is performed to widen the narrower pulse width, but if the amount of operation exceeds the limiter, an operation is performed to narrow the wider pulse width, and if the limiter is exceeded here as well, no operation is performed for that amount.

In this embodiment 4, even when the wider pulse width is narrowed, the amount that exceeds the limiter is detected, and the excess amount is used as the command value for the DC component of the primary side AC current detection value i1k of the kth unit and the secondary side AC current detection value i2k of the kth unit.

By superimposing a DC component on the primary side AC current detection value i1k of the kth unit and the secondary side AC current detection value i2k of the kth unit, a larger loss can be generated and the capacitor can be discharged.

The DC component command value is set in the opposite direction for the primary AC current detection value i1k of the kth unit and the secondary AC current detection value i2k of the kth unit. In this embodiment 4, the first multiplier 8 multiplies the primary AC current detection value i1k by 1/n, or the secondary AC current detection value i2k by n. This allows the DC components of the magnetic flux generated by both the primary and secondary currents in the iron core inside the high-frequency transformer to cancel each other out, preventing magnetic saturation of the iron core.

In this embodiment 4, for units other than those in which the total energy value Ek stored in the primary side DC capacitor and the secondary side DC capacitor is the smallest among all units, the primary side pulse width command value W1k and the secondary side pulse width command value W2k are corrected so that the DC component of the current output by the unit becomes large, and are output as the primary side positive side pulse width command value W1kp, the primary side negative side pulse width command value W1km, the secondary side positive side pulse width command value W2kp, and the secondary side negative side pulse width command value W2km.

In addition, in units other than those with the smallest DC capacitor voltage downstream of power transmission, the primary pulse width command value W1k and the secondary pulse width command value W2k may be corrected so that the DC component of the current output by the unit is large, and output as the primary side positive pulse width command value W1kp, the primary side negative pulse width command value W1km, the secondary side positive pulse width command value W2kp, and the secondary side negative pulse width command value W2km.

In this embodiment 4, as a means of generating losses, increasing reactive power on the AC side is given high priority, while superimposing DC on AC current is given low priority. The reason for this is explained below. When reactive power is increased, ripples of twice the fundamental frequency are generated on the DC side. In the case of DC superimposition, ripples of a frequency equal to the fundamental frequency are generated. If the ripple frequency is low, problems arise such as the amplitude of the voltage ripple becoming larger even with the same capacitor capacity, and a large filter being required to remove it. For this reason, priority is given to the means that generate a high ripple frequency.

Examples of balance disturbances large enough to require the application of this embodiment 4 include abnormalities in the transformer or capacitor, discharge due to the intrusion of foreign matter into the unit, and insulation breakdown of the unit. Therefore, it is possible to integrate the DC component command values of the primary side AC current detection value i1k of the kth unit and the secondary side AC current detection value i2k of the kth unit, and periodically check the values during maintenance, etc. If there is a unit with a large integrated value, it is assumed that deterioration or an abnormality has occurred in the other units, and the unit with the smallest integrated value is replaced to prevent failure.

According to this embodiment 4, even if a large balance disturbance occurs when the transmission power is zero, the voltage balance of the DC capacitors on both the primary and secondary sides can be maintained and operation can be continued.

In addition, ripples with a frequency equal to the fundamental frequency occur on the DC side, but this can be minimized.

The present invention can also be applied to a configuration in which one end of multiple DAB converters are all connected in series, as shown in Non-Patent Document 1, and the other end is a combination of series and parallel connections. In this case, multiple DAB converters are considered to be connected in series, with one end of each connected in series and the other in parallel, and an existing control method is applied to the series capacitor voltage balance control inside the unit. The present invention is applied to the capacitor voltage balance control of each unit.

The present invention has been described in detail above only with respect to the specific examples described. However, it will be clear to those skilled in the art that various modifications and alterations are possible within the scope of the technical concept of the present invention, and it goes without saying that such modifications and alterations fall within the scope of the claims.

DC1, DC2...Primary side DC power supply, secondary side DC power supply C1, C2...Primary side DC capacitor, secondary side DC capacitor L1 to L4...Reactor Tr...Transformer LPF1 to LPF4...1st to 4th low pass filters 1, 2...1st and 2nd subtractors 3...1st comparator 4...Turns ratio calculator SW1 to SW5...1st to 5th switches 5...1st amplifier 6, 7...1st and 2nd adders

Claims (6)

A DAB bidirectional isolated DC/DC converter including a primary side DC power supply, a secondary side DC power supply, and first to m-th units (m: an integer of 2 or more) connected between the primary side DC power supply and the secondary side DC power supply,
primary side DC capacitors of the first unit to the mth unit connected in series between a positive electrode and a negative electrode of the primary side DC power supply;
secondary-side DC capacitors of the first unit to the mth unit connected in series between a positive electrode and a negative electrode of the secondary-side DC power supply;
First inverters of the first unit to the m unit connected to the primary side DC capacitors of the first unit to the m unit, respectively;
second inverters of the first unit to the m unit connected to the secondary side DC capacitors of the first unit to the m unit, respectively;
Transformers of the first unit to the m unit, each having a primary winding connected to an AC side of the first inverter of the first unit to the m unit, and a secondary winding connected to an AC side of the second inverter of the first unit to the m unit,
a control unit that generates gate signals for the first and second inverters;
Equipped with
The control unit is
a first subtractor that subtracts a primary side DC capacitor voltage average value from a sum of a primary side DC capacitor voltage of the kth unit (k=an integer from 1 to m) and an unbalance voltage command value of the kth unit to calculate a primary side voltage deviation of the kth unit;
a second subtractor that subtracts a secondary DC capacitor voltage average value from a sum of the secondary DC capacitor voltage of the kth unit and the unbalance voltage command value of the kth unit to calculate a secondary voltage deviation of the kth unit;
a turns ratio multiplier that multiplies the secondary voltage deviation by -1/n, or multiplies the secondary voltage deviation by -1 and multiplies the primary voltage deviation by n, when a turns ratio of the transformer is primary winding:secondary winding=1:n;
a first amplifier that amplifies the primary voltage deviation when a power command value is greater than a first threshold, amplifies the secondary voltage deviation when the power command value is less than a second threshold, and amplifies either the primary voltage deviation or the secondary voltage deviation, or a sum of both, when the power command value is equal to or greater than the second threshold and less than the first threshold, or outputs 0 as a phase of the kth unit;
a second adder that adds a phase command value to the phase of the kth unit and outputs the result as a phase difference command value;
and controlling the first inverter and the second inverter of the kth unit based on the phase difference command value;
A DAB-type bidirectional isolated DC/DC converter, characterized in that the phase difference between the AC voltages output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages upstream of the power transmission of each unit are equal. 2. The DAB bidirectional isolated DC/DC converter according to claim 1 , wherein the unbalanced voltage command value of the kth unit is set to 0. The control unit is
a seventh subtractor that calculates a first energy deviation between a total value of energy stored in the primary side DC capacitor and the secondary side DC capacitor of a kth unit and an average value of the total values of energy stored in the primary side DC capacitor and the secondary side DC capacitor of all units;
a second amplifier that amplifies the first energy deviation and outputs the amplified energy deviation as the unbalanced voltage command value of the kth unit;
2. The DAB bidirectional isolated DC/DC converter according to claim 1, further comprising: The control unit is
a ninth subtractor that calculates a second energy deviation, which is a deviation between a total value of energy stored in the primary side DC capacitor and the secondary side DC capacitor of the kth unit and a minimum value of the total values of energy stored in the primary side DC capacitor and the secondary side DC capacitor of all units;
a third amplifier that amplifies the second energy deviation;
a seventh adder that adds the output of the third amplifier to the smaller of a primary pulse width command value of the kth unit and a secondary pulse width command value of the kth unit;
a first limiter that limits an output of the seventh adder within an upper limit value and a lower limit value;
a tenth subtractor that calculates a difference between an input value and an output value of the first limiter;
an eleventh subtractor that subtracts a difference between an input value and an output value of the first limiter from the larger one of the primary pulse width command value of the kth unit and the secondary pulse width command value of the kth unit;
a second limiter that limits the output of the eleventh subtractor to within an upper limit value and a lower limit value;
a fourth switch that outputs the output of the second limiter when the primary pulse width command value of the kth unit is greater than the secondary pulse width command value of the kth unit, and outputs the output of the first limiter otherwise;
a fifth switch that outputs the output of the first limiter when the primary pulse width command value of the kth unit is greater than the secondary pulse width command value of the kth unit, and outputs the output of the second limiter otherwise;
a first multiplier for multiplying a primary side AC current detection value of the kth unit by 1/n or multiplying a secondary side AC current detection value of the kth unit by n when a turns ratio of the transformer is primary winding:secondary winding=1:n;
a third adder that adds an amplified DC component of the primary side AC current detection value of the kth unit to an output of the fourth switch and outputs the result as a positive side pulse width command value of the primary side of the kth unit;
a fifth subtractor that subtracts a value obtained by amplifying a DC component of a primary side AC current detection value of the kth unit from an output of the fourth switch, and outputs the result as a negative side pulse width command value of the primary side of the kth unit;
a fourth adder that adds an amplified value of a DC component of a secondary side AC current detection value of the kth unit to an output of the fifth switch and outputs the result as a positive side pulse width command value of the secondary side of the kth unit;
a sixth subtractor that subtracts a value obtained by amplifying a DC component of a secondary side AC current detection value of the kth unit from an output of the fifth switch, and outputs the result as a negative side pulse width command value of the secondary side of the kth unit;
4. The DAB bidirectional isolated DC/DC converter according to claim 1, further comprising: a ninth subtractor that calculates a second energy deviation, which is a deviation between a total value of energy stored in the primary side DC capacitor and the secondary side DC capacitor of the kth unit and a minimum value of the total values of energy stored in the primary side DC capacitor and the secondary side DC capacitor of all units;
a third amplifier that amplifies the second energy deviation;
a seventh adder that adds the output of the third amplifier to the smaller of a primary pulse width command value of the kth unit and a secondary pulse width command value of the kth unit;
a first limiter that limits an output of the seventh adder within an upper limit value and a lower limit value;
a tenth subtractor that calculates a difference between an input value and an output value of the first limiter;
an eleventh subtractor that subtracts a difference between an input value and an output value of the first limiter from the larger one of the primary pulse width command value of the kth unit and the secondary pulse width command value of the kth unit;
a second limiter that limits the output of the eleventh subtractor to within an upper limit value and a lower limit value;
a twelfth subtractor that calculates a difference between an input value and an output value of the second limiter;
a fourth switch that outputs the output of the second limiter when the primary pulse width command value of the kth unit is greater than the secondary pulse width command value of the kth unit, and outputs the output of the first limiter otherwise;
a fifth switch that outputs the output of the first limiter when the primary pulse width command value of the kth unit is greater than the secondary pulse width command value of the kth unit, and outputs the output of the second limiter otherwise;
a first multiplier for multiplying a primary side AC current detection value of the kth unit by 1/n or multiplying a secondary side AC current detection value of the kth unit by n when a turns ratio of the transformer is primary winding:secondary winding=1:n;
a third subtractor that subtracts a DC component of a primary side AC current detection value of the kth unit from a difference between an input value and an output value of the second limiter;
a fourth subtractor that subtracts a DC component of the secondary AC current detection value of the kth unit from a value obtained by inverting a sign of a difference between an input value and an output value of the second limiter;
a third adder that adds a value obtained by amplifying the output of the third subtractor to an output of the fourth switch and outputs the result as a positive side pulse width command value on the primary side of the kth unit;
a fifth subtractor that subtracts a value obtained by amplifying the output of the third subtractor from the output of the fourth switch and outputs the result as a negative side pulse width command value on the primary side of the kth unit;
a fourth adder that adds a value obtained by amplifying the output of the fourth subtractor to an output of the fifth switch and outputs the result as a positive side pulse width command value on the secondary side of the kth unit;
a sixth subtractor that subtracts a value obtained by amplifying the output of the fourth subtractor from the output of the fifth switch and outputs the result as a secondary negative side pulse width command value of the kth unit;
4. The DAB bidirectional isolated DC/DC converter according to claim 1, further comprising: A primary side DC power supply;
A secondary DC power supply;
a first unit to an mth unit (m: an integer of 2 or more) connected between the primary side DC power supply and the secondary side DC power supply;
primary side DC capacitors of the first unit to the mth unit connected in series between a positive electrode and a negative electrode of the primary side DC power supply;
secondary-side DC capacitors of the first unit to the mth unit connected in series between a positive electrode and a negative electrode of the secondary-side DC power supply;
First inverters of the first unit to the m unit connected to the primary side DC capacitors of the first unit to the m unit, respectively;
second inverters of the first unit to the m unit connected to the secondary side DC capacitors of the first unit to the m unit, respectively;
Transformers of the first unit to the m unit, each having a primary winding connected to an AC side of the first inverter of the first unit to the m unit, and a secondary winding connected to an AC side of the second inverter of the first unit to the m unit,
a control unit that generates gate signals for the first and second inverters;
A control method for a DAB bidirectional isolated DC/DC converter comprising:
The control unit is
a first subtractor that subtracts a primary side DC capacitor voltage average value from a sum of a primary side DC capacitor voltage of the kth unit (k=an integer from 1 to m) and an unbalance voltage command value of the kth unit to calculate a primary side voltage deviation of the kth unit;
a second subtractor that subtracts a secondary DC capacitor voltage average value from a sum of the secondary DC capacitor voltage of the kth unit and the unbalance voltage command value of the kth unit to calculate a secondary voltage deviation of the kth unit;
a turns ratio multiplier that multiplies the secondary voltage deviation by -1/n, or multiplies the secondary voltage deviation by -1 and multiplies the primary voltage deviation by n, when a turns ratio of the transformer is primary winding:secondary winding=1:n;
a first amplifier that amplifies the primary voltage deviation when a power command value is greater than a first threshold, amplifies the secondary voltage deviation when the power command value is less than a second threshold, and amplifies either the primary voltage deviation or the secondary voltage deviation, or a sum of both, when the power command value is equal to or greater than the second threshold and less than the first threshold, or outputs 0 as a phase of the kth unit;
a second adder that adds a phase command value to the phase of the kth unit and outputs the result as a phase difference command value;
and controlling the first inverter and the second inverter of the kth unit based on the phase difference command value;
A control method for a DAB type bidirectional isolated DC/DC converter, characterized in that the phase difference between the AC voltages output by the first inverter and the second inverter of each unit is controlled so that the DC capacitor voltages upstream of the power transmission of each unit are equal.

Images