JP7835267B2 - DAB-type bidirectional isolated DC/DC converter and its control method - Google Patents

Description

This invention relates to voltage balance control in a series connection of a dual active bridge (DAB) type bidirectional isolated DC/DC converter, which converts DC power to AC power using an inverter, isolates it using a transformer, and converts it back to DC using another inverter.

Non-patent document 1 and patent documents 1-3 describe a method for controlling the balance of capacitor voltage using an auxiliary converter. By using an auxiliary converter, the deviation of the capacitor voltage can be kept very small under any conditions.

Non-patent document 1 and patent document 1 use a DAB type converter as an auxiliary converter, patent document 2 uses a chopper, and patent document 3 uses a resonant circuit and a voltage doubler rectifier circuit. Since the auxiliary converter in patent document 3 is composed only of passive elements, the capacitor voltage can be balanced without the use of separate control means.

Patent Document 4 describes a configuration in which a bridge cell is connected to one end of a DAB unit, and the cascaded bridge cell configuration is connected to a power supply. A method for balancing the capacitor voltage has been established for this cascaded bridge cell configuration, and it can also handle AC power supplies. If the power supply is DC only, the number of semiconductor elements can be reduced by replacing the bridge cell with a chopper cell. A switch is connected to the other end of the DAB unit, allowing the number of parallel DAB units to be freely switched according to the number and capacity of the load.

International release WO2017/163508 Japanese Patent Publication No. 2017-017868 Japanese Patent Publication No. 2017-017869 Japanese Patent Publication No. 2019-213424

Takuji Ishibashi, Takushi Jimichi, and Osamu Mori, "Circuit Design and Control Method for High-Voltage, High-Capacity DC/DC Converters for DC Transmission and Distribution Systems of Large-Scale Offshore Wind Power Generation," Transactions of the Institute of Electrical Engineers of Japan, Vol. 138, No. 1, pp. 58-66, 2018.

However, in the configurations described in Non-Patent Document 1 and Patent Documents 1-3, the number of components, cost, and device volume increase due to the addition of auxiliary converters. Patent Document 1 requires M-1 auxiliary converters for an M-series configuration.

Non-patent document 1 describes a configuration with 3 series and 3 parallel inputs and 9 series outputs, requiring two auxiliary converters. Furthermore, the design of the auxiliary converter capacities also presents a problem.

For example, Non-Patent Document 1 describes a design example that takes into account variations in semiconductor losses and reactors. However, it cannot accommodate other factors, such as the increase in leakage current due to the aging of DC capacitors, making it impossible to maintain balance. Designing the capacitance with a margin increases costs and device volume. Furthermore, the configurations in Non-Patent Document 1 and Patent Documents 1 and 2 require separate control means for auxiliary circuits, increasing costs due to the presence of detectors and control boards.

The configuration described in Patent Document 3 eliminates the need for control means. However, designing the adjustment voltage is difficult. If the adjustment voltage is excessive, even if the capacitor voltage is balanced, current will continue to circulate between the upper and lower DAB units via the auxiliary converter, increasing losses. If the adjustment voltage is insufficient, the capacitor voltage balance will be greatly disrupted before current begins to flow through the auxiliary converter, exacerbating the capacitor voltage deviation.

Patent Document 4 shows that the number of parts, cost, and device volume increase due to the bridge cell/chopper cell connected to one end. Furthermore, a switch is required at the other end, which also increases the number of parts, cost, and device volume. In particular, the switch requires M x M switches for M units and M loads, significantly increasing the number of parts. Using mechanical contacts for the switches presents lifespan issues, and circuit breakers designed for DC current are large and expensive. Using semiconductor switches presents problems with increased losses due to voltage drop.

Because DAB converters have isolation between the input and output sides, multiple units can be connected in series and parallel. In addition to converting and isolating high-current DC power when connected in parallel, bidirectional conversion from high-voltage power to low-voltage, high-current power is possible by connecting one end in series. Furthermore, by designing and mass-producing a single DAB unit, multiple units can be connected in series and parallel to handle high-voltage and high-power conversion.

The problem in this case is the voltage balance of the capacitor at one end of the series connection. If the voltage balance is disrupted, the voltage load concentrates on a specific DAB unit, leading to problems such as overheating of the unit, component failure due to switching surges, and component failure due to overvoltage. If the other end is connected in parallel, charge from the DC capacitor can be transferred to another unit via the parallel connection, maintaining the series capacitor voltage balance.

However, when both ends are connected in series, charge movement is limited to within the same unit, making it difficult to maintain balance.

For the reasons described above, achieving equal capacitor voltage balance in a DAB-type bidirectional isolated DC/DC converter with both ends connected in series becomes a challenge.

The present invention was devised in view of the above-mentioned conventional problems, and one embodiment thereof is a DAB type bidirectional isolated DC/DC converter comprising a primary DC power supply, a secondary DC power supply, and a first unit to the mth unit (m: an integer of 2 or more) connected between the primary DC power supply and the secondary DC power supply, wherein the primary DC capacitors of the first unit to the mth unit are connected in series between the positive and negative terminals of the primary DC power supply, the secondary DC capacitors of the first unit to the mth unit are connected in series between the positive and negative terminals of the secondary DC power supply, and the first inverters of the first unit to the mth unit are connected to the primary DC capacitors of the first unit to the mth unit, respectively. The system comprises: a transformer; second inverters for the first to m units, each connected to the secondary DC capacitors of the first to m units; transformers for the first to m units, each having a primary winding connected to the AC side of the first inverter and a secondary winding connected to the AC side of the second inverter; and a control unit that generates gate signals for the first and second inverters. The control unit controls the phase difference between the AC voltages output by the first and second inverters of each unit so that the DC capacitor voltages upstream of the power transmission of each unit are equal.

Furthermore, in one embodiment, the control unit includes a first subtractor that calculates the primary voltage deviation of the k-th unit by subtracting the average value of the primary DC capacitor voltage from the sum of the primary DC capacitor voltage of the k-th unit and the unbalanced voltage command value of the k-th unit; a second subtractor that calculates the secondary voltage deviation of the k-th unit by subtracting the average value of the secondary DC capacitor voltage from the sum of the secondary DC capacitor voltage of the k-th unit and the unbalanced voltage command value of the k-th unit; and, when the turns ratio of the transformer is primary winding:secondary winding = 1:n, multiplying the secondary voltage deviation by -1/n, or multiplying the secondary voltage deviation by -1, and then... The system comprises a turns ratio multiplier that multiplies the secondary voltage deviation by n, a first amplifier that amplifies the primary voltage deviation when the power command value is greater than a first threshold, amplifies the secondary voltage deviation when the power command value is less than a second threshold, and amplifies the sum of either the primary voltage deviation or the secondary voltage deviation, or both, or outputs 0 as the phase of the k-th unit when the power command value is greater than or equal to the second threshold and less than the first threshold, and a second adder that adds a phase command value to the phase of the k-th unit and outputs a phase difference command value, and controls the first and second inverters of the k-th unit based on the phase difference command value.

Furthermore, one embodiment of this configuration is characterized by setting the unbalanced voltage command value of the k-th unit to 0.

Furthermore, in another embodiment, the control unit controls the phase difference between the AC voltages output by the first and second inverters of the k-th unit so that the DC capacitor voltage upstream of the power transmission of the k-th unit decreases when the total energy stored in the primary and secondary DC capacitors of the k-th unit is larger than that of other units, and controls the phase difference between the AC voltages output by the first and second inverters of the k-th unit so that the DC capacitor voltage upstream of the power transmission of the k-th unit increases when the total energy stored in the primary and secondary DC capacitors of the k-th unit is smaller than that of other units.

Furthermore, in another embodiment, the control unit controls the phase difference between the AC voltages output by the first and second inverters of the k-th unit so that when the DC capacitor voltage downstream of the k-th unit's power transmission is larger than that of other units, the DC capacitor voltage upstream of the k-th unit's power transmission is smaller, and when the DC capacitor voltage downstream of the k-th unit's power transmission is smaller than that of other units, the control unit controls the phase difference between the AC voltages output by the first and second inverters of the k-th unit so that the DC capacitor voltage upstream of the k-th unit's power transmission is larger.

Furthermore, in another embodiment, the control unit is characterized by comprising: a seventh subtractor that calculates a first energy deviation between the total energy stored in the primary DC capacitor and the secondary DC capacitor of the k-th unit and the average value of the total energy stored in the primary DC capacitor and the secondary DC capacitor of all units; and a second amplifier that amplifies the first energy deviation and outputs it as the unbalanced voltage command value of the k-th unit.

Furthermore, in another embodiment, the control unit is characterized by reducing the operating power factor of a unit whose total energy stored in the primary DC capacitor and the secondary DC capacitor is not the smallest among all units.

Furthermore, in another embodiment, the control unit is characterized by reducing the operating power factor of a unit whose DC capacitor voltage downstream of the power transmission is not the minimum among all units.

In another embodiment, the control unit includes a ninth subtractor that calculates a second energy deviation, which is the difference between the total energy stored in the primary DC capacitor and the secondary DC capacitor of the k-th unit and the minimum total energy stored in the primary DC capacitor and the secondary DC capacitor of all units; a third amplifier that amplifies the second energy deviation; a seventh adder that adds the output of the third amplifier to the smaller of the primary pulse width command value of the k-th unit and the secondary pulse width command value of the k-th unit; and a control unit that limits the output of the seventh adder to an upper limit and a lower limit. A first limiter, a tenth subtractor that calculates the difference between the input and output values of the first limiter, an eleventh subtractor that subtracts the difference between the input and output values of the first limiter from the larger of the primary pulse width command value of the kth unit and the secondary pulse width command value of the kth unit, a second limiter that limits the output of the eleventh subtractor to an upper and lower limit, a fourth switch that outputs the output of the second limiter if the primary pulse width command value of the kth unit is greater than the secondary pulse width command value of the kth unit, and outputs the output of the first limiter otherwise, and the kth unit A fifth switch that outputs the output of the first limiter if the primary pulse width command value is greater than the secondary pulse width command value of the kth unit, and outputs the output of the second limiter otherwise; a first multiplier that multiplies the primary AC current detection value of the kth unit by 1/n or the secondary AC current detection value of the kth unit by n when the turns ratio of the transformer is primary winding:secondary winding = 1:n; a third adder that adds the amplified DC component of the primary AC current detection value of the kth unit to the output of the fourth switch and outputs it as the primary positive pulse width command value of the kth unit; and the fourth switch The system is characterized by comprising: a fifth subtractor that subtracts the amplified DC component of the primary AC current detection value of the k-th unit from the output of the switch and outputs it as the negative pulse width command value for the primary side of the k-th unit; a fourth adder that adds the amplified DC component of the secondary AC current detection value of the k-th unit from the output of the fifth switch and outputs it as the positive pulse width command value for the secondary side of the k-th unit; and a sixth subtractor that subtracts the amplified DC component of the secondary AC current detection value of the k-th unit from the output of the fifth switch and outputs it as the negative pulse width command value for the secondary side of the k-th unit.

Furthermore, in another embodiment, the control unit is characterized by increasing the DC component of the current output by a unit whose total energy stored in the primary DC capacitor and the secondary DC capacitor is not the smallest among all units.

Furthermore, in another embodiment, the control unit is characterized by increasing the DC component of the current output by units other than those with the minimum DC capacitor voltage downstream of the power transmission.

Furthermore, in another embodiment, a ninth subtractor calculates a second energy deviation, which is the difference between the total energy stored in the primary DC capacitor and the secondary DC capacitor of the k-th unit and the minimum total energy stored in the primary DC capacitor and the secondary DC capacitor of all units; a third amplifier amplifies the second energy deviation; a seventh adder adds the output of the third amplifier to the smaller of the primary pulse width command value of the k-th unit and the secondary pulse width command value of the k-th unit; a first limiter limits the output of the seventh adder to an upper and lower limit; and a third amplifier calculates the difference between the input value and the output value of the first limiter. A 10th subtractor, an 11th subtractor that subtracts the difference between the input and output values of the first limiter from the larger of the primary pulse width command value of the kth unit and the secondary pulse width command value of the kth unit, a second limiter that limits the output of the 11th subtractor to an upper limit and a lower limit, a 12th subtractor that calculates the difference between the input and output values of the second limiter, a fourth switch that outputs the output of the second limiter if the primary pulse width command value of the kth unit is larger than the secondary pulse width command value of the kth unit, and outputs the output of the first limiter otherwise, and the primary pulse width command value of the kth unit is larger than the secondary pulse width command value of the kth unit A fifth switch that outputs the output of the first limiter if the pulse width is greater than the pulse width command value, and outputs the output of the second limiter otherwise; a first multiplier that multiplies the primary AC current detection value of the kth unit by 1/n or the secondary AC current detection value of the kth unit by n when the turns ratio of the transformer is primary winding:secondary winding = 1:n; a third subtractor that subtracts the DC component of the primary AC current detection value of the kth unit from the difference between the input and output values of the second limiter; a fourth subtractor that subtracts the DC component of the secondary AC current detection value of the kth unit from the value obtained by inverting the sign of the difference between the input and output values of the second limiter; and the output of the fourth switch, The device is characterized by comprising: a third adder that adds the amplified output of the third subtractor to the output of the k-th unit as the positive pulse width command value on the primary side; a fifth subtractor that subtracts the amplified output of the third subtractor from the output of the fourth switch to the negative pulse width command value on the primary side of the k-th unit; a fourth adder that adds the amplified output of the fourth subtractor to the output of the fifth switch to the positive pulse width command value on the secondary side of the k-th unit; and a sixth subtractor that subtracts the amplified output of the fourth subtractor from the output of the fifth switch to the negative pulse width command value on the secondary side of the k-th unit.

According to the present invention, in a DAB-type bidirectional isolated DC/DC converter with both ends connected in series, it becomes possible to equalize the capacitor voltage balance.

This figure shows the main circuit configuration of the DAB type bidirectional isolated DC/DC converter in embodiments 1 to 4. Block diagrams showing the phase difference command value calculation units of embodiments 1 to 4. Block diagrams showing the pulse width command value calculation units of Embodiments 1 and 2. Block diagrams showing the gate signal generation units of embodiments 1 to 4. This figure shows an example of the primary AC voltage V1k, secondary AC voltage V2k, and gate signals T2k1, T2k2, T2k3, and T2k4 of the k-th unit. This diagram illustrates the effect of the primary DC capacitor voltage when power is transmitted from the primary to the secondary side. This diagram illustrates the effect of the primary DC capacitor voltage when power is transmitted from the secondary side to the primary side. A block diagram showing the unbalanced voltage command value calculation unit of Embodiment 2. A block diagram showing the pulse width command value calculation unit of Embodiment 3. A block diagram showing the pulse width command value calculation unit of Embodiment 4.

The following describes in detail, with reference to Figures 1 to 10, embodiments 1 to 4 of the DAB-type bidirectional isolated DC/DC converter according to the present invention.

[Embodiment 1]
This invention is intended to be applied to the circuit shown in Figure 1. The configuration consists of m-series DAB units connected in series on both sides, with the left side being the primary and the right side being the secondary. The first to m-th units are connected between the primary DC power supply DC1 and the secondary DC power supply DC2.

The primary DC capacitors C1 of the first to m units are connected in series between the ends of the primary DC power supply DC1. The first and second switching elements S1 and S2 are connected in series between the ends of the primary DC capacitor C1 of each unit, respectively. Furthermore, the third and fourth switching elements S3 and S4 are connected in series between the ends of the primary DC capacitor C1 of each unit. The first to fourth switching elements S1 to S4 constitute the first inverter.

The secondary DC capacitors C2 of the first to m units are connected in series between the two ends of the secondary DC power supply DC2. The fifth and sixth switching elements S5 and S6 are connected in series between the two ends of the secondary DC capacitor C2 of each unit, respectively. Furthermore, the seventh and eighth switching elements S7 and S8 are connected in series between the two ends of the secondary DC capacitor C2 of each unit. The fifth to eighth switching elements S5 to S8 constitute the second inverter.

Note that in Figure 1, capacitors are connected in parallel to the first to eighth switching elements, but these capacitors can be omitted.

One end of reactor L1 is connected to the connection point of the first and second switching elements S1 and S2. One end of reactor L2 is connected to the connection point of the third and fourth switching elements S3 and S4. One end of reactor L3 is connected to the connection point of the fifth and sixth switching elements S5 and S6. One end of reactor L4 is connected to the connection point of the seventh and eighth switching elements S7 and S8.

The primary winding of the transformer Tr is connected between the other end of reactor L1 and the other end of reactor L2. The secondary winding of the transformer Tr is connected between the other end of reactor L3 and the other end of reactor L4. The first inverter, the second inverter, and the transformer Tr form one unit. In this embodiment 1, the system comprises the first to m (m: an integer of 2 or more) units.

In Figure 1, reactors L1 to L4 are connected in series between the first inverter, the second inverter, and the transformer Tr. However, the leakage inductance of the transformer Tr may be used instead of reactors L1 to L4. Alternatively, both reactors L1 to L4 and the leakage inductance of the transformer Tr may be used.

Furthermore, let Vdc1 be the voltage of the primary DC power supply DC1, Vdc2 be the voltage of the secondary DC power supply DC2, Vdc11 to Vdc1m be the primary DC capacitor voltages of the primary DC capacitor C1 of the 1st to mth units, Vdc21 to Vdc2m be the secondary DC capacitor voltages of the secondary DC capacitor C2 of the 1st to mth units, V1k be the primary AC voltage of the kth unit, V2k be the secondary AC voltage of the kth unit, i1k be the primary AC current of the kth unit, and i2k be the secondary AC current of the kth unit. Here, k is an integer from 1 to m.

Figures 2-4 show block diagrams of the control unit of the k-th unit in the circuit configuration of Figure 1 in this embodiment 1. The control unit generates the gate signals for the first and second inverters. Figure 2 is a block diagram of the phase difference command value (θk) calculation unit of the k-th unit.

The first low-pass filter (LPF1) removes ripple and noise at twice the frequency of the fundamental wave from the primary DC capacitor voltage Vdc1k of the k-th unit.

The average primary DC capacitor voltage Vdc1avg is the sum of the primary DC capacitor voltages Vdc11 to Vdc1m or the primary DC voltage Vdc1 divided by the number of units m.

The first subtractor 1 subtracts the average primary DC capacitor voltage Vdc1avg from the sum of the primary DC capacitor voltage Vdc1k of the k-th unit to which the first low-pass filter LPF1 is applied and the unbalanced voltage command value Vdck* of the k-th unit, thereby determining the primary voltage deviation of the k-th unit. In this embodiment 1, Vdck* = 0.

The second low-pass filter (LPF2) removes ripple and noise at twice the frequency of the fundamental wave from the secondary DC capacitor voltage Vdc2k of the k-th unit. The average value of the secondary DC capacitor voltage, Vdc2avg, is the sum of the secondary DC capacitor voltages Vdc21 to Vdc2m or the secondary DC voltage Vdc2 divided by the number of units (m).

The second subtractor 2 subtracts the average value of the secondary DC capacitor voltage Vdc2avg from the sum of the secondary DC capacitor voltage Vdc2k of the k-th unit (to which the second low-pass filter LPF2 is applied) and the unbalanced voltage command value Vdck* of the k-th unit, thereby determining the secondary voltage deviation of the k-th unit.

In Figure 2, P* represents the power command value transmitted between the primary and secondary sides. If the power command value P* is positive, power is transmitted from the primary to the secondary side; if it is negative, power is transmitted from the secondary to the primary side. The power command value P* can be supplied externally, or it may be obtained through voltage control or current control of either the primary DC voltage Vdc1 or the secondary DC voltage Vdc2.

The first comparator 3 determines whether the power command value P* is positive or negative. The turns ratio calculator 4 multiplies the output of the second subtractor 2 (secondary voltage deviation) by a value obtained by multiplying the reciprocal of the transformer Tr's turns ratio by -1. Alternatively, the turns ratio calculator 4 may multiply the output of the second subtractor 2 (secondary voltage deviation) by -1 and then multiply the output of the first subtractor 1 (primary voltage deviation) by the transformer Tr's turns ratio n. Here, the turns ratio of the transformer Tr is assumed to be primary:secondary = 1:n.

The first switch SW1 outputs the primary voltage deviation of the k-th unit if the power command value P* is positive, and the output of the turns ratio calculator 4 if the power command value P* is zero or negative.

To prevent frequent switching of the first switch SW1, if the power command value P* is near zero, the state of the switch from the previous switch may be maintained to provide a hysteresis characteristic. Alternatively, if the power command value P* is zero, the average value of the primary voltage deviation and the secondary voltage deviation of the k-th unit may be output.

The first amplifier 5 amplifies the output of the first switch SW1 and outputs the phase θkb of the k-th unit. In this example, the following two components are used in combination.

The proportional amplifier P1 outputs a value proportional to the output of the first switch SW1. The gain-controlled first-order lag filter 5a amplifies the low-frequency components of the output of the first switch SW1.

The first adder 6 adds the two amplifier outputs and outputs a phase θkb. The second adder 7 adds a separately provided phase command value θ* to the phase θkb and outputs the phase difference command value θk for the k-th unit.

The phase command value θ* may be provided by feedback control of the DC current and voltage. Alternatively, it may be calculated from the power command value P*, the primary DC capacitor voltage Vdc1k of the k-th unit, and the secondary DC capacitor voltage Vdc2k of the k-th unit.

Here, when the phase θkb, phase command value θ*, and phase difference command value θk of the k-th unit are positive, the phase of the primary AC voltage V1k of the k-th unit leads the secondary AC voltage V2k of the k-th unit, and power is transmitted from the primary side to the secondary side. Figure 3 shows a block diagram of the pulse width command value (W1kp, W1km, W2kp, W2km) calculation unit.

The third low-pass filter (LPF3) extracts the DC component of the primary AC current detection value i1k of the k-th unit.

The first multiplier 8 multiplies the detected AC current value i2k of the k-th unit by the turns ratio n. The fourth low-pass filter LPF 4 extracts the DC component from the output of the first multiplier 8 (n × i2k).

In Figure 3, the detected secondary AC current value i2k of the k-th unit was multiplied by the turns ratio n of the transformer Tr. However, the detected primary AC current value i1k of the k-th unit may also be multiplied by the reciprocal of the turns ratio n (1/n). Here, the turns ratio of the transformer Tr is assumed to be primary:secondary = 1:n.

The third subtractor 9 subtracts the output of the third low-pass filter LPF3 from the DC component command value to determine the deviation. The fourth subtractor 10 subtracts the output of the fourth low-pass filter LPF4 from the DC component command value to determine the deviation. In embodiments 1, 2, and 3, the DC component command value is zero.

The PI amplifier 11 amplifies the deviation obtained by the third subtractor 9. The PI amplifier 12 amplifies the deviation obtained by the fourth subtractor 10.

The third adder 13 adds the output of the PI amplifier 11, which takes the primary side pulse width command value W1k of the k-th unit and the primary side AC current detection value i1k of the k-th unit as inputs, and outputs the primary side positive pulse width command value W1kp of the k-th unit.

The fifth subtractor 14 subtracts the output of the PI amplifier 11 (which takes the primary AC current detection value i1k of the k-th unit as input) from the primary pulse width command value W1k of the k-th unit, and outputs the negative pulse width command value W1km of the k-th unit's primary side.

The fourth adder 15 adds the output of the PI amplifier 12, which takes the secondary pulse width command value W2k of the k-th unit and the secondary AC current detection value i2k of the k-th unit as inputs, and outputs the secondary positive pulse width command value W2kp of the k-th unit.

The sixth subtractor 16 subtracts the output of the PI amplifier 12 (which takes the secondary AC current detection value i2k of the k-th unit as input) from the secondary pulse width command value W2k of the k-th unit, and outputs the negative pulse width command value W2km of the k-th unit's secondary side.

Figure 4 shows a block diagram of the gate signal generation unit.

The second multiplier 17 multiplies the phase difference command value θk of the k-th unit by 0.5. The third multiplier 18 multiplies the output of the second multiplier 17 (0.5θk) by -1 to invert its sign.

The gate generator 19 receives the output of the second multiplier 17 (0.5θk), the positive pulse width command value W1kp on the primary side of the k-th unit, and the negative pulse width command value W1km on the primary side of the k-th unit, adds a dead time, and outputs gate signals T1k1, T1k2, T1k3, and T1k4. Gate signal T1k1 controls the first switching element S1, gate signal T1k2 controls the second switching element S2, gate signal T1k3 controls the third switching element S3, and gate signal T1k4 controls the fourth switching element S4.

The gate generator 20 receives the output of the third multiplier 18 (-0.5θk), the positive pulse width command value W2kp on the secondary side of the k-th unit, and the negative pulse width command value W2km on the secondary side of the k-th unit, adds a dead time, and outputs gate signals T2k1, T2k2, T2k3, and T2k4. Gate signal T2k1 controls the fifth switching element S5, gate signal T2k2 controls the sixth switching element S6, gate signal T2k3 controls the seventh switching element S7, and gate signal T2k4 controls the eighth switching element S8.

Figure 5 shows an example of the primary AC voltage V1k, secondary AC voltage V2k, and gate signals T2k1, T2k2, T2k3, and T2k4 of the k-th unit. In this example, the phase difference command value θk of the k-th unit is positive, the phase of the primary AC voltage V1k of the k-th unit leads the secondary AC voltage V2k of the k-th unit, and power is transmitted from the primary side to the secondary side.

This embodiment 1 demonstrates capacitor voltage balance control under conditions where a certain amount of power transmission is occurring. The balance control strategy will be explained using Figures 6 and 7.

Figure 6 shows only the primary side extracted from Figure 1. Power is transmitted from the primary side to the secondary side, and the transmitted power to each unit is assumed to be equal. Consider the case where the primary side DC capacitor voltage Vdc1k of the k-th unit is excessive compared to the average primary side DC capacitor voltage Vdc1avg, and the primary side DC capacitor voltage Vdc1m of the m-th unit is insufficient compared to the average primary side DC capacitor voltage Vdc1avg.

Since the DAB units are connected in series, the DC current flowing through each unit is constant. Because the primary DC capacitor voltage Vdc1k of the k-th unit is greater than that of the other units, the power input to the k-th unit also increases. However, since the power transmitted to the secondary side by the k-th unit is equal to that of the other units, the input power becomes excessive and charges the primary DC capacitor C1, further increasing the primary DC capacitor voltage Vdc1k of the k-th unit.

The primary DC capacitor voltage Vdc1m of unit m is lower than that of the other units, resulting in a decrease in the power input to unit m. To transmit the same power as the other units, the primary DC capacitor C1 of unit m must be discharged, further decreasing the primary DC capacitor voltage Vdc1m of unit m.

Therefore, when power is transmitted from the primary side to the secondary side, the voltage balance of the primary side DC capacitor C1 is unstable and requires control.

On the other hand, consider the case where power is transmitted from the secondary side to the primary side, as shown in Figure 7. Figure 7 is an extraction of only the primary side from Figure 1. The primary side DC capacitor voltage Vdc1k of the k-th unit is greater than the primary side DC capacitor voltages of the other units, and the power output by the k-th unit also increases. However, since the power received by the k-th unit from the secondary side is equal to that of the other units, the input power is insufficient relative to the output power, and this difference is compensated for by the discharge of the primary side DC capacitor C1 of the k-th unit. Therefore, the primary side DC capacitor voltage Vdc1k of the k-th unit decreases.

The primary DC capacitor voltage Vdc1m of the m-th unit is smaller than the primary DC capacitor voltages of the other units, and the power output of the m-th unit also decreases. Since the power received by the m-th unit from the secondary side is equal to that of the other units, the power received by the m-th unit from the secondary side becomes excessive relative to its output. This excess power charges the primary DC capacitor C1 of the m-th unit, increasing the primary DC capacitor voltage Vdc1m of the m-th unit.

Therefore, when power is transmitted from the secondary side to the primary side, the voltage balance of the primary side DC capacitor C1 is stable. While some deviation occurs, it balances spontaneously without the need for control. This balancing effect increases with increasing transmitted power, but becomes more difficult to balance and the deviation increases when the transmitted power is small. If the transmitted power is zero, the balancing effect disappears, resulting in instability.

In this embodiment 1, when the power command value P* is positive and power is transmitted from the primary side to the secondary side, the primary side DC capacitor voltage is balanced. As shown in Figure 2, when the power command value P* is positive, the first switch SW1 is switched to the upper position, and the deviation between the primary side DC capacitor voltage Vdc1k and the average primary side DC capacitor voltage Vdc1avg of the k-th unit is input to the first amplifier 5.

If the primary DC capacitor voltage Vdc1k of the k-th unit is excessive, the deviation will be positive, and the phase θkb amplified by the first amplifier 5 will also be positive. As a result, the phase of the primary AC voltage V1k of the k-th unit leads the secondary AC voltage V2k of the k-th unit, and the phase difference becomes larger than that of the other units. A larger power is transmitted from the primary to the secondary side of the k-th unit than in the other units, causing the primary DC capacitor voltage Vdc1k of the k-th unit to decrease and the deviation to shrink.

If the primary DC capacitor voltage Vdc1k of unit k is insufficient, the deviation will be negative. The power transmitted from the primary to the secondary side by unit k will be less than that of the other units, and the primary DC capacitor voltage Vdc1k of unit k will increase.

The above operation balances the primary capacitor voltage. However, since the charge necessary to balance the primary capacitor voltage is supplied from the secondary capacitor, the secondary capacitor voltage balance deteriorates.

However, as mentioned earlier, the secondary capacitor voltage balance is stable. Therefore, although some deviation occurs, the secondary capacitor voltage converges to the point where the power transmitted from the unit and the output power are balanced.

When the power command value P* is zero or negative and power is transmitted from the secondary side to the primary side, the secondary side capacitor voltage is balanced. If the power command value P* is negative, the first switch SW1 is switched to the lower position, and the deviation between the secondary side DC capacitor voltage Vdc2k and the average secondary side DC capacitor voltage Vdc2avg of the k-th unit is input to the first amplifier 5.

If the secondary DC capacitor voltage Vdc2k of unit k is excessive, the deviation becomes negative, and the phase θkb amplified by the first amplifier 5 also becomes negative. The phase of the primary AC voltage V1k of unit k lags behind the secondary AC voltage V2k of unit k, and the phase difference is larger than in the other units. In unit k, more power is transmitted from the secondary to the primary than in the other units, and the secondary DC capacitor voltage Vdc2k of unit k decreases.

If the secondary DC capacitor voltage Vdc2k of unit k is insufficient, the deviation will be positive. The power transmitted from the primary to the secondary side by unit k will be less than that of the other units, and the secondary DC capacitor voltage Vdc2k of unit k will increase.

The voltage balance of the primary DC capacitor C1 stabilizes spontaneously without any control.

The first amplifier 5 in Figure 2 does not use an integrator. The reason for this is explained below. An integrator has the characteristic of making the DC gain infinite, eliminating the DC deviation, and making the controlled capacitor voltage equal to the command value.

However, in Figure 1, the system being controlled, the sum of the unit capacitor voltages (Vdc1 on the primary side) is determined by external factors such as the connected voltage source and a separately prepared constant DC current control. Therefore, once the voltage of m-1 unit capacitors is determined, the voltage of the remaining capacitor is inevitably determined. While the degree of freedom of the controlled system is m-1, controlling it with m controllers results in insufficient degrees of freedom and unstable control.

In particular, if there is an error in the detector, the integrating amplifier of one unit may increase its output in an attempt to eliminate the deviation including the error, which in turn increases the deviation of other units, causing their integrating amplifiers to increase their output as well. This can lead to an unlimited increase in amplifier output.

As a countermeasure, the DC gain is kept finite, and the remaining small deviation is tolerated by controlling it with a proportional amplifier P1 and a gain-equipped first-order lag filter 5a. Alternatively, a balanced control method could be implemented in one of the m-1 units, replacing the amplifier in Figure 2 with a PI amplifier, while the remaining units (e.g., the first unit) could not perform the balanced control shown in Figure 2 and could instead fix the phase θ1b to zero.

In Figure 2, when the power command value P* is zero, the secondary DC capacitor voltage is balanced; however, the primary DC capacitor voltage may also be balanced. In situations such as standby mode under no load, where the power command value P* is close to zero and its sign frequently changes, a hysteresis characteristic may be introduced into the switching of the first switch SW1 to prevent frequent abrupt changes in phase θkb.

In this embodiment 1, the phase difference between the AC voltages output by the first and second inverters of each unit is controlled so that the DC capacitor voltages upstream of the power transmission of each unit are equal.

The average value of the primary and secondary voltage deviations may also be input to the first amplifier 5 for control. That is, the first amplifier 5 amplifies the primary voltage deviation when the power command value P* is greater than the first threshold, amplifies the secondary voltage deviation when the power command value P* is less than the second threshold, and amplifies either the primary or secondary voltage deviation, or both (average values), or outputs 0 as the phase θkb of the k-th unit when the power command value P* is greater than or equal to the second threshold but less than the first threshold.

However, this embodiment 1 alone cannot balance the capacitor voltage at a power command value P* = 0. This problem requires combination with embodiment 3, which will be described later.

In this embodiment 1, if the absolute value of the transmitted power is sufficiently large, the balance deviation of the capacitor voltage on the non-controlled side can be kept sufficiently small. However, there is a problem that the deviation becomes larger when the load is lighter and the absolute value of the transmitted power decreases.

As described above, according to this embodiment 1, under conditions where the transmitted power is relatively large, it is possible to maintain a balance between the DC capacitor voltages on both the primary and secondary sides.

Furthermore, it prevents voltage overload on specific units, thus preventing overheating and component damage due to overvoltage, and damage to switching elements due to surges.

Furthermore, the need for high voltage resistance in components is eliminated, reducing costs. Also, because auxiliary circuits are unnecessary compared to conventional technology, not only are costs reduced, but the device can be miniaturized.

[Embodiment 2]
Figure 8 shows a block diagram of the unbalanced voltage command value (Vdck*) calculation unit of the k-th unit in this second embodiment.

The fifth low-pass filter (LPF5) removes ripple and noise at twice the frequency of the fundamental wave of the primary DC capacitor voltage Vdc1k of the k-th unit, extracting the DC component. The sixth low-pass filter (LPF6) extracts the DC component of the secondary DC capacitor voltage Vdc2k of the k-th unit.

The fourth multiplier 21 calculates the square of the primary DC capacitor voltage Vdc1k of the k-th unit to which the fifth low-pass filter LPF5 is applied. The fifth multiplier 22 calculates the square of the secondary DC capacitor voltage Vdc2k of the k-th unit to which the sixth low-pass filter LPF6 is applied.

The sixth multiplier 23 multiplies the output of the fourth multiplier 21 by the value obtained by dividing the primary capacitor capacitance C1 by 2. The seventh multiplier 24 multiplies the output of the fifth multiplier 22 by the value obtained by dividing the secondary capacitor capacitance C2 by 2.

The fifth adder 25 adds the outputs of the sixth and seventh multipliers 23 and 24 to obtain the total energy value Ek stored in the primary DC capacitor C1 and secondary DC capacitor C2 connected to both sides of the k-th unit.

The seventh subtractor 26 calculates the first energy deviation, which is the difference between the total energy value Ek and the average value Eavg of the total energy values stored in the primary DC capacitor C1 and secondary DC capacitor C2 of all units.

The second amplifier 27 amplifies the output of the seventh subtractor 26 by applying a gain G2. The gain G2 can be a fixed value, or, as shown in Figure 8, it may be changed based on the power command value P* in the gain adjuster 28, for example, by reducing it when the power command value P* is near zero. The output of the second amplifier 27 becomes the unbalanced voltage command value Vdck*.

This second embodiment describes a method for reducing the deviation under light load conditions, which is one of the problems in the first embodiment.

In this second embodiment, first, the total energy value Ek stored in the primary DC capacitor C1 and secondary DC capacitor C2 of the k-th unit is determined. Next, the deviation between the average value Eavg of the total energy values of each unit (determined similarly) and the total energy value Ek is calculated. This is amplified by the gain G2, and the resulting value is taken as the unbalanced voltage command value Vdck* of the k-th unit.

The operation of this second embodiment will now be explained. As an example, the primary DC capacitor voltage is controlled when P* > 0. In this case, since Vdc11 to Vdc1m become approximately equal due to the control in the first embodiment, the stored energy of the primary DC capacitor becomes approximately equal.

The total energy value Ek reflects the magnitude of the secondary DC capacitor voltage Vdc2k of the k-th unit. If the secondary DC capacitor voltage Vdc2k of the k-th unit is greater than the average secondary DC capacitor voltage Vdc2avg, then the total energy value Ek will also be greater than the average total energy value Eavg, and the unbalanced voltage command value Vdck* will be positive.

This unbalanced voltage command value Vdck* is input to the first and second subtractors 1 and 2 in Figure 2. The first subtractor 1 subtracts the average primary DC capacitor voltage Vdc1avg from the sum of the primary DC capacitor voltage Vdc1k of the k-th unit (to which the first low-pass filter LPF1 is applied) and the unbalanced voltage command value Vdck* of the k-th unit, thereby obtaining the primary voltage deviation of the k-th unit.

The second subtractor 2 subtracts the average value of the secondary DC capacitor voltage Vdc2avg from the sum of the secondary DC capacitor voltage Vdc2k of the k-th unit (to which the second low-pass filter LPF2 is applied) and the unbalanced voltage command value Vdck* of the k-th unit, thereby determining the secondary voltage deviation of the k-th unit.

As a result, the command value for balance control (Vdc1avg - Vdck*) decreases, and the primary DC capacitor voltage Vdc1k of the k-th unit also decreases. Since the DC current flowing through each unit is constant, the power received by the k-th unit from the primary DC voltage Vdc1 decreases. Because the primary DC capacitor voltage Vdc1k of the k-th unit is the control target, the decrease in received power is reflected in the magnitude of the secondary DC capacitor voltage Vdc2k of the k-th unit. Therefore, the secondary DC capacitor voltage Vdc2k of the k-th unit decreases and can be brought closer to the average value of the secondary DC capacitor voltage Vdc2avg.

When P* < 0 and the secondary capacitor voltage is the control target of Embodiment 1, the total energy value Ek reflects the magnitude of the primary DC capacitor voltage Vdc1k of the k-th unit. If the primary DC capacitor voltage Vdc1k of the k-th unit is smaller than the average primary DC capacitor voltage Vdc1avg, the total energy value Ek will also be smaller than the average total energy value Eavg, and the unbalanced voltage command value Vdck* will be negative.

This unbalanced voltage command value Vdck* is input to the first and second subtractors 1 and 2 in Figure 2, and the calculation is performed as described above. As a result, the balance control command value (Vdc2avg - Vdck*) increases, and the secondary DC capacitor voltage Vdc2k of the k-th unit also increases. The power received by the k-th unit from the secondary DC voltage Vdc2 increases, increasing the primary DC capacitor voltage Vdc1k of the k-th unit and bringing it closer to the average value of the primary DC capacitor voltage Vdc1avg.

In this second embodiment, a small amount of capacitor voltage balance deviation is intentionally introduced on the primary side when P* > 0 and on the secondary side when P* < 0, i.e., on the upstream side of power transmission. This improves the capacitor voltage balance deviation on the secondary side when P* > 0 and on the primary side when P* < 0, i.e., on the downstream side.

In this second embodiment, when the total energy value Ek stored in the primary and secondary DC capacitors of the k-th unit (an integer from k to m) is larger than that of other units, the phase difference between the AC voltages output by the first and second inverters of the k-th unit is controlled so that the DC capacitor voltage upstream of the power transmission of the k-th unit becomes smaller. Conversely, when the total energy value Ek stored in the primary and secondary DC capacitors of the k-th unit is smaller than that of other units, the phase difference between the AC voltages output by the first and second inverters of the k-th unit is controlled so that the DC capacitor voltage upstream of the power transmission of the k-th unit becomes larger.

In this second embodiment, the input to the second amplifier 27 is not the downstream capacitor voltage of power transmission, but the total energy stored in the primary DC capacitor C1 and secondary DC capacitor C2 of the unit. The reason for this is explained below. When P* > 0, it is also conceivable to set the input to the second amplifier 27 to Vdc2k - Vdc2avg.

However, if, for example, the secondary DC capacitor voltage Vdc2k of the k-th unit is large, reducing the primary DC capacitor voltage Vdc1k of the k-th unit will decrease the power received by the secondary DC capacitor C2 of the k-th unit. However, lowering the primary DC capacitor voltage Vdc1k of the k-th unit requires discharging the primary DC capacitor C1 of the k-th unit. Since the discharged charge moves to the secondary DC capacitor C2 of the k-th unit via the DAB converter, the secondary DC capacitor voltage Vdc2k of the k-th unit will increase further.

Consequently, the aforementioned operation attempts to further reduce the primary DC capacitor voltage Vdc1k of the k-th unit. This makes the control system prone to instability, preventing a large value from being set for the gain G2, resulting in a very small effect.

On the other hand, the total energy value Ek stored in the primary DC capacitor C1 and the secondary DC capacitor C2 remains constant even as charge moves, unlike the capacitor voltage. Therefore, the control system is more stable, allowing for a high gain to be set and sufficient effectiveness to be obtained.

As mentioned above, it is preferable to set the input of the second amplifier 27 to the total energy value Ek, but the input of the second amplifier 27 may also be the downstream DC capacitor voltage. In this case, if the DC capacitor voltage downstream of the k-th unit's power transmission is larger than that of other units, the phase difference of the AC voltages output by the first and second inverters of the k-th unit is controlled so that the DC capacitor voltage upstream of the k-th unit's power transmission becomes smaller. Conversely, if the DC capacitor voltage downstream of the k-th unit's power transmission is smaller than that of other units, the phase difference of the AC voltages output by the first and second inverters of the k-th unit is controlled so that the DC capacitor voltage upstream of the k-th unit's power transmission becomes larger.

In this second embodiment, an effect can be obtained when there is a load, but in the absence of a load, changing the capacitor voltage on the upstream side of power transmission does not produce any difference because the received power is zero, and therefore no effect is obtained. For this reason, when the power command value P* is near zero, the gain G2 may be set to zero to prevent the generation of unnecessary deviations.

This second embodiment, when combined with the first embodiment, can maintain a sufficiently small balance deviation in the capacitor voltage even when the absolute value of the transmitted power is small. However, it has the problem that in the no-load state, the control means is lost and the deviation becomes large.

By using both Embodiment 1 and Embodiment 2 in combination, it is possible to maintain the voltage balance of both the primary and secondary DC capacitors even under conditions of low transmission power.

Compared to Embodiment 1, the side where the balance was evenly distributed becomes slightly less balanced, but the voltage balance on the side where a deviation occurred in Embodiment 1 can be improved.

This allows the voltage rating of the components to be lower than in Embodiment 1. Compared to Embodiment 3 alone or in combination with Embodiment 1, losses under conditions of low transmission power can be reduced.

[Embodiment 3]
Figure 9 shows a block diagram of the pulse width command value (W1kp, W1km, W2kp, W2km) calculation unit of this third embodiment. Figure 9 differs from Figure 3 in the following respects.

In this third embodiment, the primary pulse width command value W1k and the secondary pulse width command value W2k of the k-th unit are assumed to be determined as follows.

The primary DC voltage Vdc1 and the secondary DC voltage Vdc2/n (considering the winding ratio) are compared, and the pulse width command value of the voltage with the smaller voltage is set to a fixed value close to 1, for example, between 0.7 and 1. Alternatively, it may be set to a variable value with an upper limit of approximately 0.7 to 1, which is small when the power command value P* is close to zero and increases as the power command value P* moves away from zero.

Furthermore, the pulse width command value for the higher voltage is _W1 in equation (1) below. Note that _W2 in equation (1) is the pulse width command value for the lower voltage. Also, θ in equation (1) is the value obtained by amplifying the difference between the power command value P* and the value obtained by removing noise from the product of the secondary DC voltage Vdc2 and the secondary DC current Idc2 using a low-pass filter, using a PI amplifier.

The eighth subtractor 29 subtracts the secondary pulse width command value W2k of the kth unit from the primary pulse width command value W1k of the kth unit. The second comparator 30 receives the output of the eighth subtractor 29 and determines whether W1k > W2k. The second comparator 30 may have hysteresis characteristics to avoid frequent switching of the switches described later.

The second switch SW2 receives the primary pulse width command value W1k and the secondary pulse width command value W2k of the k-th unit as inputs. If W1k > W2k, it outputs W2k; if W1k ≤ W2k, it outputs W1k; that is, the smaller of W1k and W2k. The third switch SW3 receives the primary pulse width command value W1k and the secondary pulse width command value W2k of the k-th unit as inputs. If W1k > W2k, it outputs W1k; if W1k ≤ W2k, it outputs W2k; that is, the larger of W1k and W2k.

The ninth subtractor 31 calculates the second energy deviation, which is the difference between the total energy value Ek stored in the primary and secondary DC capacitors of the k-th unit and the minimum value Emin among all units' total energy values stored in the primary and secondary DC capacitors of each unit.

The third amplifier 32, which amplifies the second energy deviation, uses the following two components in this example: The proportional amplifier P2 outputs a value proportional to the second energy deviation obtained by the ninth subtractor 31. The gain-controlled first-order lag filter 32a amplifies the low-frequency components of the second energy deviation obtained by the ninth subtractor 31. The sixth adder 33 adds the output of the proportional amplifier P2 and the output of the gain-controlled first-order lag filter 32a.

The seventh adder 34 adds the output of the third amplifier 32 and the output of the second switch SW2. The first limiter 35 limits the output of the seventh adder 34. The upper limit of the first limiter 35 is usually 1, and the lower limit is a value greater than zero, such as 0.2. The upper limit may also be a value slightly less than 1.

The tenth subtractor 36 calculates the difference between the input and output of the first limiter 35 and outputs the value exceeding the limiter 35. The eleventh subtractor 37 subtracts the output of the tenth subtractor 36 from the output of the third switch SW3. The second limiter 38 limits the output of the eleventh subtractor 37. The upper and lower limits of the second limiter 38 are set in the same way as those of the first limiter 35.

The fourth switch SW4 receives the outputs of both the first limiter 35 and the second limiter 38. If W1k > W2k, it outputs the output of the second limiter 38; otherwise, it outputs the output of the first limiter 35.

The output value of the fourth switch SW4 is independent of the relative magnitudes of the primary pulse width command value W1k and the secondary pulse width command value W2k of the k-th unit; it is the value obtained by adding the amplifier output to the primary pulse width command value W1k of the k-th unit.

The fifth switch SW5 receives the outputs of both the first limiter 35 and the second limiter 38. If W1k > W2k, it outputs the output of the first limiter 35; otherwise, it outputs the output of the second limiter 38.

The output value of the fifth switch SW5 is independent of the relative magnitudes of the primary pulse width command value W1k and the secondary pulse width command value W2k of the k-th unit, and is the value obtained by subtracting the amplifier output from the secondary pulse width command value W2k of the k-th unit.

The third adder 13 adds the DC component of the primary AC current detection value i1k of the k-th unit, amplified by the PI amplifier 11, to the output of the fourth switch SW4, and outputs it as the primary positive pulse width command value W1kp. The fifth subtractor 14 subtracts the DC component of the primary AC current detection value i1k of the k-th unit, amplified by the PI amplifier 11, from the output of the fourth switch SW4, and outputs it as the primary negative pulse width command value W1km.

The fourth adder 15 adds the value obtained by amplified by the PI amplifier 12 of the DC component of the k-th unit's secondary AC current detection value i2k to the output of the fifth switch SW5, and outputs it as the secondary positive pulse width command value W2kp. The sixth subtractor 16 subtracts the value obtained by amplified by the PI amplifier 12 of the DC component of the k-th unit's secondary AC current detection value i2k from the output of the fifth switch SW5, and outputs it as the secondary negative pulse width command value W2km.

This third embodiment describes a method for reducing the balance deviation of the capacitor voltage under no-load conditions, which was a problem in the previous embodiments 1 and 2.

The operation of this third embodiment will now be described. First, similar to the second embodiment, the total energy value Ek stored in the primary and secondary DC capacitors of the k-th unit is calculated and input. Furthermore, the minimum value Emin among all units, based on the total energy values stored in the primary and secondary DC capacitors of each unit, is calculated, and the second energy deviation, which is the deviation from the total energy value Ek of the k-th unit, is input to the third amplifier 32.

The pulse widths of the primary AC voltage V1k and the secondary AC voltage V2k of the k-th unit are controlled based on the output of the third amplifier 32. The control involves first widening the narrower pulse width, and then narrowing the wider pulse width once the limiter is exceeded.

The operation of this embodiment 3 will be explained using the example where the secondary DC voltage Vdc2 is small, the secondary pulse width command value W2k = 0.7 to 1, the primary DC voltage Vdc1 is large, the primary pulse width command value W1k = (1), and the total stored energy value Ek of the k-th unit's DC capacitor is not the minimum. In this case, the pulse width of the secondary inverter output voltage of the k-th unit is set wide, and the AC side operates with a power factor of 1. The primary inverter output voltage is set with a narrow pulse width, sharing all the reactive power supplied to the transformer and reactor.

This reduces the primary AC current detection value i1k and the secondary AC current detection value i2k, thereby reducing copper losses and conduction losses. Here, by widening the pulse width of the primary inverter output voltage of the k-th unit, which has a narrow pulse width, the reactive power supplied to the AC side becomes excessive, and the secondary inverter of the k-th unit operates with a leading power factor.

Unnecessary reactive power exchange increases the amplitude of the primary AC current detection value i1k and the secondary AC current detection value i2k, increasing copper losses and conduction losses, and promoting capacitor voltage discharge.

If the capacitor voltage discharge is insufficient even when the pulse width of the primary inverter output voltage of the k-th unit is widened to 1, the pulse width of the secondary inverter output voltage of the k-th unit is narrowed. This further increases the reactive power supplied to the AC side and further decreases the capacitor voltage.

The unit with the smallest capacitor stored energy does not undergo pulse width modification, resulting in the same operation as the secondary pulse width command value W2k = 0.7 to 1 and the primary pulse width command value W1k = (1), thereby reducing losses and suppressing capacitor discharge. This operation improves the balance of the capacitor voltage.

In this third embodiment, for units where the total energy value Ek stored in the primary and secondary DC capacitors is not the minimum, the pulse width of the smaller of the primary pulse width command value W1k and the secondary pulse width command value W2k is widened, or the pulse width of the larger of the two is narrowed, or both are done, in order to increase the reactive power output by the unit (to lower the operating power factor). The primary pulse width command value W1k and the secondary pulse width command value W2k are then corrected, and output as the primary positive pulse width command value W1kp, the primary negative pulse width command value W1km, the secondary positive pulse width command value W2kp, and the secondary negative pulse width command value W2km.

Furthermore, for units other than the minimum DC capacitor voltage downstream of the k-th unit's power transmission, the primary pulse width command value W1k and the secondary pulse width command value W2k may be corrected by widening the smaller pulse width of the primary pulse width command value W1k and the secondary pulse width command value W2k, or by narrowing the larger pulse width, or both, in order to increase the reactive power output by the unit (to lower the operating power factor). The output values may then be W1kp for the positive primary pulse width command value W1kp, W1km for the negative primary pulse width command value W2kp, and W2km for the negative secondary pulse width command value W2kp.

In this embodiment 3, the pulse width is set to the first and second limiters 35 and 38. The upper limit of the first and second limiters 35 and 38 is usually 1, but it may be set to approximately 0.7 to 0.95. Setting the lower limit of the first and second limiters 35 and 38 to 0 will result in no AC voltage output, making power transmission impossible and leading to loss of control. Therefore, it should be set to a value greater than 0, such as approximately 0.2.

In this third embodiment, priority is given to widening the narrower pulse width, but the opposite approach may be taken: prioritizing narrowing the wider pulse width. Alternatively, both pulse widths may be controlled equally.

In this embodiment 3, the gains P2 and G2 of the third amplifier 32 are kept constant. However, as in embodiments 1 and 2, the capacitor voltage can be balanced even without applying embodiment 3 if there is a load. Therefore, the gain may be switched to 0 if the power command value P* is not 0, thereby reducing losses. The gain may also be set to 0 under conditions where the absolute value of the power command value P* is 0.1 or greater, and even under light loads, intentionally generating losses can reduce the efficiency slightly, but also reduce the deviation in the capacitor voltage balance. The gain switching may have hysteresis characteristics, and the gain may be changed based on the absolute value of the power command value P*.

In Embodiment 3, losses are intentionally generated, naturally increasing the thermal load of the unit. However, Embodiment 3 assumes no load or light load conditions. In this case, copper loss, conduction loss, and switching loss are very small, with no-load losses, primarily iron loss, accounting for the majority. The losses of other units are simply adjusted to match the unit with the largest no-load loss, resulting in a small increase in overall losses.

For example, unless extreme losses increase due to abnormalities such as a crack in the transformer core leading to increased magnetic flux density and hysteresis loss, damage to the insulation of laminated steel plates due to impact leading to increased eddy current loss, or increased leakage current in capacitors due to aging, there is no need to enlarge the cooling mechanism.

According to this embodiment 3, even under conditions where the transmitted power is zero, the voltage balance of both the primary and secondary DC capacitors can be maintained, allowing operation to continue. This converter configuration can also be applied to applications where standby situations with no load frequently occur.

By using this method in combination with Embodiments 1 and 2, the voltage balance deviation of the DC capacitor can be reduced, although the power loss increases under certain conditions.

Furthermore, under conditions where the transmission power is relatively large, the control gain of this embodiment 3 can be reduced to disable it and prevent efficiency degradation. Also, unlike embodiment 4 described later, the ripple generated on the DC side is twice the fundamental frequency, so it can be removed with a small filter.

[Embodiment 4]
Figure 10 shows a block diagram of the pulse width command value (W1kp, W1km, W2kp, W2km) calculation unit of this embodiment 4. Figure 10 differs from Figure 9 in the following respects.

In this fourth embodiment, a twelfth subtractor 39 is added. The twelfth subtractor 39 calculates the difference between the input and output of the second limiter 38 and outputs the value exceeding the second limiter 38.

The output of the 12th subtractor 39 is used as the DC component command value of the primary AC current of the k-th unit and is used by the 3rd subtractor 9. Furthermore, the signal obtained by inverting the sign of the output of the 12th subtractor 39 is used as the DC component command value of the secondary AC current of the k-th unit and is used by the 4th subtractor 10.

The third subtractor 9 subtracts the output of the third low-pass filter LPF3 from the output of the twelfth subtractor 39. The fourth subtractor 10 subtracts the output of the fourth low-pass filter LPF4 from the value obtained by inverting the sign of the output of the twelfth subtractor 39.

Embodiment 3 intentionally increases losses by changing the pulse width to reduce the balance deviation of the capacitor voltage under no load. However, there is a limit to the pulse width that can be changed, and it cannot deal with capacitor voltage balance disturbances that exceed this limit, as described above.

This fourth embodiment describes a method for reducing the balance deviation of the capacitor voltage even when a larger balance disturbance occurs under no-load conditions.

In Embodiment 3, the operation to widen the narrower pulse width is performed. However, if the amount of manipulation exceeds the limiter, the operation to narrow the wider pulse width is performed. If this also exceeds the limiter, no operation is performed for that amount.

In this embodiment 4, the operation to narrow the wider pulse width also detects the portion exceeding the limiter, and the excess portion is used as the command value for the DC component of the primary AC current detection value i1k and the secondary AC current detection value i2k of the k-th unit.

By superimposing a DC component onto the primary AC current detection value i1k and the secondary AC current detection value i2k of the k-th unit, a larger loss can be generated, allowing the capacitor to discharge.

The DC component command values to be applied were set in opposite directions for the primary AC current detection value i1k and the secondary AC current detection value i2k of the k-th unit. In this embodiment 4, the first multiplier 8 multiplies the primary AC current detection value i1k by 1/n, or the secondary AC current detection value i2k by n. This causes the DC components of the magnetic flux generated by both the primary and secondary currents in the iron core inside the high-frequency transformer to cancel each other out, thus preventing magnetic saturation of the iron core.

In this embodiment 4, for units other than the one with the smallest total energy Ek stored in the primary and secondary DC capacitors, the primary pulse width command value W1k and the secondary pulse width command value W2k are corrected so that the DC component of the current output by that unit increases. The output values are then set as follows: primary positive pulse width command value W1kp, primary negative pulse width command value W1km, secondary positive pulse width command value W2kp, and secondary negative pulse width command value W2km.

Furthermore, for units other than the minimum DC capacitor voltage downstream of power transmission, the primary pulse width command value W1k and the secondary pulse width command value W2k may be corrected so that the DC component of the current output by the unit increases, and the output values may be W1kp for the positive primary pulse width command value, W1km for the negative primary pulse width command value, W2kp for the positive secondary pulse width command value, and W2km for the negative secondary pulse width command value.

In this embodiment 4, the priority for increasing reactive power on the AC side as a means of generating loss was given higher, while the priority for DC superposition on the AC current was given lower. The reason for this is explained below. Increasing reactive power generates a ripple on the DC side at twice the fundamental frequency. In the case of DC superposition, a ripple with a frequency equal to the fundamental frequency is generated. Low ripple frequencies lead to problems such as a larger voltage ripple amplitude even with the same capacitor capacitance, and the need for a larger filter to remove it. Therefore, the means that generate high ripple frequencies were prioritized.

Significant balance disturbances requiring the application of this embodiment 4 include abnormalities in transformers and capacitors, discharge due to foreign matter contamination within the unit, and insulation breakdown of the unit. Therefore, it is conceivable to periodically check the DC component command values of the primary AC current detection value i1k and the secondary AC current detection value i2k of the k-th unit during maintenance. If a unit with a large accumulated value is found, it can be assumed that deterioration or abnormality has occurred in other units, and the unit with the smallest accumulated value can be replaced to prevent failure.

According to this embodiment 4, even when a larger balance disturbance occurs under the condition of zero transmission power, the voltage balance of both the primary and secondary DC capacitors can be maintained, allowing operation to continue.

Furthermore, while ripple with a frequency equal to the fundamental frequency occurs on the DC side, this can be minimized.

Furthermore, the present invention can also be applied to a configuration where, as shown in Non-Patent Document 1, one end of multiple DAB converters is connected in series, and the other end is a combination of series and parallel connections. In this case, multiple unit units, each with one end connected in series and the other end in parallel, are considered to be connected in series, and existing control methods are applied to balance the series capacitor voltages within each unit unit. The present invention is applied to balance the capacitor voltages of each unit unit.

Although the present invention has been described in detail only with respect to the specific examples provided, it will be obvious to those skilled in the art that a wide variety of modifications and alterations are possible within the scope of the technical concept of the present invention, and it is natural that such modifications and alterations fall within the scope of the claims.

DC1, DC2… Primary DC power supply, Secondary DC power supply C1, C2… Primary DC capacitor, Secondary DC capacitor L1-L4… Reactor Tr… Transformer LPF1-LPF4… First to fourth low-pass filters 1, 2… First and second subtractors 3… First comparator 4… Turns ratio calculator SW1-SW5… First to fifth switches 5… First amplifier 6, 7… First and second adders

Claims (7)

A DAB-type bidirectional isolated DC/DC converter comprising a primary DC power supply, a secondary DC power supply, and first to m (m: an integer of 2 or more) units connected between the primary DC power supply and the secondary DC power supply,
The primary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the primary DC power supply,
The secondary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the secondary DC power supply,
The first inverters of the first unit to the m unit are connected to the primary DC capacitors of the first unit to the m unit, respectively.
The second inverters of the first unit to the m unit are connected to the secondary DC capacitors of the first unit to the m unit, respectively.
The transformers of the first unit to the m unit are configured such that the primary windings of the first inverters of the first unit to the m unit are connected to the AC side of each unit, and the secondary windings of the second inverters of the first unit to the m unit are connected to the AC side of each unit,
A control unit that generates gate signals for the first and second inverters,
Equipped with,
The control unit,
A DAB-type bidirectional isolated DC/DC converter characterized in that the operating power factor of a unit is reduced in any unit other than the unit with the smallest total energy stored in the primary DC capacitor and the secondary DC capacitor. A DAB-type bidirectional isolated DC/DC converter comprising a primary DC power supply, a secondary DC power supply, and first to m (m: an integer of 2 or more) units connected between the primary DC power supply and the secondary DC power supply,
The primary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the primary DC power supply,
The secondary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the secondary DC power supply,
The first inverters of the first unit to the m unit are connected to the primary DC capacitors of the first unit to the m unit, respectively.
The second inverters of the first unit to the m unit are connected to the secondary DC capacitors of the first unit to the m unit, respectively.
The transformers of the first unit to the m unit are configured such that the primary windings of the first inverters of the first unit to the m unit are connected to the AC side of each unit, and the secondary windings of the second inverters of the first unit to the m unit are connected to the AC side of each unit,
A control unit that generates gate signals for the first and second inverters,
Equipped with,
The control unit,
A DAB-type bidirectional isolated DC/DC converter characterized by reducing the operating power factor of a unit in which the DC capacitor voltage on the downstream side of power transmission is not the minimum of all units. The control unit,
A ninth subtractor calculates a second energy deviation, which is the difference between the total energy stored in the primary DC capacitor and the secondary DC capacitor of the k-th unit and the minimum total energy stored in the primary DC capacitor and the secondary DC capacitor of all units.
A third amplifier that amplifies the second energy deviation,
A seventh adder adds the output of the third amplifier to the smaller of the primary pulse width command value of the kth unit and the secondary pulse width command value of the kth unit.
A first limiter that limits the output of the seventh adder to within an upper and lower limit,
A tenth subtractor calculates the difference between the input value and the output value of the first limiter,
An eleventh subtractor subtracts the difference between the input value and output value of the first limiter from the larger of the primary pulse width command value of the kth unit and the secondary pulse width command value of the kth unit,
A second limiter that limits the output of the 11th subtractor to within an upper and lower limit,
A fourth switch that outputs the output of the second limiter if the primary pulse width command value of the k-th unit is greater than the secondary pulse width command value of the k-th unit, and outputs the output of the first limiter otherwise,
A fifth switch outputs the output of the first limiter when the primary pulse width command value of the k-th unit is greater than the secondary pulse width command value of the k-th unit, and outputs the output of the second limiter otherwise.
When the turns ratio of the transformer is primary winding:secondary winding = 1:n, a first multiplier multiplies the primary AC current detection value of the kth unit by 1/n, or multiplies the secondary AC current detection value of the kth unit by n.
A third adder adds the amplified DC component of the AC current detection value on the primary side of the k-th unit to the output of the fourth switch and outputs it as the positive pulse width command value on the primary side of the k-th unit.
A fifth subtractor subtracts the amplified DC component of the AC current detection value on the primary side of the k-th unit from the output of the fourth switch and outputs it as the negative pulse width command value on the primary side of the k-th unit.
A fourth adder adds the amplified DC component of the detected AC current value on the secondary side of the k-th unit to the output of the fifth switch and outputs it as the positive pulse width command value on the secondary side of the k-th unit.
A sixth subtractor subtracts the amplified DC component of the detected AC current on the secondary side of the k-th unit from the output of the fifth switch and outputs it as the negative pulse width command value on the secondary side of the k-th unit.
The DAB type bidirectional isolated DC/DC converter according to claim 1, characterized by comprising the above. The control unit,
The DAB type bidirectional isolated DC/DC converter according to claim 1, characterized in that, for units other than the one with the smallest total energy stored in the primary DC capacitor and the secondary DC capacitor, the DC component of the current output by that unit is increased. The control unit,
The DAB type bidirectional isolated DC/DC converter according to claim 2, characterized in that the DC component of the current output by a unit is increased in units other than the unit with the smallest DC capacitor voltage downstream of the power transmission. Primary DC power supply,
Secondary DC power supply and
A first unit to the mth (m: an integer of 2 or more) unit connected between the primary DC power supply and the secondary DC power supply,
The primary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the primary DC power supply,
The secondary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the secondary DC power supply,
The first inverters of the first unit to the m unit are connected to the primary DC capacitors of the first unit to the m unit, respectively.
The second inverters of the first unit to the m unit are connected to the secondary DC capacitors of the first unit to the m unit, respectively.
The transformers of the first unit to the m unit are configured such that the primary windings of the first inverters of the first unit to the m unit are connected to the AC side of each unit, and the secondary windings of the second inverters of the first unit to the m unit are connected to the AC side of each unit,
A control unit that generates gate signals for the first and second inverters,
A control method for a DAB-type bidirectional isolated DC/DC converter, comprising:
The control unit,
A control method for a DAB-type bidirectional isolated DC/DC converter, characterized in that the operating power factor of a unit is reduced for any unit other than the unit with the smallest total energy stored in the primary DC capacitor and the secondary DC capacitor. Primary DC power supply,
Secondary DC power supply and
A first unit to the mth (m: an integer of 2 or more) unit connected between the primary DC power supply and the secondary DC power supply,
The primary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the primary DC power supply,
The secondary DC capacitors of the first unit to the m unit are connected in series between the positive and negative terminals of the secondary DC power supply,
The first inverters of the first unit to the m unit are connected to the primary DC capacitors of the first unit to the m unit, respectively.
The second inverters of the first unit to the m unit are connected to the secondary DC capacitors of the first unit to the m unit, respectively.
The transformers of the first unit to the m unit are configured such that the primary windings of the first inverters of the first unit to the m unit are connected to the AC side of each unit, and the secondary windings of the second inverters of the first unit to the m unit are connected to the AC side of each unit,
A control unit that generates gate signals for the first and second inverters,
A control method for a DAB-type bidirectional isolated DC/DC converter, comprising:
The control unit,
A control method for a DAB-type bidirectional isolated DC/DC converter, characterized in that the operating power factor of a unit is reduced in any unit other than the unit with the lowest DC capacitor voltage downstream of the power transmission.