JPS5816810B2 - AD conversion device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an AD converter that changes the level of an input analog signal using a range switching circuit, supplies it to an integral AD converter, and converts it into a digital signal, and particularly, an AD converter that automatically switches the range. Regarding equipment.

In the conventional AD converter of this kind, as shown in FIG.
The level of the signal is changed at , and the signal is supplied to the integral type AD converter 13 .

In the integrating type AD converter 13, the input analog signal is integrated by the integrating circuit 14 for a certain period of time T (hereinafter referred to as the first integration), and then the reference voltage having the opposite polarity to the input analog signal is integrated by the integrating circuit 14 (hereinafter referred to as the first integration). (referred to as integration), and the comparator 15 detects when the integrated output exceeds an initial constant level l.

The integration operation is stopped based on the detection output, the length of the second integration period is taken out as a digital signal, and the input analog signal is converted into a digital signal.

In this case, if the level of the input analog signal is higher than the convertible full scale, the range switching circuit 12 lowers the level, and conversely, if the level is lower than the full scale of 1710, the control circuit 16 increases the analog signal level. It is controlled by

For example, as shown in FIG.
The integration circuit 14 integrates the first integrator in a certain direction, and at that time, in this example, it exceeds the full scale level Ef and is saturated, and then the second integration is performed and the integration circuit 14 integrates the first integrator in a certain direction. At the time t2 when the second integration is completed and the converted digital signal is obtained, it is determined whether the conversion result is greater than or equal to the full scale.

As in this example, when it is determined that the output of the range switching circuit 12 is higher than the full scale level Ef, the range switching circuit 12 is controlled to lower the input signal to a certain level, and at the next time t3, the same conversion operation is performed again. and the conversion end point t
4 is examined in the same manner.

In this case as well, it is determined that the signal is larger than full scale, and the input signal level is further lowered by the range switching circuit 12 again.
At the next time point t5, a digital conversion operation is performed in the same way,
The conversion result is known at t6.

Even in this state, the input signal is at full scale level Bf
It is determined that the input signal level is larger than that, and the input signal level is further lowered, and the result of the conversion operation from the next time point t7 is obtained at time point t8.

At this time t8, in this example, it is detected that the output of the range switching circuit 12 has become below the full scale level Ef,
The digital value of the input analog signal is obtained from the set range in the range switching circuit 12 at that time and the converted digital signal.

In this way, in conventional AD converters, the operation for automatically setting the range switching circuit is to finish the conversion operation for one sample value of the input signal, and then determine the optimal setting range of the range switching circuit based on the digital value. Since it is determined whether the range is present or not, it takes time until the range switching circuit 12 is set to the optimum range.

Therefore, it was unsuitable for high-speed AD conversion.

In a conventional AD conversion device, the output of the range switching circuit 12 is supplied to an over comparator 17 and an under comparator 18, respectively, as shown in FIG. It is determined whether or not is larger than the scale level Ef, and if it is larger, the judgment result is provided to the control circuit 16, and the control circuit 16 controls the range switching circuit 12 to lower the input signal level.

Further, the under comparator 18 judges whether the input is smaller than a certain level, for example, 1/10 of the full scale level Ef, and if it is smaller, the result is given to the control circuit 16, and the control circuit 16 switches the range. For example, when the over comparator 11 determines that the output of the range switching circuit 12, which operates to increase the input analog signal level by controlling the circuit 12, is higher than the full scale level Bf as shown in FIG. 4A, , 51 pulses P1 are given to the control circuit 16 as shown in FIG.

The output level of range switching circuit 12 is reduced.

Such a comparison operation is performed several times, in this example 4
The output of the range switching circuit 12 falls below the full scale level Ef by the fourth pulse P1 after n times.

In this state, the integration operation for the integrator 13 is performed as shown in FIG. 4C.

This AD converter takes less time to set the range switching circuit 12 to the optimum range than the one shown in FIG.
There were drawbacks that made it especially necessary.

An object of the present invention is to provide an AD converter which has a simple circuit configuration, can quickly set an optimum range for a range switching circuit, and has a high conversion speed.

According to the present invention, in the middle of the first integral, it is determined whether the output of the range switching circuit is within the optimum range from the magnitude of the output level of the first integral, especially at a relatively high timing. .

If the result is outside the optimal range, the range switching circuit is controlled to change the input signal level and output it, and at the same time, the integral conversion operation is performed from the beginning, and if the judgment result is within the optimal range, the input signal level is changed and output. Continue the integral operation.

In this way, the circuit configuration is almost the same as the conventional one without providing any over comparator or under comparator, and in addition, it is possible to check whether or not it is within the optimal range in the middle of the first integration. In order to continue the integration operation as it is, faster conversion is performed than when a new AD conversion operation is performed after determining whether or not it is within the optimum range.

FIG. 5 shows an embodiment of the AD conversion device according to the present invention,
The same reference numerals are given to the parts corresponding to those in FIG. 1, and the circuits of each part are shown in more detail.

That is, the range switching circuit 121 includes, for example, an operational amplifier 21, and its non-inverting input terminal is connected to the input terminal 11 through the switch S1.

The connection point between switch S1 and input terminal 11 is voltage dividing resistor 2.
2 to ground, and its voltage dividing point is connected to the non-inverting input terminal of the operational amplifier 21 through the switch S2.

The inverting input terminal and output terminal of the amplifier 21 are connected to the switch S3.
The output terminal is grounded through the voltage dividing resistor 23, and the voltage dividing point is connected to the inverting input terminal through the switch S4.

If the switch S1 is on, the input analog signal is supplied as is to the amplifier 21, and the input analog signal is passed through the switch S2 by turning off the switch S1 and turning on S2.
The signal is thus attenuated and supplied to the amplifier 21.

When the switch S4 is turned on, the amplified output is divided and fed back, and the gain is reduced accordingly, but when the switch S3 is turned on, the amplified output is fed back as is, and the amplified gain is further reduced.

In the integrating circuit 14, the output side of the range switching circuit 12 is connected to a non-inverting input terminal of an operational amplifier 25 through a switch S6 and an integrating resistor 24.

The inverting input terminal of the operational amplifier 25 is grounded, and the integrating capacitor 26 is connected between the output terminal and the non-inverting input terminal.

Its output terminal is also grounded through switch S5.

The positive reference voltage terminal 29 and the negative reference voltage terminal 31 of the reference voltage generation circuit 28 are connected to the switch S7. Through S8, it is further connected to an arithmetic scaler 25 through a resistor 24.

The output of the operational amplifier 25, that is, the output of the integrator 14, is supplied to one input side of the comparator 15, and the other input side of the n1 comparator 15 is grounded through the resistor 32.

In this embodiment, the voltage generated by the reference voltage generating circuit 28 is
Reference comparison levels for positive and force are supplied to comparator 15I through selection circuit 33 and further through switch S.

In this embodiment, the control circuit 16 uses a so-called microcomputer and is executed under program control, and controls the switches 81-S.

Next, the operation of FIG. 5 will be explained with reference to FIG.

First, switch S, , S4. S, is turned on at time t, and all other switches are turned off.

Therefore, the output A of the range switching circuit 12 is integrated by the integrator 14, and the integrated output shown in FIG. 6C is obtained.

This integral output is compared with the cello level by the comparator 15, and in this example, the integral output is positive and the comparator 15 is at a high level as shown in the sixth diagram.

When time T has elapsed since time t1, the control circuit 16 determines whether the output of the comparator 15 is at a high level or a low level, and if it is at a high level, determines that the input analog signal is positive. , the input analog signal is determined to be negative if it is at a low level.

Based on this determination result, the reference voltage generating circuit 28 switches the switch S7. It is known whether to turn on or off the signal at S8, and the comparison level selection circuit 33 selects between +Vc and -Vc of the comparison level obtained from the reference voltage generation circuit.

+Vc is selected when the input analog signal is positive.

The selected +Vc is supplied to the comparator 15 by turning on the switch S9.

The control circuit 16 determines the comparison result of the integrated output with the comparison level selected by the selection circuit 33 when a time T2 has elapsed from the time t1.

Therefore, switch S9 is turned on before time T2 has elapsed.

As a result of comparing the comparison level +Vc and the integral output C, if the integral output is large, the comparison output becomes a high level.

When this is determined by the control circuit 16, the range switching circuit 12 is controlled.

Before that, when it is determined that the range is not set to the optimum range, the switch S6 is turned off and the switch S5 is turned on to stop the integration operation of the integrator 14 and return the integrated voltage to the initial state, and then at time t2 The switch S3 is turned on and the switch S4 is turned off to lower the level of the input analog signal, and as before, the polarity of the output of the integrating circuit is determined, the comparison level Vc is determined, and the comparison operation with Vc is performed. .

After determining that this result is still not in the optimum range and returning the integrator 14 to its initial state, at time t3 the switch S1 is turned off and the switch S2 is turned on.
Furthermore, switch S3. S5 is off, switch S4. When S6 is turned on, the level of the n1 human input signal is further lowered, an integral operation is performed on that signal, and the integral output is compared with the comparison level Vc.

In this example, it is determined that the level is not yet within the optimum level, and at time t4, switch S4 is turned off and switch S
3 is turned on, and the integration operation is started again from n.

At this time, the output level of the range switching circuit 12 falls below the full scale level Ef as shown in FIG. .

As a result, the control circuit 16 determines that the output of the range switching circuit is smaller than the full scale level Fe.

Therefore, the operation of the first integration continues as it is, and the switch S9 remains on.

The integral operation continues and the integral output C reaches the comparison reference level Vc.
At time t, it becomes a dog.

The output of the comparator 15 becomes high level.

After a time T3 has elapsed from the start time t4 of the first integration, it is determined whether the output level of the comparator 15 is at a high level.

If the output of the comparator 15 at that time is high level, it is determined that the input analog signal is lower than the lowest comparison level.If the output of the comparator 15 is low level, it is determined that it is smaller than the lowest comparison level, and the input analog signal is determined to be lower than the lowest comparison level. When the switch 14 is returned to its initial state, it acts to increase the gain for the range switching circuit 121.

If the output of the comparator 15 is at a high level as determined at time T3, it is determined that the range switching circuit 12 has been set to the optimum level for the input analog signal, and the first integration is continued.

The subsequent operation is the same as the conventional one, that is, the first integration is performed from time t4 for the period T, the reference voltage from the reference voltage generation circuit 28 is integrated, and the second integration is started. The period T2 for determining whether or not exceeds the full scale level is the comparison reference level Vc, the resistance value R of the integrating resistor 24, and the integrating capacitor 2.
Range voltage Vu that can be raised by switching the capacity C lunge of 6
cXRXC T2=□ seconds up for p.

Similarly, if the range voltage lowered by range switching in the range switching circuit 12 is do, the period T3 for determining whether it is below the lowest comparison level is cXRXC T3=□ seconds vd.

selected.

It is easy to understand whether the integrator input is within the optimum range by determining the level of the integrator output Vc, but for example, as shown in FIG. The integrated output for the input of Ef is shown by a line 35, and the output when the reference voltage is integrated in the second integration period is shown by a line 36.

The integral of the input voltage 1.2 times with respect to the full-scale level Ef becomes as shown by the line 37, which has a steeper slope than the line 35, while the input level is very low (the full-scale level E
The first integral output for an input of 1/10 of f is as shown by line 38.

If these rising parts are enlarged and shown in FIG. 8, the line 35 is below Vc, but the line 37 is below Vc at the time T2 has elapsed from the start of the first integral.
Therefore, it can be determined that the input exceeds the full scale level and is overrange, for example, 120% or more of the full scale.

Furthermore, when T3 has elapsed from the start of integration, it is determined that the integrated output is above Vc and above the underrange, that is, above the full scale, for example, 10 inches.
Below, it is determined that the range is underrange.

In FIG. 8, the optimum range is between lines 37 and 38.

In this way, by looking at the output voltage of the integrator, it is determined whether the output of the range switching circuit is within the optimum range.

In FIG. 5, the control circuit 16 is operated under program control, but it can also be configured as a pure circuit using a so-called timing circuit.

In this case, as shown in FIG. 9, the timing generation circuit 39 in the control circuit is used to generate the timing T1. T2.
Take out T3 and game the timing) 44, 45.
46, the output of the comparator 15 at that time is taken out, a circuit 47 determines whether the output is high level or low level based on the output of the gate 44, and the selection circuit 33 is controlled by the resulting output.

If the output of the gate 45 is at a high level, it is applied to the reset terminal of each circuit to reset it and change the range of the range switching circuit 12 by 1, causing the range control counter to step so that the output becomes a low level. control the speed.

Also, when the output of the gate 46 is at a high level, it is applied to all reset terminals to set the reset state, and at the same time, the range control counter of the range switching circuit is changed by 1, and the output is controlled to be at a high level. .

As described above, in the AD converter according to the present invention, it is determined from the integral output during the first integration whether the range switching circuit is set to the optimum range, and if the range switching circuit is not set to the optimum range, The range switching circuit is controlled and the first integration is newly started again.

When the optimum range is set, the first integration is continued as it is, so AD conversion can be performed quickly.

For example, the first integration time is 100 mi! If the second integration time is 7 seconds and the input is at the full scale level, and the second integration time is 100 milliseconds, then one AD conversion operation will take 100 milliseconds to 200, - IJ seconds when the input is in the optimal range. is necessary.

According to the conventional device shown in FIG. 1, it takes 100 to 200 milliseconds to change one range, and for example, when changing five ranges, it takes at least 500 milliseconds.
It takes milliseconds to 1 second.

On the other hand, in this invention, when T2 is 100 microseconds and T3 is 1.2 milliseconds, the time required to switch ranges is calculated by T3, switch switching time, and time required for stabilizing the operation of the range switching circuit. This is the sum of several hundred microseconds.

Therefore, the time required to switch between the five ranges is completed within 10 milliseconds.

It will be appreciated that the device according to the invention is significantly faster than the prior art shown in FIG.

Furthermore, although the configuration shown in FIG. 3 requires two comparison circuits, as can be seen from the example in FIG. Yes, all you need to do is slightly change the control circuit program.

Furthermore, the circuit configuration is not particularly complicated since the existing timing circuit is used as described with reference to FIG.

As shown in FIG. 10, the output of the integrator 14 is transferred to the absolute value circuit 4
The control circuit 16 controls the switching circuit 51 to switch between the output of the integrator 14 and the output of the absolute value circuit 49 and supply the output to the comparator 15.

In this way, during the period of determining whether or not the optimum range is present and setting the range, the integrator 14 is operated by the absolute value circuit 49.
By controlling the signal to be supplied to the comparator 15 through the signal, the polarity determination operation at T1 described above can be omitted.

When the optimum range is determined, the switching circuit 51 is controlled to directly connect the integrator 14 to the comparator 15.

Furthermore, as shown in FIG.
In addition to 5, a comparator 52.53 is also supplied, and the comparator 52.53
are given different comparison voltages from a comparison level generator 54, and these comparators 52 are applied at the same timing.
．． 53, a comparison is made with the integral output, and at that time the comparator 53
The comparator 53 determines whether the input is over-range, and the comparator 53 determines whether the input is under-range.

In this way, range judgment can be made at the same timing after a certain period of time from the start of the first integration period, and since it is made in the middle of the first integration, the judgment can be made as shown in Fig. 3. If the integral operation is performed later, faster speed conversion can be achieved.

[BRIEF DESCRIPTION OF THE DRAWINGS] Fig. 1 is a block diagram showing a conventional AD converter, Fig. 2 is a waveform diagram explaining its operation, and Fig. 3 is a conventional A/D converter.
A block diagram showing another example of the D conversion device, FIG. 4 is a waveform diagram for explaining its operation, and FIG. 5 is an AD conversion device according to the present invention.
A block diagram showing an example of a conversion device, FIG. 6 is a waveform diagram for explaining its operation, and FIG. 7 shows changes in the integral output within the optimal range of integral operation of AD conversion, over range, and under range. 8 is an enlarged view of the rising portion of FIG. 7, FIG. 9 is a block diagram showing a part of the circuit configuration of the control circuit, and FIGS. 10 and 11 are each an AD according to the present invention. FIG. 3 is a block diagram showing another example of a conversion device. 11: input terminal, 12: range switching circuit, 13: integral type AD converter, 14: integrator, 15: comparator, 16 two control circuits, 28: reference voltage generation circuit, 33: reference level selection circuit.

Claims (1)

[Claims] 1. In an AD converter that changes the level of a human-powered analog signal using a range switching circuit and supplies the output to an integral type AD converter to convert it into a digital signal, in the middle of the first integration in the conversion operation of the AD converter, determining means for determining whether the integrated voltage of the AD converter reaches a reference level and determining whether or not the input analog signal level is within the optimal range; and when the determination is not within the optimal range; is an AD converter comprising means for switching the range of the range switching circuit and bringing the AD converter into an initial state, and means for continuing the conversion operation of the AD converter when the judgment is within the optimum range. Device.