JPS5822898B2 - Hand tie souchi - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a device for obtaining one-dimensional or two-dimensional optical information as an electrical signal via a semiconductor device.

Conventionally, as a device for converting optical information into an electrical signal, for example, a device with a self-scanning function (5elf-8
canned Image 5 sensor IEEE
ED-18A611 (1971), PAULK WE
There is a device that converts optical information into an electrical signal and reads it out using a combination of a photosensor and a charge transfer device (BBD) or CCD (such as IMER).

Examples of optical sensors include photodiodes and phototransistors.

There is also a method in which the charge transfer element is directly irradiated with light to perform the photoelectric conversion function and the readout function in the same element, but this method causes large optical distortion because the transfer element is exposed to light even during charge transfer. This is not done much now.

The present invention relates to the former device, which is composed of a part of the optical sensor and a charge transfer part, and allows the exchange of photoelectric conversion signals between the part of the photosensor and the charge transfer part to be performed simply by simply charging the charge without adding a new control line. By applying a control □ pulse to the clock signal line for transfer, it is possible to read the photoelectric conversion signal into the charge transfer stage.

Since this effect does not require a special read control line, it is possible to increase the density of sensors when constructing a two-dimensional matrix, and the performance as a two-dimensional optical information reading device is significantly improved.

FIG. 1 shows an example of the configuration of a conventional optical sensor and shows its circuits.

In FIG. 1, Ql is a transistor for setting the photodiode D to a constant potential for a certain period of time.

Q2 is a transistor for reading the photoelectric conversion signal of the diode D into an arbitrary stage Tr(n) of the charge transfer element array.

Tr(nL Tr (n+1)) is a transistor forming a charge transfer circuit.

In this circuit/circuit, clock control lines ψ1 . In addition to ψ2, a control line ψ8 for setting the diode to a constant potential and a read control line ψ□ for reading the photoelectric conversion signal into the potential transfer element array in parallel are required, and when configuring a matrix (two-dimensional sensor), This control line becomes an obstacle to increasing the density of sensors.

Figure 2 shows Japanese Patent Application No. 49-101083 (Japanese Patent Application No. 51-284) filed by the present applicant, which partially improved the above-mentioned disadvantages.
This is an example shown in Publication No. 27).

I will omit the details of the operation here, but the main point is
This is an example in which the control line of the read gate Q2 in the figure is shared with the clock line, thereby increasing the number of control lines to three lines in total, making it possible to increase the density of the two-dimensional arrangement of sensors.

The present invention further aims to reduce the number of control lines under specific driving conditions, has the above-mentioned functions as is, and uses the control lines as clock control lines ψ1 . ψ2
The purpose of the present invention is to provide a self-scanning solid-state imaging device that can be made to have a high density.

Here, the reason why a large number of control lines becomes an obstacle to high density will be briefly explained with reference to FIG.

Figure 3 shows how many circuits in Figure 1 are placed under a semiconductor.

This is an example of the arrangement when

In the figure, a control line ψ8 for setting the diode D to a constant potential for a certain period of time and a read control line ψ□ for reading the diode's power transformation conversion signal are placed on the Y axis.

Also, the clock control line for signal charge transfer is X.

It's on the axis.

1 in the figure is a preset gate consisting of transistor Q1;
2 means a read gate made up of a transistor Q2, and 3 means a transfer gate made up of a charge transfer transistor Tr(n).

Here, ψ8. Regarding the ψ□ line, it is a diode.

Since D needs to be irradiated with light, these control lines need to be routed avoiding the top of the diode.

The reason for this is that the wiring causes light shielding. Therefore, these control lines occupy extra wiring sparse in areas other than the active area, which becomes an obstacle to high density when configuring a two-dimensional array.

FIG. 4 shows an example of the configuration of a photosensor made of a MOS transistor circuit according to an embodiment of the present invention.

Ql is a transistor for setting the photodiode D to a constant potential for a certain period of time, Q2 is a transistor for reading the photoelectric conversion signal of the phototransistor into the charge transfer stage, and Tr(n).

Tr(n+1) is a transistor constituting an example of a charge transfer element as described above.

Examples of charge transfer elements 1 to Ranjisku Tr
(n+1) are clock control lines ψ1 . . . for applying two-phase clock pulses for charge transfer. ψ
2 is supplied.

In the sensor of this embodiment, one line ψ1 of the two-phase clock control lines is commonly connected to the control gate of the transistor Q2 for reading the photoelectric conversion signal of the photodiode, and the other line ψ2 of the two-phase clock control lines is commonly connected to the control gate of the transistor Q1 for setting the photodiode to a constant potential for a certain period of time.

According to this sensor, the number of control lines can be reduced to two, the clock control lines ψ□ and ψ2 for charge transfer.

The operation of the optical sensor having the circuit configuration shown in FIG. 4 will be explained below.

FIG. 5 shows a cross-sectional configuration of essential parts of the optical sensor shown in FIG. 4.

In the figure, 10 is a P-type semiconductor substrate, and 20 is an n-shaded area of the substrate 1.
A photodiode D configured between 0 and 0 is shown.

30 is the drain region of the transistor Q1 for setting the diode to a constant potential, 40 is the drain region of the transistor Q2 for reading the photoelectric conversion signal of the photodiode D, and at the same time, the transistor Tr(n ).

50 is an oxide film 60, 70 is a transistor Q1. This is the gate of Q2.

Now, when a set pulse ψ8 is applied to the gate controller 0, a conductive channel is formed on the gate, and the diode D is at a constant potential corresponding to the set pulse ψ8 (usually Vψs v
, , where VT is held at the threshold voltage of a MOS transistor.

When ψ8 is cut off, diode D becomes electrically floating.

When the diode is irradiated with light for a certain period of time in this state, a photocurrent flows between the n-shaded region 20 and the semiconductor substrate 10, and as a result, the diode potential decreases by Δ■.

This value is proportional to the amount of light.

In this state, when a read pulse ψ□ is applied to the gate 70, the drain region 40 of the read transistor is exposed to the oxide film 50.
Since it is capacitively coupled to the gate γ0 via the read pulse ψ□, it is pulled up to a high positive potential.

As a result, current flows into the diode from the drain region 40.

The amount of charge flowing into the substrate is proportional to the total amount of charge flowing into the substrate due to light irradiation for a certain period of time.

As described above, the photoelectric conversion signal can be read into any stage of the charge transfer element array as the total amount of charge flowing out to the diode due to the application of ψ□.

FIG. 6 is an example of drive pulses for the circuit configuration shown in FIG. 4.

Figure 6 1. II is the control line ψ1. The pulse signal waveform applied to ψ2 is shown, and ■ indicates the voltage waveform of the diode D.

The diode set pulse ψ8 mentioned above is applied to the control line of ψ1 at a voltage higher than the voltage of the timing transfer pulses 100 and 200 shown in the figure.

The diode is set to V□ at ψ8, and becomes electrically floating for a time TW after ψ8 is cut off.

During this period, the potential of the diode receiving light irradiation decreases by Δ■. In this state, a read pulse ψ□ is applied to the control line of ψ1.

As a result, for the reason mentioned above, a photoelectric conversion signal of ΔV is read into the middle stage of the charge transfer element, and at this time, the diode potential becomes a value close to the masset potential ■□.

After being read, the diode is set correctly again to ■□, and the read signal is ψ1. It is read out as a serial signal with clock pulses 100 and 200 for charge transfer applied to ψ2.

In this example, the maximum allowable photoelectric conversion signal Δ■ is
is given by the Zoset pulse voltage ψ8 and the voltage difference between the read pulse ψ□ and the voltage of the transfer lock pulses 100 and 200.

According to the circuit configuration according to the present invention, a high-density two-dimensional solid-state imaging device having a self-scanning function can be realized by reducing the number of control lines.

Furthermore, according to the present invention, it is possible to arbitrarily set the application of different pulse voltages to the charge transfer lock control line for the diode set voltage and read voltage, so there is freedom in device voltage conditions when receiving optical signals. degree.

[Brief explanation of the drawing]

Figure 1 is a circuit configuration diagram of a conventional optical sensor, Figure 2 is a circuit configuration diagram of an optical sensor proposed by the applicant, Figure 3 is a planar layout configuration diagram of a conventional optical sensor, and Figure 4 is a diagram of the present invention. FIG. 5 is a sectional view of the main structure of the optical sensor of FIG. 4, and FIG. 6 is a timing diagram of one drive bus of the optical sensor of FIG. 4. D...Photodiode, Ql...Transistor for setting the diode D to a constant potential for a certain period of time, Q2...Transistor for reading the photoelectric conversion signal into the charge transfer stage, Tr '(n), Tr (
n+1)...Transistors forming the charge transfer element array, ψ1. ψ2...Clock control line, ψ1...Read pulse, Q8...Set pulse.

Claims (1)

[Claims] 1 A charge transfer element array consisting of a plurality of photo-sensing elements and a plurality of charge transfer elements, and a first charge transfer element array for reading photoelectric conversion signals of the photo-sensing elements into any stage of the charge transfer element array in parallel.
a second gate circuit that holds the photo-sensing element at a constant potential for a certain period of time, a first clock that drives the charge transfer element array, and a first clock that drives the charge transfer element array; a second clock for driving a second gate circuit; and a two-phase or multi-phase line to which a clock signal consisting of a second clock is applied, and one of the lines is used to control the first gate circuit. one of the lines is used as a control line of the second gate circuit, and the photoelectric conversion signal of the photosensitive element is transmitted to the first gate circuit driven by the second clock.
A semiconductor characterized in that the photoelectric conversion signal is read in parallel to the charge transfer element array through the gate circuit of the semiconductor device, and then the photoelectric conversion signal is read out as a series of serial signals via the charge transfer element array using the first clock. Device.