JPS5847077B2 - banknote identification device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a banknote identification device that identifies the type of banknote by determining the frequency of a pattern detection signal obtained from the banknote.

Conventionally, the pattern of a banknote, such as vertical stripes, is detected optically or magnetically and passed through a bandpass filter, and it is determined whether or not the detected signal has a predetermined vertical stripe based on whether or not it has a predetermined frequency. There are several banknote recognition devices.

However, since such conventional identification devices use a bandpass filter, there is a range of frequencies that can be detected, and it is not possible to accurately detect only a specific frequency. It has the disadvantage that it cannot be discriminated and the identification accuracy is extremely low.

In addition, since it is an essential condition that the conveyance speed of banknotes be constant, it is impossible to respond to changes in the conveyance speed at all, and it is not practical.

SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a banknote identification device that does not have these drawbacks.

This invention will be explained below.

The present invention relates to a banknote identification device, and as shown in FIG.
A pattern detection device 10 for detecting a pattern on a banknote, and a time-lapse signal generation device 20 that generates a time-lapse signal of a constant width after a predetermined time period each time a pattern detection signal obtained from the pattern detection device 10 is input. , and a gate device 30 that detects that the next detection signal is obtained when the elapsed signal is being generated, and the banknote is identified by determining the frequency of the pattern of the banknote from the output content of the gate device 30. This is what I did to get it.

Here, the pattern detection device 10 includes a magnetic head 11 that scans the surface of a banknote being conveyed, and a waveform shaping circuit 12 that amplifies and shapes a detection signal from the magnetic head 11.
and a one-shot circuit 13 that outputs, as a pattern detection signal PD, a pulse signal having a pulse width sufficiently shorter than the width of the output signal WF at the rise (or fall) of the output signal WF from the waveform shaping circuit 12; The delay circuit 14 momentarily delays and outputs the pattern detection signal PD.

The elapsed signal generation device 20 also includes a reference clock signal forming device 200 that forms and outputs a reference clock signal SCL (described later), a counter 21 that counts the reference clock signal SCL, and a flip-flop that reads the counted value of the counter 21. The counter reading circuit 22 outputs set signals ST1 to ST3 and reset signals R8I to R83, and flip-flops 26 to 28.

Note that the reset signals R81 to R83 are sent to the OR circuit 2 along with the pattern detection signal PDA from the pattern detection device 10.
The signals are inputted to flip-flops 26 to 28 via channels 3 to 25.

Further, the gate device 30 is composed of AND circuits 31 to 33, and includes temporal signals TP1 to TP3, which are set outputs of flip-flops 26 to 28 of the temporal signal generator 20.
and a pattern detection signal PD from the pattern detection device 10.
The logical product is obtained and is inputted to the discrimination device 40 as identification signals ND1 to ND3.

Therefore, this discriminating device 40 uses the banknote dividing point signal NTD.
a delay circuit 41 for delaying , and counters 42 to 42 for counting identification signals ND1 to ND3 from the gate device 30.
44, shift registers 45 to 47 that shift and store the output states of the counters 42 to 44 at that time each time the banknote division point signal NTD is input, and shift registers 45 to 47.
When the content of is a predetermined content, the banknote discrimination signal CNI
- Selector circuits 48 to 50 that output CN3.

Note that the reference clock signal forming circuit 200 generates a reference clock signal SCL with an extremely short period corresponding to the speed of the conveyance mechanism that conveys banknotes. For example, when a banknote is excited by 1 mm by the conveyance mechanism, about 100 It is designed to generate a reference clock signal pulse.

Further, the reason why the three flip-flops 26 to 28 that output the elapsed time signals TPI to TP3 are provided is to identify three denominations of banknotes (-1,000 yen, 5,000 yen, 10,000 yen). The gate device 30 detects that the next pattern detection signal PD is obtained when the elapsed time signals TPI to TP3 are obtained.

Further, the counters 42 to 44 count the identification signals ND1 to ND3 from the gate device 30, and when the counted value reaches the respective predetermined value, the subsequent shift registers 45 to 47 count the identification signals ND1 to ND3 from the gate device 30.
It outputs a pulse signal, and detects whether a predetermined number of consecutive patterns (for example, vertical stripes) are present at a certain interval.

These counters 42 to 44 are reset by a signal obtained by delaying the banknote dividing point signal NTD by the delay circuit 41.
This banknote dividing point signal NTD is separately output when the banknote has moved a predetermined distance after the start of recognition.

Further, the selector circuits 48 to 50 are constituted by decoders that input the binary outputs of the shift registers 45 to 47 in parallel, for example, and convert them into decimal numbers.

On the other hand, as shown in FIG. 2, the reference clock signal generation device 200 includes a synchronization signal generation mechanism 20 that generates a synchronization signal synchronized with the drive operation of the conveyance mechanism section CN that conveys the banknotes 205.
9, a synchronization signal detection circuit 214 that detects a synchronization signal and generates a division signal DS, and a clock signal H that is not synchronized with the drive operation of the transport mechanism section CN and has a shorter period than the synchronization signal.
1 and H2, and a control clock signal CCL, a counter 216 that counts the clock signal H1 while the division signal DS is obtained from the synchronization signal detection circuit 214, and this counter 216.
A latch circuit 217 that stores the counted value CV of
It consists of a counter 218 that generates a reference clock signal SCL and reloads the value of the latch circuit 217 using this reference clock signal SCL, and a control circuit 213 that controls the operation of each of the circuits described above using a control clock signal CCL. Thus, the reference clock signal SC synchronized with the transport mechanism section CN
This is to obtain L.

Here, the conveyance mechanism section CN includes a pair of upper and lower conveyor belts 201.
．． 201A and the pulleys 202, 202A, and are driven by the motor 203.Boo! 7
An identification unit 204 is disposed between 202 and 202A, and the banknote 20 is transported by the transport bell) 20L 201A.
5 is inspected optically or magnetically.

Further, a gear 207 is attached to one of the pulley shafts 206 of the conveyance mechanism section CN, and a permanent magnet 208 as a magnetizing means is disposed near this gear 207. The permanent magnet 208 constitutes a synchronization signal generation mechanism 209 that generates a synchronization signal synchronized with the drive operation of the transport mechanism section CN.

Furthermore, a magnetic head 210 is provided near the gear 207 for detecting the magnetized state as a synchronization signal, and the detection signal is input to a waveform shaping circuit 211 including an amplifier circuit, and after being waveform-shaped, it is sent to a counter. 212.

Thus, when the counter 212 counts two pulses of the synchronization signal, it outputs the division signal DS, and when this division signal DS is input to the control circuit 213, it is cleared by the reset signal R81 to prepare for the next count. This function takes into account the variation error in the pitch of the teeth of the gear 207 and averages out the pitch error.

The magnetic head 210, the waveform shaping circuit 211, and the counter 212 constitute a synchronizing signal detection circuit 214.

On the other hand, the clock signal generation circuit 215 generates the clock signal H1.
and R2 (>Hl) and a control clock signal CCL, and the counter 216 counts this clock signal H1 and is cleared by a reset signal R82 from the control circuit 213.

Further, the latch circuit 217 latches the count value CV of the counter 216 based on the latch signal LT from the control circuit 213, and the counter 218 loads the value latched in the launch circuit 217 based on the load signal LD from the control circuit 213. At the same time, the clock signal H2 from the clock signal generation circuit 215 is counted, and when the counted value reaches the above load value, a coincidence signal is outputted as the reference clock signal SCL.

Note that the latch signal LT is output before the division signal DS is output from the synchronization signal detection circuit 214 and the counter 216 is reset, and the latch signal LT is output from the synchronization signal detection circuit 214 before the counter 216 is reset.
A load signal LD is outputted from the control circuit 213 to the counter 218 by CL, and the value of the latch circuit 217 is loaded into the counter 218 again.

Note that the above-mentioned banknote division point signal NTD is output when the division signal DS is counted after the start of the discrimination operation and the counted value reaches a predetermined value.

Here, first, such reference clock signal forming device 200
The operation will be explained with reference to FIGS. 3A to 3E.

When the transport mechanism section CN is driven by the motor 203, a synchronization signal is generated from the synchronization signal generation mechanism 209, and a synchronization signal as shown in FIG. 3A is input to the counter 212 via the magnetic head 210 and the waveform shaping circuit 211. be done.

The counter 212 outputs the division signal DS to the control circuit 213 when it counts two pulses of the synchronization signal as shown in FIG. Reset signals R8I and R82, launch signal L at the timing of
T, outputs load signal LD.

The clock signal generation circuit 215 also generates a lock signal H1 (for example, 20 KHz) as shown in FIG. 3C, and a lock signal H2 having a higher frequency as shown in the same figure.
(for example, 200 KHz), which are counted by counters 216 and 218, respectively.

Here, when the division signal DS is given to the control circuit 213, the control circuit 213 first resets the counter 212 by the reset signal R8I, and outputs the latch signal LT to change the count value CV of the counter 216 (time tn in this example). '80'') is stored in the launch circuit 217.

Thus, after the count value CV is stored in the latch circuit 217, the control circuit 213 sends the reset signal R to the counter 216.
82 and reset the counter 216.

This operation is performed every time the division signal DS is obtained, and the latch circuit 217 stores a value corresponding to the speed of the transport mechanism section CN.

Therefore, when the counter 218 outputs the reference clock signal SCL (1n), the control circuit 213 outputs the load signal L.
D, the value stored in the latch circuit 217 (“8
0"), and from this time, count the clock signal H2, and when it reaches that load value, the next reference clock signal S
Output CL.

The value of the latch circuit 217 is loaded again by this reference clock signal SCL, and the same operation is repeated thereafter.

Here, in this example, the period of the clock signal H2 is set to 1/10 of the clock signal H1, so the reference clock signal SCL is 1/10 of the time required for two teeth of the gear 207 to pass. One pulse will be output.

In other words, if the conveyance speed remains unchanged, ten pulses of the reference clock signal SCL will be output until the next division signal DS is obtained (FIG. 3E).

Similarly, if the period of the clock signal H2 is set to 1/100, that is, 100 times the frequency of the clock signal H1, a reference clock signal SCL of 100 pulses can be obtained between the division signals DS.

The above description is based on a case where the conveyance speed is constant, but next, a case where the conveyance speed of the conveyance mechanism section CN changes (in this case, it becomes slower) will be explained.

As the transport speed becomes slower, the time required to obtain the next sorting signal DS becomes longer, so the input timing of the reset signal R82 to the counter 216 is delayed from the previous time,
16, the clock signal H1 is counted more than the previous time (for example, '90'').

Then, when the synchronization signal detection circuit 214 outputs the division signal DS, the control circuit 213 outputs the latch signal LT, and the latch circuit 217 outputs the count value CV of the counter 216 (
"90") is stored (time tn+1).

Therefore, the latch circuit 217 receives this new value (“90″
), and when the reference clock signal SCL is output from the counter 218, the counter 218 stores this new value (
"90"), and when the clock signal H2 is counted up to this value, the next reference clock signal SCL is output, but the time required for this is longer than the previous one.

Here, since the speed of the transport mechanism section CN is high and the gear 207 is also rotating at a high speed, the time interval at which the classification signal DS is obtained does not change abruptly even if the transport speed changes.

Therefore, even when the conveyance speed becomes slow, the latch circuit 21
The values stored in 7 gradually increase, and the period of the reference clock signal SCL increases each time the value of the latch circuit 217 is updated (times tn-1, tn, tn+1, etc.).
-...) It gets longer.

Conversely, when the transport speed becomes faster, the period of the reference clock signal SCL becomes shorter.

Thus, the reference clock signal forming device 200 obtains a reference clock signal that is synchronized with the transport speed and has a higher frequency than the division signal.

Next, the operation of the apparatus shown in FIG. 1 will be explained.

When the banknote 205 is sent to the conveyance mechanism unit CN and reaches the position of the identification unit 204, a separate detection means detects this and from this point on outputs the banknote dividing point signal NTD.
Start counting S.

Also, at this time, the counter 21 and the flip-flops 26 to 2
8. Counters 42-44 and shift registers 45-47
are initialized.

On the other hand, the magnetic head 11 of the pattern detection device 10 comes into contact with the surface of the banknote, but since there is no printed pattern (for example, vertical stripes) on the edge of the banknote, no detection signal is obtained yet.

As a result, the bill 205 moves further and the magnetic head 11
When detecting a pattern, the one-shot circuit 1 is activated at the rising edge of the pulse signal WF output from the waveform shaping circuit 12.
3 outputs a pattern detection signal PD with a narrow pulse width, and a pattern detection signal PDA is outputted from the delay circuit 14 with an instantaneous delay, thereby resetting the counter 21 and flip-flops 26 to 28, respectively.

Therefore, the counter 21 is connected to the reference clock signal forming device 2.
Counting the reference clock signal SCL from 00, the counter reading circuit 22 either sets the flip-flops 26-28 at the subsequent stage depending on the count contents of the counter 21, or resets the flip-flops 26-28 via the OR circuits 23-25.

For example, the flip-flop 26 for a 10,000 yen bill is set when the count value of the counter 21 reaches '20', and is reset when the count value reaches +42591, and the 7 flip-flop 2γ for a 5,000 yen bill is It is set when the count value reaches '30'', and
It is reset when it reaches 113.511.

Furthermore, the flip-flop 28 for the 10,000 yen bill is set when the count value of the counter 21 reaches 25''';
28 It is reset when it becomes I+.

Now, the counter 21 outputs a reference clock signal SC of 24 pulses.
When the next pattern is detected by the magnetic head 11 when L is counted, the one-shot circuit 13 outputs a pattern detection signal PD, but since only the flip-flop 26 is set, this pattern detection signal PD is It passes only through the circuit 31, thereby incrementing the counter 42.

Further, the delayed pattern detection signal PDA from the delay circuit 14 is used to control the counter 21 and the flip-flops 26 to 28.
are respectively reset, and the counter 21 starts counting again from °'0'.

If the next pattern detection signal PD is obtained after counting 23 pulses, only the counter 42 increments again.

In this way, when the count of the counter 42 reaches a predetermined value (for example, "6"), an "H" level signal is output to the shift register 45 at the subsequent stage, and the bill 205
is shifted by the banknote dividing point signal NTD when the banknote is moved a predetermined distance.

Immediately after that, the counter 42 is reset by the output from the delay circuit 41 and starts counting again from 0''.

Similarly, rHJ
The level signal or "L" level signal is sent to the shift register 46
, 47, respectively.

Therefore, if all banknote dividing point signals NTD are obtained,
The selector circuits 48 to 50 determine whether or not the contents of the shift registers 45 to 47 at that time are the same as predetermined contents.
Output CN3.

The same applies to other denominations (round dried yen banknotes, 10,000 yen banknotes).

Note that the banknote discrimination signals CN1 to CN3 are provided by the selector circuit 48.
50, and if it is not obtained from any of the selector circuits 48 to 50, it is identified as a counterfeit bill.

As described above, according to the present invention, time is measured from when one pattern detection signal is obtained, and whether or not the next pattern detection signal is obtained after a predetermined period of time that takes into account changes in the conveyance speed of banknotes is determined. This method determines the intervals between the patterns on banknotes, making it possible to identify them with extremely high accuracy.

Although magnetic means are used as the pattern detection device in the above-described embodiments, it is also possible to detect the pattern using optical means.

In addition, the time-lapse signal generator is not limited to the one shown in the embodiment, and in short, every time the detection signal from the pattern detection device is input, a pulse signal of a predetermined width is applied to the banknote conveying speed from the time of input. It may be of any kind as long as it is output after a corresponding predetermined period of time has elapsed.

Furthermore, if a computer is used, the output of the counter of the discriminator may be temporarily stored in a latch section, and the content of the latch section may be read by a command from a CPU (microprocessor), and the discrimination may be made within the CPU. .

On the other hand, the above-mentioned embodiment is configured to identify one side of a banknote, but in order to identify both the front and back sides, another set of the same device, that is, is installed to be able to detect both sides of the transported banknote. That's fine.

[Brief explanation of the drawing]

FIG. 1 is a circuit configuration diagram showing an embodiment of the present invention, FIG. 2 is a configuration diagram showing an example of a reference clock signal forming device used in this invention, and FIGS. 3A to 3E are diagrams for explaining its operation. This is a time chart. 10... Pattern detection device, 11...
Magnetic head, 12... Waveform shaping circuit, 13...
...-One-shot circuit, 14... Delay circuit, 20... Time-lapse signal generator, 21...
・Counter, 22... Counter reading circuit, 23
~25...OR circuit, 26~28...
Flip-flop, 200...-Reference clock signal forming device, 204... Identification section, 205...
...Banknote, 209...Synchronization signal generation mechanism, 2
14... Synchronous signal detection circuit, 215...
・Clock signal generation circuit, 30...-gate device, 31-33...AND circuit, 40...
・Discrimination device, 41... Delay circuit, 42-44.
...Counter, 45-47...Shift register, 48-50...Selector circuit.

Claims (1)

[Claims] 1 A pattern detection device for detecting a pattern on a banknote, and each time a pattern detection signal obtained from this pattern detection device is input, a time-lapse signal of a predetermined time width is transmitted from the time of input of the pattern detection signal to the conveyance of the banknote. The device includes a time-lapse signal generation device that generates a signal after a predetermined time period corresponding to the speed, and a gate device that detects that the next detection signal is obtained while the time-lapse signal is being generated. A banknote identification device characterized in that a banknote can be identified by determining the frequency of a pattern on the banknote.